Chip sorting and grouping method based on simulated annealing algorithm and related device

Abstract

The embodiment of the invention discloses a chip sorting and grouping method based on a simulated annealing algorithm and a related device, and the method comprises the steps: obtaining a plurality of chips to be sorted and the parallel number of the chips, and setting the annealing parameters of the simulated annealing algorithm; calculating a target group number to be grouped according to the plurality of chips to be sorted and the parallel number of the chips; executing the simulated annealing algorithm according to the annealing parameters so as to sort the plurality of chips to be sorted to obtain a target sequence; and dividing the plurality of chips to be sorted into the chip parallel groups with the target group number according to the target sequence. By adopting the embodiment of the invention, the current balance degree among multiple chips connected in parallel can be improved, so that higher reliability and longer service life are provided for a power electronic system.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor chips, and particularly to a chip sorting and grouping method and related device based on an annealing algorithm. Background Art

[0002] With the wide application of semiconductor devices in the fields of rail transit, industrial frequency conversion, new energy, etc., the power of converters is continuously increasing, and a single chip can no longer meet the requirements. Usually, multiple chips are connected in parallel to increase the capacity of the power module. However, due to material defects and immature processes, there are certain differences in device parameters between chips. These differences will cause uneven current distribution between parallel modules. Severe current sharing imbalance will cause some modules to be overloaded and overheated, thereby reducing the reliability and lifespan of the system. Therefore, chip screening has important application value in optimizing the current sharing characteristics of power modules, providing higher reliability and longer lifespan for power electronic systems. Summary of the Invention

[0003] An embodiment of the present application provides a chip sorting and grouping method and related device based on an annealing algorithm, which is beneficial to improving the current balance degree between multiple parallel chips, thereby providing higher reliability and longer lifespan for power electronic systems.

[0004] In a first aspect of an embodiment of the present application, a chip sorting and grouping method based on an annealing algorithm is provided. The method includes: Obtaining multiple chips to be sorted, the number of parallel chips, and setting annealing parameters of the annealing algorithm; Calculating the target number of groups to be grouped according to the multiple chips to be sorted and the number of parallel chips; Executing the annealing algorithm according to the annealing parameters to sort the multiple chips to be sorted to obtain a target order; Dividing the multiple chips to be sorted into chip parallel groups of the target number of groups according to the target order.

[0005] Optionally, the annealing parameters include an initial temperature, a termination temperature, a temperature reduction coefficient, and the target number of iterations at each temperature. The executing the annealing algorithm according to the annealing parameters to sort the multiple chips to be sorted to obtain a target order includes: Calculating the current temperature according to the initial temperature and the temperature reduction coefficient; Determining whether the current temperature is greater than the termination temperature; If the current temperature is greater than or equal to the termination temperature, execute the iterative algorithm with the target number of iterative steps according to the candidate order determined at the previous temperature to sort the multiple chips to be sorted, obtain the candidate order at the current temperature, and perform the step of calculating the current temperature according to the initial temperature and the temperature decrease coefficient; If the current temperature is less than the termination temperature, use the candidate order determined at the previous temperature as the target order.

[0006] Optionally, the step of executing the iterative algorithm with the target number of iterative steps according to the candidate order determined at the previous temperature to sort the multiple chips to be sorted and obtain the candidate order at the current temperature includes: Determine whether the current number of iterative steps is less than or equal to the target number of iterative steps; If the current number of iterative steps is less than or equal to the target number of iterative steps, determine the order of the multiple chips to be sorted at the current number of iterative steps, and the order of the multiple chips to be sorted at the initial number of iterative steps is the candidate order determined at the previous temperature; Perturb the order of the multiple chips to be sorted at the current number of iterative steps to obtain a new order of the multiple chips to be sorted at the current number of iterative steps; Calculate the first fitness function value of the order of the multiple chips to be sorted at the current number of iterative steps and the second fitness function value of the new order of the multiple chips to be sorted at the current number of iterative steps according to the fitness function; When the difference between the second fitness function value and the first fitness function value is less than 0, use the new order of the multiple chips to be sorted at the current number of iterative steps as the order of the multiple chips to be sorted at the next number of iterative steps; Assign the next number of iterative steps to the current number of iterative steps, and perform the step of determining whether the current number of iterative steps is less than or equal to the target number of iterative steps; If the current number of iterative steps is greater than the target number of iterative steps, use the order of the multiple chips to be sorted at the previous number of iterative steps as the candidate order at the current temperature.

[0007] Optionally, the method further includes: When the difference between the second fitness function value and the first fitness function value is greater than or equal to 0, judge whether to use the new order as the order of the multiple chips to be sorted at the next number of iterative steps according to the Metropolis criterion, and the Metropolis criterion is with a probability Use the new order as the order of the multiple chips to be sorted at the next number of iterative steps, where T is the current temperature, is the difference between the second fitness function value and the first fitness function value.

[0008] Optionally, the first fitness function value for calculating the order of the multiple chips to be sorted at the current iteration step according to the fitness function and the second fitness function value for the new order of the multiple chips to be sorted at the current iteration step include: Dividing the multiple chips to be sorted into chip parallel groups of the target number of groups according to the order of the multiple chips to be sorted at the current iteration step, and dividing the multiple chips to be sorted into new chip parallel groups of the target number of groups according to the new order of the multiple chips to be sorted at the current iteration step; Calculating the first fitness function value of the chip parallel group according to the fitness function, and calculating the second fitness function value of the new chip parallel group according to the fitness function, where the fitness function is the sum of variances of chip parameters within each chip parallel group.

[0009] Optionally, the number of the multiple chips to be sorted is m, the number of parallel chips is n, and both m and n are integers greater than 0; When the remainder of n divided by m is 0, the fitness function is:

[0010] When the remainder of n divided by m is not 0, the fitness function is:

[0011] Wherein, , is the device parameter of the j-th chip in the i-th group, is the average value of the device parameters of the chips in the i-th group, and X is the order of the multiple chips to be sorted.

[0012] Optionally, the device parameter is the threshold voltage and / or the on-resistance.

[0013] The second aspect of the embodiments of the present application provides a chip sorting and grouping device based on the simulated annealing algorithm. The device includes: A data acquisition unit, configured to acquire multiple chips to be sorted and the number of parallel chips, and set annealing parameters of the simulated annealing algorithm; A group number calculation unit, configured to calculate the target number of groups to be grouped according to the multiple chips to be sorted and the number of parallel chips; A chip sorting unit, configured to execute the simulated annealing algorithm according to the annealing parameters to sort the multiple chips to be sorted to obtain a target order; A chip grouping unit, configured to divide the multiple chips to be sorted into chip parallel groups with the target number of groups according to the target order.

[0014] A third aspect of the embodiments of the present application provides an electronic device, including: a processor and a memory; The processor is connected to the memory. Among them, the memory is used to store a computer program, and the processor is used to call the computer program to execute the method in the first aspect of the embodiments of the present application.

[0015] A fourth aspect of the embodiments of the present application provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by a processor, the method in the first aspect of the embodiments of the present application is executed.

[0016] The present application calculates the target number of groups to be grouped according to the multiple chips to be sorted and the number of parallel chips, and executes the simulated annealing algorithm according to the annealing parameters to sort the multiple chips to be sorted to obtain the target order; finally, divide the multiple chips to be sorted into chip parallel groups with the target number of groups according to the target order. It can be seen that the embodiments of the application realize the sorting and grouping of chips through the simulated annealing algorithm, which is beneficial to improving the current balance degree among multiple parallel chips, thereby providing higher reliability and longer service life for the power electronic system. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 Shows a schematic diagram of the operating environment of an application program for chip sorting and grouping based on the simulated annealing algorithm provided by an embodiment of the present application; Figure 2 Shows a schematic flowchart of a method for chip sorting and grouping based on the simulated annealing algorithm provided by an embodiment of the present application; Figure 3 Shows a schematic structural diagram of a device for chip sorting and grouping based on the simulated annealing algorithm provided by an embodiment of the present application; Figure 4 Shows a schematic structural diagram of a computer device provided by an embodiment of the present application. Detailed Embodiments

[0019] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the protection scope of the present application.

[0020] Please refer to Figure 1 , which shows a schematic diagram of the operating environment of a chip sorting and grouping application based on the simulated annealing algorithm provided by an embodiment of the present application. The operating environment of this application may include: a terminal 10 and a server 20.

[0021] The terminal 10 includes, but is not limited to, electronic devices such as mobile phones, computers, intelligent voice interaction devices, intelligent home appliances, vehicle-mounted terminals, game consoles, e-book readers, multimedia playback devices, and wearable devices. The client of the application program may be installed in the terminal 10.

[0022] In the embodiments of the present application, the above application program may be any application program that can provide chip sorting and grouping services based on the simulated annealing algorithm. Typically, this application program is an industrial application program. Of course, in addition to industrial application programs, other types of application programs may also provide services that rely on chip sorting and grouping based on the simulated annealing algorithm. For example, scientific research application programs, browser application programs, virtual reality (VR) application programs, augmented reality (AR) application programs, etc., and the embodiments of the present application do not make any limitations in this regard. The embodiments of the present application do not make any limitations in this regard. Optionally, the client of the above application program runs in the terminal 10.

[0023] The server 20 is used to provide background services for the client of the application program in the terminal 10. For example, the server 20 may be the background server of the above application program. The server 20 may be an independent physical server, or a server cluster or distributed system composed of multiple physical servers. It may also be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. Optionally, the server 20 provides background services for the application programs in multiple terminals 10 at the same time.

[0024] Optionally, the terminal 10 and the server 20 can communicate with each other through the network 30. The terminal 10 and the server 20 can be directly or indirectly connected through wired or wireless communication methods, and the present application does not make any restrictions in this regard.

[0025] Please refer to Figure 2 which shows a schematic flow diagram of a chip sorting and grouping method based on the simulated annealing algorithm provided by an embodiment of the present application. This method can be applied to a computer device, where the computer device refers to an electronic device with data calculation and processing capabilities. For example, the execution entity of each step can be Figure 1 the terminal 10 or the server 20 in the application program running environment shown. This method may include the following steps: Step 201: Obtain a plurality of chips to be sorted, the parallel number of the chips, and set the annealing parameters of the simulated annealing algorithm.

[0026] Exemplarily, the simulated annealing algorithm (SA) is a general probabilistic heuristic search algorithm used to find the global optimal solution in a large search space. It draws on the annealing process in physics, that is, the process of heating a metal material to a high temperature and then slowly cooling it to reach the lowest energy state.

[0027] Exemplarily, the annealing parameters include the initial temperature , the termination temperature , the temperature reduction coefficient and the target number of iteration steps at each temperature , then the current temperature can be calculated according to the previous temperature or the current number of times . For example, the temperature calculated for the first time is , the temperature calculated for the second time is , the temperature calculated for the third time is , and so on, until is less than , where.

[0028] Step 202: Calculate the target number of groups to be grouped according to the plurality of chips to be sorted and the parallel number of the chips.

[0029] Exemplarily, the number of the plurality of chips to be sorted is m, the parallel number of the chips is n, and both m and n are integers greater than 0. Then the target number of groups to be grouped is .

[0030] Step 203: Execute the simulated annealing algorithm according to the annealing parameters to sort the plurality of chips to be sorted and obtain the target order.

[0031] Specifically, the executing the simulated annealing algorithm according to the annealing parameters to sort the plurality of chips to be sorted and obtain the target order includes: Calculate the current temperature according to the initial temperature and the temperature decrease coefficient; Determine whether the current temperature is greater than the termination temperature; If the current temperature is greater than or equal to the termination temperature, execute the iterative algorithm for the target number of iterative steps according to the candidate order determined at the previous temperature to sort the multiple chips to be sorted, obtain the candidate order at the current temperature, and execute the step of calculating the current temperature according to the initial temperature and the temperature decrease coefficient; If the current temperature is less than the termination temperature, use the candidate order determined at the previous temperature as the target order.

[0032] Among them, the initial temperature The order of randomly generating multiple chips to be sorted is used as the candidate order.

[0033] Further, the step of executing the iterative algorithm for the target number of iterative steps according to the candidate order determined at the previous temperature to sort the multiple chips to be sorted and obtain the candidate order at the current temperature includes: Determine whether the current number of iterative steps is less than or equal to the target number of iterative steps; If the current number of iterative steps is less than or equal to the target number of iterative steps, determine the order of the multiple chips to be sorted at the current number of iterative steps, and the order of the multiple chips to be sorted at the initial number of iterative steps is the candidate order determined at the previous temperature; Perturb the order of the multiple chips to be sorted at the current number of iterative steps to obtain a new order of the multiple chips to be sorted at the current number of iterative steps; Calculate the first fitness function value of the order of the multiple chips to be sorted at the current number of iterative steps and the second fitness function value of the new order of the multiple chips to be sorted at the current number of iterative steps according to the fitness function; When the difference between the second fitness function value and the first fitness function value is less than 0, use the new order of the multiple chips to be sorted at the current number of iterative steps as the order of the multiple chips to be sorted at the next number of iterative steps; Assign the next number of iterative steps to the current number of iterative steps, and execute the step of determining whether the current number of iterative steps is less than or equal to the target number of iterative steps; If the current number of iterative steps is greater than the target number of iterative steps, use the order of the multiple chips to be sorted at the previous number of iterative steps as the candidate order at the current temperature.

[0034] Further, the method further includes: When the difference between the second fitness function value and the first fitness function value is greater than or equal to 0, it is determined according to the Metropolis criterion whether to use the new order as the order of the multiple chips to be sorted at the next iteration step, and the Metropolis criterion is with a probability Use the new order as the order of the multiple chips to be sorted at the next iteration step, where T is the current temperature, is the difference between the second fitness function value and the first fitness function value.

[0035] Among them, the order of the multiple chips to be sorted at the current iteration step is the order of the multiple chips to be sorted at the previous iteration step.

[0036] Among them, the perturbation can be, for example, randomly swapping the positions of one or several chips.

[0037] Among them, the fitness function is a key component used to evaluate the quality of candidate solutions in optimization algorithms. In different optimization problems, the specific form of the fitness function will be different, but its basic role is to quantify the quality or performance of candidate solutions.

[0038] For example, the current iteration step l The order of the multiple chips to be sorted is X, and after perturbation, the new order of the multiple chips to be sorted at the current iteration step is Xnew. If , then let X = Xnew, and use Xnew as the order of the multiple chips to be sorted at the next iteration step l + 1, and then determine whether l + 1 is less than or equal to L for iteration. If , then with a probability Let X = Xnew, and use Xnew as the order of the multiple chips to be sorted at the next iteration step l + 1.

[0039] Specifically, calculating the first fitness function value of the order of the multiple chips to be sorted at the current iteration step and the second fitness function value of the new order of the multiple chips to be sorted at the current iteration step according to the fitness function includes: Dividing the multiple chips to be sorted into chip parallel groups of the target number of groups according to the order of the multiple chips to be sorted at the current iteration step, and dividing the multiple chips to be sorted into new chip parallel groups of the target number of groups according to the new order of the multiple chips to be sorted at the current iteration step; Calculate the first fitness function value of the chip parallel group according to the fitness function, and calculate the second fitness function value of the new chip parallel group according to the fitness function, where the fitness function is the sum of variances of chip parameters within each chip parallel group.

[0040] Exemplarily, when the remainder of n divided by m is 0, the fitness function is:

[0041] When the remainder of n divided by m is not 0, the fitness function is:

[0042] Where, , is the device parameter of the j-th chip in the i-th group, is the average value of the device parameters of the i-th group of chips, and X is the order of multiple chips to be sorted.

[0043] Exemplarily, the device parameter is the threshold voltage and / or on-resistance. The threshold voltage is an important parameter in semiconductor devices, especially in field-effect transistors (FETs). The threshold voltage refers to the minimum voltage applied between the gate and the source, which enables the channel region to start conducting, thereby allowing current to flow from the drain to the source. The on-resistance is the resistance between the drain and the source of a field-effect transistor (FET) in the conducting state. It is one of the important parameters for measuring the performance of a MOSFET in the conducting state. The lower the on-resistance, the smaller the voltage drop across the MOSFET and the lower the power consumption under the same current.

[0044] Step 204: Divide the multiple chips to be sorted into chip parallel groups of the target number of groups according to the target order.

[0045] This application calculates the target number of groups to be grouped according to multiple chips to be sorted and the parallel number of chips, and executes the simulated annealing algorithm according to the annealing parameters to sort the multiple chips to be sorted to obtain the target order; finally, divide the multiple chips to be sorted into chip parallel groups of the target number of groups according to the target order. It can be seen that the application embodiment realizes the sorting and grouping of chips through the simulated annealing algorithm, which is beneficial to improving the current balance among parallel multiple chips, thereby providing higher reliability and longer service life for the power electronic system.

[0046] Figure 3The structural schematic diagram of a chip sorting and grouping device based on a simulated annealing algorithm provided by an embodiment of the present application is shown. The device includes: A data acquisition unit 301, configured to acquire a plurality of chips to be sorted and the parallel number of the chips, and set annealing parameters of the simulated annealing algorithm; A group number calculation unit 302, configured to calculate a target number of groups to be grouped according to the plurality of chips to be sorted and the parallel number of the chips; A chip sorting unit 303, configured to execute the simulated annealing algorithm according to the annealing parameters to sort the plurality of chips to be sorted to obtain a target order; A chip grouping unit 304, configured to divide the plurality of chips to be sorted into chip parallel groups of the target number of groups according to the target order.

[0047] Figure 4 The structural schematic diagram of a computer device provided by an embodiment of the present application is shown, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it realizes the functions of a computer system for the chip sorting and grouping method based on the simulated annealing algorithm in any of the above embodiments.

[0048] An embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by the computer, the computer realizes the functions of a computer system for the chip sorting and grouping method based on the simulated annealing algorithm in any of the above embodiments.

[0049] An embodiment of the present application further provides a computer program product including instructions. When the instructions are executed by the computer, the computer realizes the functions of a computer system for the chip sorting and grouping method based on the simulated annealing algorithm in any of the above embodiments.

[0050] It can be understood that the specific examples in the present application are only for helping those skilled in the art better understand the embodiments of the present application, rather than limiting the scope of the present invention.

[0051] It can be understood that in various embodiments of the present application, the magnitudes of the sequence numbers of the processes do not mean the sequence of execution. The execution sequence of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0052] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0053] Unless otherwise specified, all technical and scientific terms used in the embodiments of this application have the same meanings as those commonly understood by those skilled in the technical field of this application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more of the related listed items. The singular forms "a", "above", and "the" used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise.

[0054] It can be understood that the processor in the embodiments of this application can be an integrated circuit chip with the ability to process signals. In the implementation process, each step of the above method embodiments can be completed by the integrated logic circuit in the hardware of the processor or by instructions in software form. The above-mentioned processor can be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute each method, step, and logic block diagram disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of this application can be directly embodied as being executed and completed by a hardware decoding processor, or can be executed and completed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0055] It can be understood that the memory in the embodiments of this application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0056] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. A professional technician can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0057] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0058] In several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be electrical, mechanical, or other forms.

[0059] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place, or can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0060] In addition, the functional units in each embodiment of this application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0061] If a function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0062] The above are only specific implementation manners of this application, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A chip sorting and grouping method based on simulated annealing algorithm, characterized in that: The method comprises: Obtaining multiple chips to be sorted and the number of chips in parallel, and setting annealing parameters of a simulated annealing algorithm; Calculating a target number of groups to be grouped according to the plurality of chips to be sorted and the number of chips connected in parallel; Executing the simulated annealing algorithm according to the annealing parameters to sort the plurality of chips to be sorted to obtain a target order; The plurality of chips to be sorted are divided into the target number of chip parallel groups according to the target order.

2. The method according to claim 1, characterized in that The annealing parameters include an initial temperature, an end temperature, a temperature drop coefficient, and a target number of iteration steps at each temperature. The simulated annealing algorithm is executed according to the annealing parameters to sort the plurality of chips to be sorted to obtain a target order, including: Calculate the current temperature according to the initial temperature and the temperature drop coefficient; Determining whether the current temperature is greater than the termination temperature; If the current temperature is greater than or equal to the termination temperature, the iterative algorithm of the target number of iterations is executed according to the candidate sequence determined at the previous temperature to sort the multiple chips to be sorted, obtain the candidate sequence at the current temperature, and execute the step of calculating the current temperature according to the initial temperature and the temperature drop coefficient; If the current temperature is lower than the termination temperature, the candidate sequence determined at the previous temperature is used as the target sequence.

3. The method according to claim 2, characterized in that The iterative algorithm of the target number of iterations is executed according to the candidate sequence determined at the previous temperature to sort the multiple chips to be sorted and obtain the candidate sequence at the current temperature, including: Determine whether the current iteration step number is less than or equal to the target iteration step number; If the current iteration step is less than or equal to the target iteration step, the order of the plurality of chips to be sorted under the current iteration step is determined, and the order of the plurality of chips to be sorted under the initial iteration step is the candidate order determined at the previous temperature; Perturbing the order of the plurality of chips to be sorted at the current iteration step number to obtain a new order of the plurality of chips to be sorted at the current iteration step number; Calculating, according to the fitness function, a first fitness function value of the order of the plurality of chips to be sorted at the current iteration step and a second fitness function value of the new order of the plurality of chips to be sorted at the current iteration step; When the difference between the second fitness function value and the first fitness function value is less than 0, the new order of the plurality of chips to be sorted at the current iteration step is used as the order of the plurality of chips to be sorted at the next iteration step; Assigning the next iteration step number to the current iteration step number, and executing the step of determining whether the current iteration step number is less than or equal to the target iteration step number; If the current iteration step number is greater than the target iteration step number, the order of the plurality of chips to be sorted at the previous iteration step number is used as a candidate order at the current temperature.

4. The method according to claim 3, characterized in that The method further comprises: When the difference between the second fitness function value and the first fitness function value is greater than or equal to 0, whether to use the new order as the order of the plurality of chips to be sorted in the next iteration step is determined according to the Metropolis criterion, wherein the Metropolis criterion is based on probability The new order is used as the order of the plurality of chips to be sorted in the next iteration step, wherein T is the current temperature, is the difference between the second fitness function value and the first fitness function value.

5. The method according to claim 3, characterized in that: The step of calculating, according to the fitness function, a first fitness function value of the order of the plurality of chips to be sorted at the current iteration step and a second fitness function value of the new order of the plurality of chips to be sorted at the current iteration step includes: Dividing the plurality of chips to be sorted into the target number of chip parallel groups according to the order of the plurality of chips to be sorted at the current iteration step number, and dividing the plurality of chips to be sorted into the target number of new chip parallel groups according to the new order of the plurality of chips to be sorted at the current iteration step number; A first fitness function value of the chip parallel group is calculated according to a fitness function, and a second fitness function value of the new chip parallel group is calculated according to a fitness function, wherein the fitness function is the sum of the variances of the chip parameters in each chip parallel group.

6. The method according to claim 4, characterized in that The number of the plurality of chips to be sorted is m, the number of the chips connected in parallel is n, and both m and n are integers greater than 0; When the remainder of n divided by m is 0, the fitness function is: When the remainder of n divided by m is not 0, the fitness function is: in, , is the device parameter of the jth chip in the i-th group, is the average value of the device parameters of the i-th group of chips, and X is the order of the multiple chips to be sorted.

7. The method according to claim 6, characterized in that The device parameters are threshold voltage and / or on-resistance.

8. A chip sorting and grouping device based on simulated annealing algorithm, characterized in that: The device comprises: A data acquisition unit, used to acquire a plurality of chips to be sorted and the number of chips in parallel, and to set annealing parameters of a simulated annealing algorithm; A group number calculation unit, used for calculating the target number of groups to be grouped according to the plurality of chips to be sorted and the number of chips connected in parallel; A chip sorting unit, configured to execute the simulated annealing algorithm according to the annealing parameters to sort the plurality of chips to be sorted to obtain a target order; The chip grouping unit is used to group the plurality of chips to be sorted into chip parallel groups of the target number according to the target order.

9. An electronic device, characterized in that: include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to call the computer program to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the method according to any one of claims 1 to 7 is executed.

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