Standard unit layout method and device
By establishing a standard unit layout area model, the problem of inaccurate area prediction in standard unit layout is solved, and rapid and accurate layout efficiency and accuracy are improved.
Patent Information
- Application Number
- CN202510039279.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-10
- Publication Date
- 2025-05-30
AI Technical Summary
In the prior art, it is difficult to accurately predict the area of standard units under different layout methods when laying standard units, resulting in limited layout accuracy and speed.
By analyzing the standard unit area corresponding to the number of MOS tubes under different layout methods, a matrix of standard unit area and layout times is generated, in-group variation and intergroup variation are verified, and a standard unit layout area model is established to predict the standard unit area under different layout methods.
It realizes the rapid and accurate acquisition of standard unit area, improves the efficiency and accuracy of standard unit layout, and saves time in obtaining standard unit area.
Smart Images
Figure CN120068776A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of integrated circuit technology, and particularly relates to a layout method and device for standard cells. Background Art
[0002] A standard cell is a basic building block in digital integrated circuit design. Standard cells include various types such as inverters, AND gates, registers, selectors, full adders, etc. Each standard cell corresponds to multiple different sizes.
[0003] Standard cell layout refers to calling pre-designed functional units from a library, arranging them in rows, leaving a certain wiring area between rows. These functional units generally have a rectangular shape, with the same height for each unit but different widths. The width of the unit varies with the complexity of the unit function, and the power supply lines and ground lines of all units are in the same position.
[0004] In the prior art, when laying out the same pair of standard cells, it is necessary to estimate the area of the standard cells in a certain layout manner. However, the area of the standard cells in a certain layout is affected by different splicing methods and different wiring methods of the standard cells, resulting in different area results and thus affecting the accuracy of the layout.
[0005] Therefore, it is necessary to design a method for predicting the area of standard cells in a certain layout manner to improve the accuracy and speed of standard cell layout. Summary of the Invention
[0006] This application discloses a layout method and device for standard cells, which can save the time for obtaining the area of standard cells and improve the layout efficiency and accuracy of standard cells.
[0007] Other objects and advantages of this application can be further understood from the technical features disclosed in this application.
[0008] To achieve one or part or all of the above objects or other objects, a layout method for standard cells provided by a technical solution of the present invention includes: based on the layout manner of standard cells, obtaining the number of MOS transistors in different layout manners, obtaining the area of standard cells corresponding to different numbers of MOS transistors when laying out a single type of standard cell, the areas of standard cells corresponding to different numbers of MOS transistors being a set of values, performing multiple layouts in the same layout manner to generate a matrix of standard cell area and layout times; verifying the within-group variation and between-group variation of the multiple sets of values in the generated matrix of standard cell area and layout times; when the within-group variation and between-group variation of the multiple sets of values meet the preset requirements, establishing a standard cell layout area model, and the standard cell layout area model is used to predict the area of standard cells in different layout manners.
[0009] In one implementation, the method for establishing a standard cell layout area model includes: taking the average of the standard cell values for each number of MOS transistors, and performing linear regression fitting on the average values of the standard cells for multiple numbers of MOS transistors to obtain the standard cell layout area model.
[0010] In one implementation, the method for verifying whether the within-group variation and between-group variation of the multiple groups of values meet the preset requirements includes: calculating the sum of the sum of squares of deviations of all standard cell areas as the between-group variation, and calculating the sum of the sum of squares of deviations of the mean of each standard cell area in each group from the standard cell areas within that group as the within-group variation; determining the test value of the standard cell area based on the between-group variation, within-group variation, number of groups, and total data volume, determining the between-group degrees of freedom and within-group degrees of freedom based on the number of groups and total data volume, and analyzing the distribution of the between-group degrees of freedom and within-group degrees of freedom to determine the critical value; if the probability value that the test value is greater than the critical value meets the preset condition, establish a standard cell layout area model based on the number of MOS transistors of the standard cell and the standard cell area.
[0011] In one implementation, the between-group degrees of freedom is equal to the number of groups minus 1, and the within-group degrees of freedom is equal to the total data volume minus the number of groups.
[0012] In one implementation, the ratio of the between-group variation to the between-group degrees of freedom is used as the between-group mean square, the ratio of the within-group variation to the within-group degrees of freedom is used as the within-group mean square, and the test value is the ratio of the between-group mean square and the within-group mean square.
[0013] In one implementation, the method for obtaining the standard cell area under a single type of standard cell layout includes determining the layout position coordinates of the standard cell for each layout method, and calculating the area of the corresponding standard cell according to the layout position coordinates of the standard cell, where the layout coordinate positions include at least two position coordinates.
[0014] In one implementation, the formulas for determining the between-group variation and the within-group variation are:
[0015]
[0016] where SS 1 represents the between-group variation, SS 2 represents the within-group variation, represents the total mean of the T-group standard cell areas; represents the mean of N standard cell areas in each group, i = 1…5; n i j represents the standard cell area at the i-th row and j-th column in the standard cell area and layout times matrix, j = 1…5.
[0017] Another technical solution of the present invention provides a layout device for the area of standard cells. The layout device is used to implement the layout method of the standard cells described in any one of the above. The device includes: a layout acquisition module, which acquires the areas of standard cells corresponding to different numbers of MOS transistors during the layout of a single type of standard cell, and generates a matrix of standard cell areas and layout times; a layout analysis module, which is used to verify the within-group variation and between-group variation of multiple sets of values in the generated matrix of standard cell areas and layout times; a layout area prediction module, which is used to establish a standard cell layout area model when the within-group variation and between-group variation of the multiple sets of values meet the preset requirements, and the standard cell layout area model is used to predict the areas of standard cells under different layout methods.
[0018] Another technical solution of the present invention provides a computer-readable storage medium, in which program codes are stored, and the program codes are called by a processor to execute the layout method of the standard cells described in any one of the above.
[0019] Another technical solution of the present invention provides an electronic device, including one or more processors; a memory; one or more application programs, wherein the one or more application programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more application programs are configured to execute the layout method of the standard cells described in any one of the above.
[0020] For the above layout method and device of the standard cells, by analyzing multiple sets of standard cell areas, it is determined that there is a strong correlation between the number of MOS transistors and the standard cell area, thereby ensuring the accuracy and reliability of generating the standard cell layout area model, realizing that the standard cell area can be quickly and accurately obtained through the known number of MOS transistors, greatly saving the time for obtaining the standard cell area, and improving the layout efficiency and accuracy of the standard cells.
[0021] To make the above and other purposes, features and advantages of the present application more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes the following detailed description. Description of the Drawings
[0022] To more clearly illustrate the technical solutions in the specific embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0023] Figure 1 It is a schematic flowchart of the layout method of the standard cells in an embodiment.
[0024] Figure 2Schematic diagram of the layout of a standard cell in an embodiment.
[0025] Figure 3 Curve graph of the area analysis model of a standard cell in an embodiment.
[0026] Figure 4 Block diagram of the structure of the layout device of a standard cell in an embodiment. Detailed implementation manners
[0027] The foregoing and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the accompanying drawings. The terms "first", "second", etc. in the description and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing the embodiments of the present application.
[0028] Embodiment 1
[0029] A standard cell is a basic building block in digital integrated circuit design and usually contains one or more MOS transistors. A standard cell can contain different types of MOS transistors, such as NMOS, PMOS or CMOS pairs, and the specific number depends on its function and design requirements. Standard cells can be classified into logic gate cells, flip-flop cells, I / O cells, etc. according to their functions. Logic gate cells such as AND, OR, NOT, etc. usually contain one or two MOS transistors; flip-flop cells such as D flip-flops, JK flip-flops, etc. usually contain multiple MOS transistors to implement the storage function; I / O cells are used for input and output signals and may contain buffer or driver circuits, and also contain multiple MOS transistors. The standard cell layout refers to calling pre-designed functional units from the library and arranging them in rows, with a certain wiring area left between rows. Therefore, different splicing methods and different wiring methods will result in different area results, and different layout methods need to measure the area of the corresponding standard cell separately, resulting in low efficiency.
[0030] In the standard cell layout design, efficiently and accurately measuring the area of standard cells can optimize more flexibly among area, performance, power consumption, and cost. Therefore, in order to improve the layout efficiency and accuracy of standard cells, this embodiment provides a layout method for standard cells. Based on the layout methods of standard cells, the number of MOS transistors under different layout methods is obtained. When obtaining the layout of a single type of standard cell, the area of the standard cell corresponding to different numbers of MOS transistors is obtained. The areas of the standard cells corresponding to different numbers of MOS transistors form a set of values. Through multiple layouts under the same layout method, a matrix of standard cell area and layout times is generated; for multiple sets of values in the generated matrix of standard cell area and layout times, the within-group variation and between-group variation of the multiple sets of values are verified; when the within-group variation and between-group variation of the multiple sets of values meet the requirements, a standard cell layout area model is established, and the standard cell layout area model is used to predict the area of standard cells under different layout methods.
[0031] By analyzing the areas of standard cells corresponding to different numbers of MOS transistors under different layout methods, the strong correlation between the standard cell layout area and the number of MOS transistors is determined, and a standard cell layout area model is established. Thus, the area of the corresponding standard cell can be directly predicted according to the number of MOS transistors, and it is ensured that the predicted area of the standard cell is accurate and reliable, greatly saving the time for obtaining the area of the standard cell and improving the layout efficiency and accuracy of the standard cell.
[0032] The technical solution of the present application will be described in detail below with reference to the accompanying drawings.
[0033] Step S1: Based on the layout methods of standard cells, the number of MOS transistors under different layout methods is obtained. When obtaining the layout of a single type of standard cell, the area of the standard cell corresponding to different numbers of MOS transistors is obtained. The areas of the standard cells corresponding to different numbers of MOS transistors form a set of values. Through multiple layouts under the same layout method, a matrix of standard cell area and layout times is generated. Specifically, through an electronic design automation (EDA) tool, the rectangular layout position coordinates of the standard cell under different layout methods can be measured as ((x1, y1), (x2, y1), (x2, y2), (x1, y2)), and then the area of the corresponding standard cell can be calculated as |(x2 - x1) * (y2 - y1)|. For the sake of convenience of description, several standard cells shown in the example are referred to. Among them, Figure 2 As shown in Figure 2 a shows the layout structure of an Inverter (inverter) standard cell, and this standard cell includes 2 MOS transistors; Figure 2 b shows the layout structure of a logic AND standard cell, and this standard cell includes 4 MOS transistors; Figure 2As shown in c, it is the layout structure of the D flip-flop standard cell. Different standard cells of this type can include 16 MOS transistors, 20 MOS transistors, 30 MOS transistors, etc. By laying out the aforementioned standard cells multiple times and measuring the layout position coordinates of the corresponding standard cells, and calculating their areas, the experimental data shown in Table 1 are obtained (here, the accuracy of the standard cell area is taken to two decimal places):
[0034]
[0035] Table 1
[0036] Referring to Table 1, a 5×5 standard cell area matrix is obtained, and the standard cell area data with different numbers of MOS transistors in each row are taken as a group.
[0037] Step S2: For multiple groups of values in the generated standard cell area and layout times matrix, verify the within-group variation and between-group variation of the multiple groups of values. Among them, the within-group variation represents the difference within the same group of values among the multiple groups of values, and the between-group variation represents the difference between different groups among the multiple groups of values. The methods for verifying the within-group variation and between-group variation of the multiple groups of values include but are not limited to chi-square test, t-test, etc.
[0038] In this embodiment, calculate the mean value of the areas of 5 standard cells in each group and the total mean value of the areas of 25 standard cells to obtain Table 2:
[0039]
[0040] Table 2
[0041] Referring to Table 1 and Table 2, calculate the sum of the squared deviations between the total mean value of the areas of 5 groups of standard cells and the mean values of each group through the following formula as the between-group variation:
[0042]
[0043] Calculate the sum of the squared deviations between the mean values of each row of the areas of 5 groups of standard cells and the areas of 5 standard cells within the corresponding row through the following formula as the within-group variation:
[0044]
[0045] Determine that the between-group degrees of freedom = N - 1 = 4, and the within-group degrees of freedom = N×T - N = 20.
[0046] Determine that the between-group mean square = between-group variation / between-group degrees of freedom v 1 = 0.4958 / 4 = 0.12395.
[0047] Determine that the within-group mean square = within-group variation / within-group degrees of freedom v2 = 410.0662 / 20 = 20.50331.
[0048] Determine the test value F = mean square between groups / mean square within groups = 0.12395 / 20.50331 = 0.006045.
[0049] Select α = 0.05, and according to the distribution of degrees of freedom between groups and degrees of freedom within groups, look up and determine the critical value F in the distribution critical value table 3 α,4,20 = 2.866081.
[0050]
[0051] Table 3
[0052] Furthermore, determine the probability value P through the probability density function. Specifically, the expression of the probability density function is:
[0053]
[0054] where x > 0, B(p, q) represents the beta function, v 1 represents the degrees of freedom between groups, v 2 represents the degrees of freedom within groups.
[0055] Furthermore, the probability value P(F > F α,4,20 ) = 1 - F(0.006045, 4, 20) = 0.999920.
[0056] It can be seen that the probability value P is much greater than α (i.e., 0.999920 > 0.05). Therefore, it is determined that the overall means of the 5 groups of standard cell areas are equal, indicating that there is a strong correlation between the number of MOS transistors in the standard cell and the standard cell area, that is, the within-group variation and between-group variation of multiple groups of standard cell areas meet the preset requirements.
[0057] Step S3: When the within-group variation and between-group variation of multiple groups of numerical values meet the preset requirements, establish a standard cell layout area model, which is used to predict the standard cell area under different layout methods. Among them, according to Step S2, it has been determined that the within-group variation and between-group variation of multiple groups of data meet the preset requirements, so the accuracy and reliability of the standard cell layout area model established based on the data in Table 1 can be determined.
[0058] Specifically, establishing the standard cell layout area model includes: calculating the mean value of the standard cell areas corresponding to the same number of MOS transistors, as shown in Table 4:
[0059]
[0060] Table 4
[0061] According to the data in Table 4 of this embodiment, the expression of the standard cell layout area model obtained by linear regression fitting is specifically:
[0062] y = 0.2732x + 0.6077;
[0063] In the formula, y represents the standard cell area, and x represents the number of MOS transistors; among them, the model fitting degree R 2 = 0.9871 indicates a strong correlation between the standard cell and the number of the MOS transistors.
[0064] More specifically, referring to Figure 3 the linear curve of the standard cell layout area model shown, it can be observed that different numbers of MOS transistors correspond to different standard cell areas. The linear curve obtained in this application basically coincides with the implementation data, that is, the accuracy of the generated standard cell layout area model is relatively high.
[0065] In summary, the method of this application obtains the standard cell areas of different numbers of MOS transistors in different layout manners by performing layout on the standard cells, realizes the verification and analysis of the experimental data using less experimental data, and obtains an accurate and reliable model, avoiding the problem that a large number of layout actions and measurements are required to obtain an accurate model in general. The area data of the required standard cell can be directly read from the model through the model of this application, which is time-saving, labor-saving, accurate and reliable.
[0066] Embodiment 2
[0067] A layout device for a standard cell provided in Embodiment 2 is used to implement the layout method of the standard cell described in any one of the above, as Figure 4 shown, the device includes:
[0068] A layout acquisition module 41, configured to obtain the standard cell areas corresponding to different numbers of MOS transistors when a single type of standard cell is laid out, and generate a matrix of standard cell areas and layout times.
[0069] A layout analysis module 42, configured to verify the within-group variation and between-group variation of multiple groups of values in the generated matrix of standard cell areas and layout times.
[0070] A layout area prediction module 43, configured to establish a standard cell layout area model when the within-group variation and between-group variation of the multiple groups of values meet the preset requirements, and the standard cell layout area model is used to predict the standard cell areas under different layout manners.
[0071] It should be noted that for the information interaction, execution process, etc. among the above-mentioned device modules / units, since they are based on the same concept as the method embodiments of the present application, the technical effects brought by them are the same as those of the method embodiments of the present application. For the specific content, reference can be made to the description in the method embodiments shown above in the embodiments of the present application, and details will not be repeated here. Additionally, it should be noted that the device embodiments described above are merely illustrative, and some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Moreover, in the accompanying drawings of the device embodiments provided in the present application, the connection relationships between the modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines.
[0072] Embodiment 3
[0073] A computer-readable storage medium provided by Embodiment 3 stores program code, and the program code is called by a processor to execute the layout method of the standard cell as described in any one of the above.
[0074] Embodiment 4
[0075] An electronic device provided by Embodiment 4 includes one or more processors; a memory; and one or more application programs, where the one or more application programs are stored in the memory and configured to be executed by the one or more processors, and the one or more application programs are configured to execute the layout method of the standard cell as described in any one of the above.
[0076] It should be pointed out that for those of ordinary skill in the art in the technical field of the present application, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of separate embodiments for clarity can also be provided in a single embodiment by combination. Conversely, the various features of the present disclosure described in the context of a single embodiment for clarity can also be provided separately or in any suitable combination or as any other described embodiment of the present disclosure.
Claims
1. A layout method for a standard cell, characterized in that: The method comprises: Based on the layout mode of the standard cell, the number of MOS tubes under different layout modes is obtained, and when a single type of standard cell layout is obtained, the standard cell area corresponding to different numbers of MOS tubes is obtained. The standard cell areas corresponding to different numbers of MOS tubes are taken as a group of values, and the layout is performed multiple times under the same layout mode to generate a matrix of standard cell area and layout times; For multiple groups of values in the generated matrix of standard cell area and layout times, verifying intra-group variation and inter-group variation of the multiple groups of values; When the intra-group variation and inter-group variation of the plurality of groups of values meet preset requirements, a standard cell layout area model is established, and the standard cell layout area model is used to predict the standard cell areas under different layout modes.
2. A layout method for a standard cell according to claim 1, characterized in that: The method for establishing a standard cell layout area model includes: averaging the standard cell values under each MOS tube quantity, and performing linear regression fitting on the standard cell average values under multiple MOS tube quantities to obtain a standard cell layout area model.
3. A layout method for a standard cell according to claim 1, characterized in that: The method for verifying whether the intra-group variation and inter-group variation of the plurality of groups of values meet the preset requirements includes: The sum of the squared deviations of all standard unit areas was calculated as the inter-group variation, and the sum of the squared deviations of the mean of each standard unit area in each group and the standard unit area in the group was calculated as the intra-group variation; Determine the test value of the standard unit area based on the inter-group variation, the intra-group variation, the number of groups and the total data volume, determine the inter-group degrees of freedom and the intra-group degrees of freedom based on the number of groups and the total data volume, and analyze the distribution of the inter-group degrees of freedom and the intra-group degrees of freedom to determine the critical value; If the probability value that the inspection value is greater than the critical value satisfies a preset condition, a standard cell layout area model is established based on the number of MOS tubes in the standard cell and the area of the standard cell.
4. A layout method for a standard cell according to claim 3, characterized in that: The between-group degrees of freedom are equal to the number of groups minus 1, and the within-group degrees of freedom are equal to the total data amount minus the number of groups.
5. A layout method for a standard cell according to claim 4, characterized in that: The ratio of the inter-group variation to the inter-group degrees of freedom is taken as the inter-group mean square, the ratio of the intra-group variation to the intra-group degrees of freedom is taken as the intra-group mean square, and the test value is the ratio of the inter-group mean square to the intra-group mean square.
6. A layout method for a standard cell according to claim 1, characterized in that: The method for obtaining the area of a standard cell under a single type of standard cell layout includes determining the layout position coordinates of the standard cell under each layout mode, and calculating the area of the corresponding standard cell according to the layout position coordinates of the standard cell, wherein the layout coordinate position includes at least two position coordinates.
7. A layout method for a standard cell according to claim 1 or 3, characterized in that , the formula for determining the inter-group variation and the intra-group variation is: Among them, SS1 represents the between-group variation, SS2 represents the within-group variation, represents the total mean of the standard unit area of group T; Represents the average area of each group of N standard units, i = 1...5; n i j represents the standard cell area in the i-th row and j-th column in the standard cell area and layout frequency matrix, j = 1…5.
8. A layout device of a standard unit area, characterized in that The layout device is used to implement the layout method of the standard cell according to any one of claims 1 to 7, and the device includes: The layout acquisition module generates a matrix of standard cell area and layout times corresponding to the standard cell area of different numbers of MOS tubes when acquiring the layout of a single type of standard cell; A layout analysis module, for verifying intra-group variation and inter-group variation of multiple groups of values in the generated matrix of standard cell area and layout times; The layout area prediction module is used to establish a standard unit layout area model when the intra-group variation and inter-group variation of the multiple groups of values meet preset requirements. The standard unit layout area model is used to predict the standard unit area under different layout modes.
9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program codes, and the program codes are called by a processor to execute the layout method of the standard cell according to any one of claims 1 to 7.
10. An electronic device, characterized in that: comprising one or more processors; Memory; One or more application programs, wherein the one or more application programs are stored in the memory and configured to be executed by the one or more processors, and the one or more application programs are configured to execute the layout method of the standard cell according to any one of claims 1 to 7.