Semiconductor device integrated circuit layout method applied to power supply stability control

Abstract

The invention discloses a semiconductor device integrated circuit layout method applied to power supply stability control, and relates to the field of circuit layout, and the method comprises the steps: building a current loss model in an integrated circuit, building a current delay model in the integrated circuit, and building a current crosstalk model in the integrated circuit; forming at least one preparation layout scheme of the semiconductor device; calculating a comprehensive stability coefficient of the preparation layout scheme; selecting the preparation layout scheme with the maximum comprehensive stability coefficient as a target layout scheme; obtaining at least one local circuit; calculating to obtain a burst coefficient of the local circuit; and a current stabilization point distribution setting scheme of the local circuit is formed. The optimal target layout scheme can be selected by calculating the comprehensive stability coefficient of the preparation layout scheme and forming the current stabilization point distribution setting scheme of the local circuit, and the overall stability of the current in the integrated circuit is ensured when the sudden current appears by arranging the current stabilizers at the current stabilization points.

Description

Technical Field

[0001] The present invention relates to the field of circuit layout, and more particularly to an integrated circuit layout method for semiconductor devices applied to power supply stability control. Background Art

[0002] Automatic placement and routing of integrated circuits is a key step in the physical design of integrated circuits, which involves reasonably placing and connecting billions of transistors and other circuit elements on a chip. This process is crucial for ensuring the performance, power consumption, and manufacturing yield of integrated circuits. When designing an integrated circuit, it is necessary to ensure that the current input to the semiconductor device can reach its rated current as much as possible, thereby ensuring its working efficiency.

[0003] However, in an integrated circuit, the current will decay with the transmission distance. At the same time, when the integrated circuit is very dense, cross-talk will occur between adjacent lines. Moreover, when semiconductor components work for a long time, sudden currents are likely to be induced, all of which will affect the stability of the current in the integrated circuit, and further cause the current of the input semiconductor device not to reach its rated current. Summary of the Invention

[0004] To solve the above technical problems, an integrated circuit layout method for semiconductor devices applied to power supply stability control is provided, and the present technical solution solves the problems raised in the above background art.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] An integrated circuit layout method for semiconductor devices applied to power supply stability control, comprising:

[0007] Obtaining at least one semiconductor device to be integrated, and obtaining the rated current of the semiconductor device;

[0008] Establishing a current loss model in the integrated circuit, establishing a current delay model in the integrated circuit, and establishing a current crosstalk model in the integrated circuit;

[0009] Forming at least one preliminary layout plan for the semiconductor device;

[0010] Calculating the comprehensive stability coefficient of the preliminary layout plan based on the established models;

[0011] Selecting the preliminary layout plan with the maximum comprehensive stability coefficient as the target layout plan;

[0012] Based on the implemented functions, dividing the circuit formed by the target layout plan to obtain at least one local circuit;

[0013] Based on historical data, obtaining the current burst value caused by the semiconductor device, and calculating the burst coefficient of the local circuit;

[0014] Form a setting scheme for the steady current point distribution of the local circuit, and set a steady current regulator at the steady current point;

[0015] Supplement the setting position of the steady current regulator into the target layout scheme as the final layout scheme.

[0016] Preferably, the establishment of the current loss model in the integrated circuit includes the following steps:

[0017] In the integrated circuit, obtain the distance value range from the semiconductor device to the power supply, equally divide the distance value range, and obtain at least one distance point;

[0018] Under the condition that the distance from the semiconductor device to the power supply is equal to the value of the distance point, obtain the first actual current passing through the semiconductor device;

[0019] Divide the first actual current of the semiconductor device by the rated current of the semiconductor device to obtain the actual action ratio;

[0020] Subtract the actual action ratio from 1 to obtain the loss ratio;

[0021] Pair and fit the distance point and the loss ratio to obtain a current loss fitting function, where the distance point is the independent variable and the loss ratio is the dependent variable.

[0022] Preferably, the establishment of the current delay model in the integrated circuit includes the following steps:

[0023] In the integrated circuit, obtain the distance value range from the semiconductor device to the power supply, equally divide the distance value range, and obtain at least one distance point;

[0024] Under the condition that the distance from the semiconductor device to the power supply is equal to the value of the distance point, obtain the time interval when the semiconductor device is triggered after the circuit is closed;

[0025] Pair and fit the distance point and the time interval when the semiconductor device is triggered to obtain a current delay fitting function, where the distance point is the independent variable and the time when the semiconductor device is triggered is the dependent variable.

[0026] Preferably, the establishment of the current crosstalk model in the integrated circuit includes the following steps:

[0027] In the integrated circuit, obtain the interval value range of adjacent circuits, equally divide the interval value range, and obtain at least one identification point;

[0028] Take one of the adjacent circuits as the circuit under test, and take at least one sampling point in the circuit under test;

[0029] Under the condition that the distance between adjacent circuits is equal to the value of the identification point, obtain the second actual current flowing through the sampling point;

[0030] Obtain the distance from the sampling point to the power supply as the characteristic distance, substitute the characteristic distance into the current loss fitting function to obtain the current compensation value;

[0031] Superimpose the second actual current of the sampling point and the current compensation value to obtain the third actual current;

[0032] Based on the position of the line to be measured in the integrated circuit, determine the voltages distributed at both ends of the line to be measured as the actual voltages, and obtain the resistance of the line to be measured as the actual resistance;

[0033] Divide the actual voltage by the actual resistance to obtain the fourth actual current;

[0034] Take the average value of the fourth actual currents at at least one sampling point in the line to be measured to obtain the actual average current;

[0035] Subtract the third actual current from the actual average current to obtain the crosstalk current;

[0036] Pair and fit the value at the identification point with the crosstalk current to obtain the current crosstalk fitting function, where the value at the identification point is the independent variable and the crosstalk current is the dependent variable.

[0037] Preferably, forming at least one preliminary layout plan for the semiconductor device includes the following steps:

[0038] Set at least one series frame on the circuit board integrated with the semiconductor device, and set at least one parallel position within the series frame, such that the number of all parallel positions is consistent with the number of semiconductor devices;

[0039] The distance between adjacent series frames is equal to one of the values in at least one distance point, and the distance between adjacent parallel positions is equal to one of the values in at least one identification point;

[0040] The semiconductor device is installed at the parallel position, and each position setting relationship between the series frame and the parallel position forms a preliminary layout plan.

[0041] Preferably, calculating the comprehensive stability coefficient of the preliminary layout plan based on the established model includes the following steps:

[0042] Based on big data, obtain the total power-on time length during the normal operation of the integrated circuit as the characteristic time length, obtain the number of power-on times before the integrated circuit is scrapped as the characteristic number of times, and divide the characteristic time length by the characteristic number of times to obtain the preset time;

[0043] Substitute the value at the distance point into the current loss fitting function and take the average value to obtain the first average value, and multiply the first average value by the preset time to obtain the loss weight;

[0044] Substitute the value at the recognition point into the current crosstalk fitting function and take the mean to obtain the second mean value. Multiply the second mean value by the preset time to obtain the crosstalk weight.

[0045] Substitute the value at the distance point into the current delay fitting function and take the mean to obtain the third mean value. Multiply the first mean value and half of the second mean value by the third mean value to obtain the delay weight.

[0046] Obtain the position of the semiconductor device in the preliminary layout scheme as the preliminary position.

[0047] Substitute the distance from the preliminary position to the power supply into the current loss fitting function to obtain the preliminary loss value. Take the mean of the preliminary loss values corresponding to at least one preliminary position to obtain the pre-averaged loss value.

[0048] Substitute the distance from the preliminary position to the power supply into the current delay fitting function to obtain the preliminary delay time. Take the mean of the preliminary delay times corresponding to at least one preliminary position to obtain the pre-averaged delay time.

[0049] Obtain the line adjacent to the preliminary position as the target line, and obtain the distance between the target line and the line where the preliminary position is located as the target distance.

[0050] Substitute the target distance into the current crosstalk fitting function to obtain the preliminary crosstalk value. Take the mean of the preliminary crosstalk values corresponding to at least one preliminary position to obtain the pre-averaged crosstalk value.

[0051] Use the circuit synthesis formula to calculate the comprehensive stability coefficient of the preliminary layout scheme.

[0052] The circuit synthesis formula is as follows:

[0053]

[0054] Where A is the comprehensive stability coefficient, b is the loss weight, c is the crosstalk weight, d is the delay weight, B is the pre-averaged loss value, C is the pre-averaged crosstalk value, and D is the pre-averaged delay time.

[0055] Preferably, the steps of dividing the circuit formed by the target layout scheme into at least one local circuit include the following:

[0056] Obtain the line directly between adjacent semiconductor devices in the target layout scheme as the line to be divided.

[0057] During division, divide according to the midpoint of the line to be divided, and divide the circuit formed by the target layout scheme into at least one local circuit block.

[0058] Cluster adjacent local circuit blocks, and the clustered local circuit blocks satisfy that the semiconductor devices included in the local circuit blocks are of the same type.

[0059] Merge the grouped local circuit blocks into a local circuit.

[0060] Preferably, the steps of obtaining the current burst value caused by the semiconductor device and calculating the burst coefficient of the local circuit include the following:

[0061] Classify the semiconductor devices in the local circuit to obtain at least one series classification. The series classification is composed of semiconductor devices. The semiconductor devices in the same series classification are in a parallel relationship, and different series classifications are in a series relationship;

[0062] Superimpose the current burst values caused by the semiconductor devices in the series classification to obtain a burst classification value;

[0063] Take the maximum value of the burst classification values of the series classification as the burst coefficient of the local circuit.

[0064] Preferably, the steps of forming the steady current point distribution setting scheme of the local circuit include the following:

[0065] Based on big data, obtain the upper limit of the mutant current for steady current at the steady current point;

[0066] When the burst coefficient does not exceed the upper limit of the mutant current, obtain a series bus in the local circuit. The series bus connects all the series classifications in the local circuit in series, and take any point on the series bus as the setting position of the steady current point;

[0067] When the burst coefficient is greater than the upper limit of the mutant current, take the series classification with a burst classification value greater than the upper limit of the mutant current as the target series classification;

[0068] Set a steady current point parallel line at both ends of the target series classification. The number of parallel steady current points in the steady current point parallel line is equal to k, where k is the smallest integer not less than e, and e is the deviation value, and e is calculated using the steady current formula;

[0069] Take the midpoint of each parallel line in the steady current point parallel line as the setting position of the steady current point, and take any point on the series bus as the setting position of the steady current point;

[0070] The steady current formula is as follows:

[0071]

[0072] Among them, f is the burst classification value and g is the upper limit of the mutant current.

[0073] Preferably, the steps of supplementing the setting position of the current stabilizer into the target layout scheme as the final layout scheme include the following:

[0074] Supplement the setting position of the current stabilizer into the position of the local circuit in the target layout scheme.

[0075] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0076] By establishing a current loss model in an integrated circuit, a current delay model in an integrated circuit, and a current crosstalk model in an integrated circuit, calculating the comprehensive stability coefficient of a preliminary layout scheme, and forming a steady current point distribution setting scheme for a local circuit, it is possible to take into account the attenuation of current with transmission distance in the integrated circuit, the influence of cross-current between adjacent lines, and the influence of current delay in the circuit. According to their different natures, corresponding weights are formed for comprehensive consideration. Thus, the optimal target layout scheme can be selected. At the same time, in order to reduce the influence of sudden current, the position of the steady current point is set in the integrated circuit, and a current stabilizer is arranged at the steady current point. When sudden current appears, the overall stability of the current in the integrated circuit is ensured. Thus, it is ensured that all semiconductor devices in the integrated circuit can work with a current close to the rated current as much as possible, and further, the working effect of the integrated circuit is ensured. Description of the Drawings

[0077] Figure 1 It is a schematic flow chart of the integrated circuit layout method of a semiconductor device applied to power supply stability control according to the present invention;

[0078] Figure 2 It is a schematic flow chart of establishing a current loss model in an integrated circuit according to the present invention;

[0079] Figure 3 It is a schematic flow chart of establishing a current delay model in an integrated circuit according to the present invention;

[0080] Figure 4 It is a schematic flow chart of establishing a current crosstalk model in an integrated circuit according to the present invention;

[0081] Figure 5 It is a schematic flow chart of forming at least one preliminary layout scheme of a semiconductor device according to the present invention;

[0082] Figure 6 It is a schematic flow chart of calculating the comprehensive stability coefficient of a preliminary layout scheme based on the established model according to the present invention;

[0083] Figure 7 It is a schematic flow chart of dividing the circuit formed by the target layout scheme to obtain at least one local circuit according to the present invention;

[0084] Figure 8 It is a schematic flow chart of obtaining the current burst value caused by a semiconductor device and calculating the burst coefficient of a local circuit according to the present invention;

[0085] Figure 9Schematic flowchart of the setting scheme for the steady current point distribution of the local circuit of the present invention. Detailed implementation manners

[0086] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments in the following description are only examples, and other obvious variations can be conceived by those skilled in the art.

[0087] Referring to Figure 1 As shown, a semiconductor device integrated circuit layout method applied to power supply stability control includes:

[0088] Obtain at least one semiconductor device to be integrated, and obtain the rated current of the semiconductor device;

[0089] Establish a current loss model in the integrated circuit, establish a current delay model in the integrated circuit, and establish a current crosstalk model in the integrated circuit;

[0090] Form at least one preliminary layout scheme of the semiconductor device;

[0091] Based on the established models, calculate the comprehensive stability coefficient of the preliminary layout scheme;

[0092] Select the preliminary layout scheme with the largest comprehensive stability coefficient as the target layout scheme;

[0093] Based on the implemented functions, divide the circuit formed by the target layout scheme to obtain at least one local circuit;

[0094] Based on historical data, obtain the current burst value caused by the semiconductor device, and calculate the burst coefficient of the local circuit;

[0095] Form a setting scheme for the steady current point distribution of the local circuit, and set a current stabilizer at the steady current point;

[0096] Supplement the setting position of the current stabilizer into the target layout scheme as the final layout scheme.

[0097] In this solution, due to the different positions of semiconductor devices and the different positions of circuits in the integrated circuit, there will be slight changes in the current input to the semiconductor devices. However, since the semiconductor devices in the integrated circuit are very small and numerous, the cumulative effect of these slight changes in multiple semiconductor devices will lead to differences in overall performance. Moreover, when the semiconductor devices are operating, current mutations may occur, and the mutated current will affect the operation of the nearby semiconductor devices. As a result, it may cause a temporary performance decline of the integrated circuit. Therefore, in order to handle the above situations, in this solution, a series of algorithms are set to design the layout and limit the position of the current stabilizer, so as to ensure the current stability of the integrated circuit with the least number of current stabilizers.

[0098] Refer to Figure 2 As shown, establishing a current loss model in an integrated circuit includes the following steps:

[0099] In the integrated circuit, obtain the distance value range from the semiconductor device to the power supply, equally divide the distance value range, and obtain at least one distance point;

[0100] Under the condition that the distance from the semiconductor device to the power supply is equal to the value of the distance point, obtain the first actual current passing through the semiconductor device;

[0101] Divide the first actual current of the semiconductor device by the rated current of the semiconductor device to obtain the actual action ratio;

[0102] Subtract the actual action ratio from 1 to obtain the loss ratio;

[0103] Pair and fit the distance point and the loss ratio to obtain a current loss fitting function, where the distance point is the independent variable and the loss ratio is the dependent variable.

[0104] Since the attenuation of the current varies with different distances, therefore, in order to predict the attenuation of the current, it is necessary to establish a suitable model for estimation. Since the thickness of the circuit in the integrated circuit is constant, therefore, the only factor that will cause attenuation of the current is the distance. Thus, the corresponding function can be obtained by fitting.

[0105] Refer to Figure 3 As shown, establishing a current delay model in an integrated circuit includes the following steps:

[0106] In the integrated circuit, obtain the distance value range from the semiconductor device to the power supply, equally divide the distance value range, and obtain at least one distance point;

[0107] Under the condition that the distance from the semiconductor device to the power supply is equal to the value of the distance point, obtain the time interval after the circuit is closed when the semiconductor device is triggered;

[0108] Pair and fit the distance point and the time interval when the semiconductor device is triggered to obtain a current delay fitting function, where the distance point is the independent variable and the time when the semiconductor device is triggered is the dependent variable.

[0109] When the integrated circuit is started, due to the long length of the internal circuit, therefore, there will be a certain delay in the transmission of the current, and the length of the delay will also affect the performance of the integrated circuit. The longer the delay, the greater the room for improvement in the use effect of the integrated circuit, and the delay is determined by the transmission time of the circuit, and thus determined by the transmission distance of the circuit.

[0110] Refer to Figure 4As shown, establishing a current crosstalk model in an integrated circuit includes the following steps:

[0111] In the integrated circuit, obtain the interval value range of adjacent circuits, equally divide the interval value range, and obtain at least one identification point;

[0112] Take one of the adjacent circuits as the circuit under test, and take at least one sampling point in the circuit under test;

[0113] Under the condition that the distance between adjacent circuits is equal to the value at the identification point, obtain the second actual current flowing through the sampling point;

[0114] Obtain the distance from the sampling point to the power supply as the characteristic distance, substitute the characteristic distance into the current loss fitting function, and obtain the current compensation value;

[0115] Superimpose the second actual current of the sampling point and the current compensation value to obtain the third actual current;

[0116] Based on the position of the circuit under test in the integrated circuit, determine the voltages distributed at both ends of the circuit under test as the actual voltages, and obtain the resistance of the circuit under test as the actual resistance;

[0117] Divide the actual voltage by the actual resistance to obtain the fourth actual current;

[0118] Take the average value of the fourth actual currents of at least one sampling point taken in the circuit under test to obtain the actual average current;

[0119] Subtract the third actual current from the actual average current to obtain the crosstalk current;

[0120] Pair and fit the value at the identification point with the crosstalk current to obtain a current crosstalk fitting function, where the value at the identification point is the independent variable and the crosstalk current is the dependent variable.

[0121] When obtaining the crosstalk current, it is necessary to exclude the influence of current attenuation and not calculate the attenuated part of the current into the crosstalk current. Therefore, calculate the third actual current and supplement the attenuated part of the current. Thus, subtract the third actual current from the actual average current to obtain the crosstalk current, and then a current crosstalk fitting function can be fitted.

[0122] Refer to Figure 5 As shown, forming at least one preliminary layout plan for a semiconductor device includes the following steps:

[0123] Set at least one series frame on the circuit board integrated with the semiconductor device, and set at least one parallel position in the series frame, such that the number of all parallel positions is consistent with the number of semiconductor devices;

[0124] The distance adjacent to the series box is equal to one of the values in at least one distance point, and the distance adjacent to the parallel position is equal to one of the values in at least one identification point;

[0125] The semiconductor device is installed at the parallel position, and each positional setting relationship between the series box and the parallel position forms a preliminary layout scheme.

[0126] In an integrated circuit, the semiconductor devices are classified based on the series and parallel relationships of the semiconductor devices. The number of at least one parallel position within the series box is variable, as long as it satisfies that the number of all parallel positions is consistent with the number of semiconductor devices. Thus, when the distance between adjacent series boxes is determined and the distance between adjacent parallel positions is determined, the integrated circuit determines a preliminary layout scheme. Here, the distance between adjacent series boxes is equal to one of the values in at least one distance point, and the distance between adjacent parallel positions is equal to one of the values in at least one identification point. Each time different values are taken, different preliminary layout schemes will be generated.

[0127] Refer to Figure 6 As shown, based on the established model, calculating the comprehensive stability coefficient of the preliminary layout scheme includes the following steps:

[0128] Based on big data, obtain the total power-on time of the integrated circuit during normal operation as the characteristic time length, and obtain the number of power-on times before the integrated circuit is scrapped as the characteristic number of times. Divide the characteristic time length by the characteristic number of times to obtain the preset time;

[0129] Substitute the value at the distance point into the current loss fitting function and take the mean to obtain the first mean value. Multiply the first mean value by the preset time to obtain the loss weight;

[0130] Substitute the value at the identification point into the current crosstalk fitting function and take the mean to obtain the second mean value. Multiply the second mean value by the preset time to obtain the crosstalk weight;

[0131] Substitute the value at the distance point into the current delay fitting function and take the mean to obtain the third mean value. Multiply the third mean value by half of the sum of the first mean value and the second mean value to obtain the delay weight;

[0132] Obtain the position of the semiconductor device in the preliminary layout scheme as the preliminary position;

[0133] Substitute the distance from the preliminary position to the power supply into the current loss fitting function to obtain the preliminary loss value. Take the mean of the preliminary loss values corresponding to at least one preliminary position to obtain the pre-average loss value;

[0134] Substitute the distance from the preliminary position to the power supply into the current delay fitting function to obtain the preliminary delay time. Take the mean of the preliminary delay times corresponding to at least one preliminary position to obtain the pre-average delay time;

[0135] Obtain the line adjacent to the preparatory position as the target line, and obtain the distance between the target line and the line where the preparatory position is located as the target distance;

[0136] Substitute the target distance into the current crosstalk fitting function to obtain the preparatory crosstalk value, and take the average value of the preparatory crosstalk values corresponding to at least one preparatory position to obtain the pre-average crosstalk value;

[0137] Use the circuit synthesis formula to calculate the comprehensive stability coefficient of the preparatory layout scheme;

[0138] The circuit synthesis formula is as follows:

[0139]

[0140] Among them, A is the comprehensive stability coefficient, b is the loss weight, c is the crosstalk weight, d is the delay weight, B is the pre-average loss value, C is the pre-average crosstalk value, and D is the pre-average delay time.

[0141] The setting of the loss weight, crosstalk weight and delay weight here is the most important, because only the reasonable setting of the weights can ensure that the data in the three cases can be reasonably integrated. When setting the weights, it is determined according to their influence on the current within the preset time. For loss, within the preset time, its overall influence is the product of the first mean value and the preset time. For crosstalk, within the preset time, its overall influence is the product of the second mean value and the preset time. For delay, it has no influence on the magnitude of the current, but it has an influence on the preset time. Because due to the delay, when the power is off and then on, the current will be delayed for a period of time. Therefore, within this time, the current can be regarded as 0. Thus, the influence of the delay on the current within this time can be obtained. Therefore, multiply half of the first mean value and the second mean value by the third mean value to obtain the delay weight;

[0142] The acquisition of the preset time is determined according to the average power-on time. The operation of the integrated circuit can be approximately regarded as that every time the preset time elapses, the integrated circuit will be powered off once and then powered on again.

[0143] Refer to Figure 7 As shown, the steps for dividing the circuit formed by the target layout scheme into at least one local circuit include:

[0144] Obtain the line directly between adjacent semiconductor devices in the target layout scheme as the line to be divided;

[0145] During the division, divide according to the midpoint of the line to be divided, and divide the circuit formed by the target layout scheme into at least one local circuit block;

[0146] Cluster adjacent local circuit blocks, where the clustered local circuit blocks satisfy that the semiconductor devices included in the local circuit blocks are of the same type;

[0147] Merge the local circuit blocks clustered into the same type into a local circuit.

[0148] Refer to Figure 8 As shown, obtaining the current burst value caused by semiconductor devices and calculating the burst coefficient of the local circuit includes the following steps:

[0149] Classify the semiconductor devices in the local circuit to obtain at least one series classification. The series classification is composed of semiconductor devices. The semiconductor devices in the same series classification are in a parallel relationship, and different series classifications are in a series relationship;

[0150] Superimpose the current burst values caused by the semiconductor devices in the series classification to obtain the burst classification value;

[0151] Take the maximum value of the burst classification values of the series classification as the burst coefficient of the local circuit.

[0152] According to the properties of series-parallel, respectively take the maximum value of the burst classification values of the series classification as the burst coefficient of the local circuit, and superimpose the current burst values caused by the semiconductor devices in the series classification to obtain the burst classification value.

[0153] Refer to Figure 9 As shown, forming a steady current point distribution setting scheme for the local circuit includes the following steps:

[0154] Based on big data, obtain the upper limit of the sudden change current of the steady current at the steady current point;

[0155] When the burst coefficient does not exceed the upper limit of the sudden change current, obtain a series bus in the local circuit. The series bus connects all the series classifications in the local circuit in series, and take any point on the series bus as the setting position of the steady current point;

[0156] When the burst coefficient is greater than the upper limit of the sudden change current, take the series classification with the burst classification value greater than the upper limit of the sudden change current as the target series classification;

[0157] Set a steady current point parallel line at the lines at both ends of the target series classification. The number of parallel steady current points in the steady current point parallel line is equal to k, where k is the smallest integer not less than e, and e is the deviation value, and e is calculated using the steady current formula;

[0158] Take the midpoint of each parallel line in the steady current point parallel line as the setting position of the steady current point, and take any point on the series bus as the setting position of the steady current point;

[0159] The steady current formula is as follows:

[0160]

[0161] Among them, f is the burst classification value, and g is the upper limit of the mutant current.

[0162] Since the current stabilizer can stabilize the burst current, when the mutant current does not exceed the upper limit of the mutant current, only one current stabilizer is needed. However, for complex integrated circuits, according to different circuit settings, series-parallel classification is required. Thus, the maximum burst current in the series bus is determined. When it does not exceed the upper limit of the mutant current, only one current stabilizer is needed to complete the current stabilization. However, when it exceeds, the target series classification needs to be processed, and only the part of the target series classification that exceeds the upper limit of the mutant current needs to be stabilized. Therefore, the number of current stabilizers set on both sides of the target series classification is k and they are set in parallel. The method of taking k is easy to understand. If the burst classification value is between the upper limit of the mutant current and twice the upper limit of the mutant current, then according to common sense, one current stabilizer needs to be set. And according to the above calculation result, k is also taken as 1 because e is between 0 and 1, and the smallest integer not less than e is 1. Therefore, this is consistent with the actual situation. Similarly, when the burst classification value is other values, the value of k can be obtained by similar discussions as above, and it is easy to verify that it is consistent with the result obtained by the current stabilization formula.

[0163] Supplement the setting position of the current stabilizer into the target layout scheme. The steps for the final layout scheme are as follows:

[0164] Supplement the setting position of the current stabilizer into the position of the local circuit in the target layout scheme.

[0165] Furthermore, this solution also proposes a storage medium, on which a computer-readable program is stored. When the computer-readable program is called, it executes the above-mentioned integrated circuit layout method for power stability control of semiconductor devices.

[0166] It can be understood that the storage medium can be a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape; an optical medium, such as a DVD; or a semiconductor medium, such as a solid-state drive (SSD).

[0167] In summary, the advantages of the present invention are as follows: By establishing a current loss model in an integrated circuit, a current delay model in the integrated circuit, and a current crosstalk model in the integrated circuit, calculating the comprehensive stability coefficient of the preliminary layout scheme, and forming a stable current point distribution setting scheme for the local circuit, it is possible to take into account the attenuation of current with transmission distance in the integrated circuit, the influence of cross-current between adjacent lines, and the influence of current delay in the circuit. According to their different natures, corresponding weights are formed for comprehensive consideration. Thus, the optimal target layout scheme can be selected. At the same time, in order to reduce the influence of sudden current, the position of the stable current point is set in the integrated circuit, and a current stabilizer is arranged at the stable current point to ensure the overall stability of the current in the integrated circuit when sudden current occurs. Thus, it is ensured that all semiconductor devices in the integrated circuit can work with a current as close as possible to the rated current, thereby ensuring the working effect of the integrated circuit.

[0168] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. What is described in the above embodiments and the specification is only the principle of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of protection required by the present invention is defined by the appended claims and their equivalents.

Claims

1. A semiconductor device integrated circuit layout method for power supply stabilization control, characterized in that: include: Obtaining at least one semiconductor device to be integrated, and obtaining a rated current of the semiconductor device; Establish a current loss model in an integrated circuit, establish a current delay model in an integrated circuit, and establish a current crosstalk model in an integrated circuit; forming at least one preliminary layout scheme of a semiconductor device; Based on the established model, calculate the comprehensive stability coefficient of the preliminary layout scheme; Select the preliminary layout plan with the largest comprehensive stability coefficient as the target layout plan; Based on the implemented functions, the circuit formed by the target layout scheme is divided to obtain at least one partial circuit; Based on historical data, the current burst value caused by the semiconductor device is obtained, and the burst coefficient of the local circuit is calculated; A distribution setting scheme of steady current points of a local circuit is formed, and a current stabilizer is set at the steady current point; The setting position of the current stabilizer is added into the target layout plan as the final layout plan.

2. A semiconductor device integrated circuit layout method for power supply stabilization control according to claim 1, characterized in that: The establishment of the current loss model in the integrated circuit comprises the following steps: In an integrated circuit, a distance value range from a semiconductor device to a power source is obtained, and the distance value range is divided into equal intervals to obtain at least one distance point; Under the condition that the distance between the semiconductor device and the power source is equal to the value at the distance point, obtaining a first actual current passing through the semiconductor device; The first actual current of the semiconductor device is divided by the rated current of the semiconductor device to obtain an actual action ratio; 1 minus the actual action ratio to get the loss ratio; The distance points and the loss ratio are paired and fitted to obtain the current loss fitting function, where the distance points are the independent variables and the loss ratio is the dependent variable.

3. A semiconductor device integrated circuit layout method for power supply stabilization control according to claim 2, characterized in that: The establishment of the current delay model in the integrated circuit comprises the following steps: In an integrated circuit, a distance value range from a semiconductor device to a power source is obtained, and the distance value range is divided into equal intervals to obtain at least one distance point; Under the condition that the distance between the semiconductor device and the power source is equal to the value at the distance point, obtain the time interval for the semiconductor device to be triggered after the circuit is closed; The distance points are paired and fitted with the time interval at which the semiconductor device is triggered, thereby obtaining a current delay fitting function, wherein the distance points are independent variables and the time at which the semiconductor device is triggered is a dependent variable.

4. A semiconductor device integrated circuit layout method for power supply stabilization control according to claim 3, characterized in that: The establishment of the current crosstalk model in the integrated circuit comprises the following steps: In an integrated circuit, obtaining an interval value range of adjacent circuits, dividing the interval value range into equal intervals, and obtaining at least one identification point; One of the adjacent circuits is used as a circuit to be tested, and at least one sampling point is selected in the circuit to be tested; Under the condition that the distance between adjacent circuits is equal to the value at the identification point, obtaining a second actual current flowing through the sampling point; Obtain the distance from the sampling point to the power supply as the characteristic distance, substitute the characteristic distance into the current loss fitting function, and obtain the current compensation value; The second actual current at the sampling point is superimposed on the current compensation value to obtain a third actual current; Based on the position of the circuit to be tested in the integrated circuit, the voltage distributed at both ends of the circuit to be tested is determined as the actual voltage, and the resistance of the circuit to be tested is obtained as the actual resistance; The actual voltage is divided by the actual resistance to obtain a fourth actual current; Taking an average value of a fourth actual current of at least one sampling point in the circuit to be tested to obtain an actual average current; The actual average current minus the third actual current is used to obtain the crosstalk current; The value at the identification point is paired with the crosstalk current and fitted to obtain the current crosstalk fitting function, in which the value at the identification point is the independent variable and the crosstalk current is the dependent variable.

5. A semiconductor device integrated circuit layout method for power supply stabilization control according to claim 4, characterized in that: The forming of at least one preliminary layout scheme of the semiconductor device comprises the following steps: At least one series connection frame is provided on a circuit board on which semiconductor devices are integrated, and at least one parallel connection position is provided in the series connection frame, so that the number of all parallel connection positions is consistent with the number of semiconductor devices; The distance between adjacent series frames is equal to the value of one of at least one distance point, and the distance between adjacent parallel positions is equal to the value of one of at least one identification point; The semiconductor devices are mounted at parallel positions, and each positional arrangement relationship of the series frame and the parallel positions forms a preliminary layout scheme.

6. A semiconductor device integrated circuit layout method for power supply stabilization control according to claim 5, characterized in that: The method of calculating the comprehensive stability coefficient of the preliminary layout scheme based on the established model includes the following steps: Based on big data, the total time of the integrated circuit being powered on during normal operation is obtained as the characteristic time, the number of times the integrated circuit is powered on before it is scrapped is obtained as the characteristic number, and the characteristic time is divided by the characteristic number to obtain the preset time; Substitute the value at the distance point into the current loss fitting function and take the average to obtain a first average value, and multiply the first average value by the preset time to obtain a loss weight; Substituting the value at the identification point into the current crosstalk fitting function and taking the average to obtain a second average value, and multiplying the second average value by the preset time to obtain a crosstalk weight; Substitute the value at the distance point into the current delay fitting function and take the average to obtain a third mean, multiply the first mean and half of the second mean by the third mean to obtain a delay weight; obtaining a position of the semiconductor device in the preliminary layout scheme as a preliminary position; Substituting the distance from the preparation position to the power supply into the current loss fitting function to obtain a preparation loss value, taking the average of the preparation loss values ​​corresponding to at least one preparation position to obtain a preparation average loss value; Substituting the distance from the preparation position to the power supply into the current delay fitting function to obtain the preparation delay time, taking the average of the preparation delay time corresponding to at least one preparation position to obtain the pre-average delay time; Obtain a line adjacent to the preparation position as a target line, and obtain a distance between the target line and the line where the preparation position is located as a target distance; Substituting the target distance into the current crosstalk fitting function to obtain a pre-set crosstalk value, taking the average of the pre-set crosstalk values ​​corresponding to at least one pre-set position to obtain a pre-average crosstalk value; Use the circuit synthesis formula to calculate the comprehensive stability coefficient of the preliminary layout solution; The circuit synthesis formula is as follows: Among them, A is the comprehensive stability coefficient, b is the loss weight, c is the crosstalk weight, d is the delay weight, B is the pre-average loss value, C is the pre-average crosstalk value, and D is the pre-average delay time.

7. A semiconductor device integrated circuit layout method for power supply stabilization control according to claim 6, characterized in that: The step of dividing the circuit formed by the target layout scheme to obtain at least one local circuit comprises the following steps: Acquire the circuits directly adjacent to the semiconductor device in the target layout scheme as the circuits to be divided; When dividing, dividing is performed according to the midpoint of the circuit to be divided, and the circuit formed by the target layout scheme is divided into at least one local circuit block; Clustering adjacent local circuit blocks, wherein the clustered local circuit blocks satisfy the requirement that semiconductor devices contained in the local circuit blocks are of the same type; The local circuit blocks that are clustered into the same type are merged into a local circuit.

8. The semiconductor device integrated circuit layout method for power supply stabilization control according to claim 7, characterized in that: The method of obtaining the current burst value caused by the semiconductor device and calculating the burst coefficient of the local circuit comprises the following steps: Classifying semiconductor devices in the local circuit to obtain at least one series classification, wherein the series classification is composed of semiconductor devices, semiconductor devices in the same series classification are in a parallel relationship, and semiconductor devices in different series classifications are in a series relationship; The current burst values ​​caused by the semiconductor devices in the series classification are superimposed to obtain the burst classification value; The maximum value of the burst classification value of the series classification is taken as the burst coefficient of the local circuit.

9. A semiconductor device integrated circuit layout method for power supply stabilization control according to claim 8, characterized in that: The scheme for forming a distribution setting scheme of steady current points of a local circuit comprises the following steps: Based on big data, the upper limit of the sudden change current of the steady current point is obtained; When the burst coefficient does not exceed the upper limit of the sudden change current, a series bus is obtained in the local circuit, and the series bus connects all the series classifications in the local circuit in series, and any point in the series bus is used as the setting position of the steady current point; When the burst coefficient is greater than the upper limit of the mutation current, the series classification whose burst classification value is greater than the upper limit of the mutation current is taken as the target series classification; A steady flow point parallel line is set on the lines at both ends of the target series classification, and the number of parallel steady flow points in the steady flow point parallel line is equal to k, where k is the smallest integer not less than e, and e is the deviation value, which is calculated using the steady flow formula; The midpoint of each parallel line in the steady current point parallel line is used as the setting position of the steady current point, and any point in the series bus is used as the setting position of the steady current point; The steady flow formula is as follows: Where, f is the burst classification value and g is the upper limit of the mutation current.

10. The semiconductor device integrated circuit layout method for power supply stabilization control according to claim 9, characterized in that: The method of adding the setting position of the current stabilizer into the target layout scheme as the final layout scheme includes the following steps: The setting position of the current stabilizer is supplemented into the position of the local circuit in the target layout scheme.

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