Identification method and device for chip autonomous design

Abstract

The invention discloses a chip autonomous design identification method and device, and the method comprises the steps: selecting an identification layer of a chip according to a provided electronic layout, selecting a coordinate origin and a characteristic attribute pattern in the electronic layout corresponding to the identification layer, and recording the relative coordinates of a characteristic point in the characteristic attribute pattern to the coordinate origin; unsealing and removing the layer of the chip, and exposing the identification layer; using a field emission scanning electron microscope to shoot and splice actual images of relative coordinate positions in the identification hierarchy, comparing the actual images with characteristic attribute patterns selected in an electronic layout, and judging whether the actual image of the chip is consistent with the layout or not, so as to identify whether the chip is autonomously designed or not. According to the method, whether the chip is autonomously designed by a provider or not is identified from the physical structure level of the bottom layer of the integrated circuit by acquiring the microstructure of the integrated circuit and comparing the consistency of the design layout, so that the purposes of autonomously designing and tracing the chip are achieved, and the safety and stability of a supply chain of a key chip are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method and device for identifying independently designed chips. Background Art

[0002] The integrated circuit industry chain is long, from semiconductor materials to integrated circuit design, manufacturing, packaging and testing, and terminal applications, involving a large number of participants in different segments. The long supply chain and a large number of product numbers have brought huge challenges to the supply chain management of terminal application manufacturers, an important part of which is the sustainability and autonomous controllability of the chip supply chain.

[0003] The independent research and development evaluation and appraisal of chip design is an important part of supply chain management. The existing evaluation method is mainly document review, supplemented by the comparison of model identification after the chip is unpacked to confirm whether the internal model is consistent with the external model of the package. The advantages of this evaluation method are simplicity, convenience and strong operability, but the disadvantages are also obvious. By comparing the model identification on the package shell and the internal bare chip, it can only be proved that the actual chip and the provided chip are the same model, but it cannot prove that the chip is the core element of the supplier's independent design. The supplier can circumvent this review by purchasing wafers and then packaging and marking them independently. Summary of the invention

[0004] In view of the above problems and technical requirements, the present invention proposes a chip self-designed identification method and device, and the technical solution is as follows:

[0005] In a first aspect, the present invention discloses a method for identifying an autonomously designed chip, the method comprising:

[0006] Select the identification level of the chip to be identified according to the provided electronic layout, and determine the coordinate origin and select the characteristic attribute pattern in the electronic layout corresponding to the identification level;

[0007] Select a feature point in the feature attribute pattern and record the relative coordinates of the feature point position to the coordinate origin;

[0008] Unseal and remove the layers of the identification chip by physical and / or chemical methods to expose the identification layer;

[0009] The actual image of the relative coordinate position in the identification layer is magnified and photographed using a field emission scanning electron microscope, and the photographed images are spliced ​​using EDA software to obtain a regional morphology image with characteristic attributes;

[0010] The regional morphological image with characteristic attributes is compared with the characteristic attribute pattern to determine whether the actual image of the chip is consistent with the layout; if they are consistent, the chip is identified as an independent design; otherwise, the chip is not an independent design.

[0011] A further technical solution is that the identification method further includes:

[0012] Before unsealing, perform an appearance inspection on the chip to be identified to determine that the chip to be identified has not been unsealed.

[0013] A further technical solution is that the unsealing method includes at least one of mechanical unsealing, chemical unsealing, and laser unsealing; the delayer method includes at least one of grinding, reactive ion etching, and wet etching.

[0014] A further technical solution is that the characteristic attribute pattern includes wirings and vias.

[0015] A further technical solution is that the identification level is the metal layer.

[0016] A further technical solution is that the identification level is the polysilicon gate layer.

[0017] A further technical solution is that compare the topographic image of the area with characteristic attributes with the characteristic attribute pattern to determine whether the actual image of the chip is consistent with the layout, including:

[0018] Compare the wiring direction, via position, and via quantity in the topographic image of the area with characteristic attributes and the characteristic attribute pattern. If any one of the wiring direction, via position, and via quantity is inconsistent, it is determined that the actual image of the chip is inconsistent with the layout; otherwise,

[0019] Compare the sizes of the wirings and vias in the topographic image of the area with characteristic attributes and the characteristic attribute pattern. If the size errors of the wirings and vias do not exceed the threshold, it is determined that the actual image of the chip is Figure 1 consistent with the layout; otherwise, it is determined that the actual image of the chip is inconsistent with the layout.

[0020] A further technical solution is that comparing the sizes of the wirings and vias in the topographic image of the area with characteristic attributes and the characteristic attribute pattern includes:

[0021] Compare the wiring widths at multiple corresponding positions in the topographic image of the area with characteristic attributes and the characteristic attribute pattern;

[0022] Compare the via aperture sizes at multiple corresponding positions in the topographic image of the area with characteristic attributes and the characteristic attribute pattern.

[0023] A further technical solution is that before determining whether the actual image of the chip is consistent with the layout, the identification method further includes:

[0024] Take a polysilicon gate layer pattern by a field emission scanning electron microscope and identify the minimum standard unit that composes the gate circuit in the polysilicon gate layer pattern;

[0025] Compare the actual pattern of the minimum standard cell with the provided standard cell library to determine whether the actual process library corresponding to the chip matches the provided process library information. If not, identify that the chip is not independently designed; if it matches, continue to determine whether the actual image of the chip is consistent with the layout.

[0026] In a second aspect, the present invention discloses an identification device for independently designing a chip, including:

[0027] A chip identification layer selection module, configured to select the identification level of the chip to be identified according to the provided electronic layout.

[0028] A characteristic attribute pattern determination module, configured to select the coordinate origin and the characteristic attribute pattern in the electronic layout corresponding to the identification level, and record the relative coordinates of the positions of the characteristic points in the characteristic attribute pattern to the coordinate origin.

[0029] An opening and layer-removing module, configured to open and remove the layer of the chip to be identified by physical and / or chemical methods to expose the identification level.

[0030] An actual pattern photographing module, configured to magnify and photograph the actual image at the relative coordinate position in the identification level by using a field emission scanning electron microscope, and splice the photographed images through EDA software to obtain a regional morphology image with characteristic attributes.

[0031] An independent design identification module, configured to compare the regional morphology image with characteristic attributes with the characteristic attribute pattern to determine whether the actual image of the chip is consistent with the layout; if it is consistent, identify that the chip is independently designed; otherwise, identify that the chip is not independently designed.

[0032] The beneficial technical effects of the present invention are:

[0033] By extracting the physical layer characteristic attributes (DNA) of the chip and comparing them with the design documents, the present invention conducts independent research and development traceability identification of the chip from the underlying physical structure level, solves the forgery problem that may be brought by the existing data review, provides a credible inspection and identification method for equipment manufacturers to select chips, and ensures the security and stability of the supply chain of key chips.

[0034] The present invention conducts independent research and development identification of the chip by extracting the microscopic characteristic morphology of the chip, greatly reducing the time and cost of chip identification. Further, the identification method adopted by the present invention discloses as little chip design information as possible, and is an identification method mainly based on physical examination of the chip and supplemented by data review, effectively protecting the trade secrets of chip design enterprises. Description of the Drawings

[0035] Figure 1 It is a schematic flow chart of a method for identifying the independent design of a chip in an embodiment.

[0036] Figures 2A-2B They are respectively the electronic version diagram of the characteristic attribute pattern of the metal layer of an embodiment and the actual image of the corresponding chip.

[0037] Figures 3A-3B They are respectively the electronic version diagram of the characteristic attribute pattern of the metal layer of a comparative embodiment and the actual image of the corresponding chip.

[0038] Figures 4A-4B They are respectively the electronic version diagram of the characteristic attribute pattern of the polysilicon gate layer of another embodiment and the actual image of the corresponding chip.

[0039] Figure 5 It is the structural block diagram of a chip independent design identification device of an embodiment. Specific embodiments

[0040] The following further describes the specific embodiments of the present invention with reference to the accompanying drawings.

[0041] In one embodiment, as Figure 1 shown, a method for identifying the independent design of a chip is provided. In this embodiment, the method includes the following steps:

[0042] Step 102, select the identification level of the chip to be identified according to the provided electronic version diagram, and determine the coordinate origin and select the characteristic attribute pattern in the electronic version diagram corresponding to the identification level.

[0043] Specifically, the identification level of the chip preferably selects the Poly layer or the metal layer. Among them, the Poly layer refers to the polysilicon layer, which is mainly used to manufacture the gate electrodes in transistors and memory cells, and is therefore also called the polysilicon gate layer. The number of metal layers is usually 1-10 according to chip design and process, including metal layer 1 (M1), metal layer 2 (M2),..., metal layer n (Mn), top metal (TM), etc. The materials of the metal layers usually include aluminum or copper according to the process.

[0044] When selecting the characteristic attribute pattern, it is necessary to avoid: 1) repetitive structure areas that may affect judgment, such as the Memory area; 2) Dummy areas. Dummy refers to a semiconductor element or structure without function, which is usually used to fill the unused areas in the chip to ensure that the structure and performance of other parts can be maintained; these fillers are usually made of the same material as the chip, but they are not used for any circuit or logic function.

[0045] The characteristic attribute pattern selects structures that are easy to identify and different from the surrounding areas. It is preferably to select the positions of wiring and vias, and the wiring and vias can be combined into a characteristic combination, which is more conducive to subsequent consistency comparison.

[0046] The selection of the size of the characteristic attribute pattern is based on the criterion of being able to identify the uniqueness of the pattern. On the premise of meeting the identification requirements, a square area with a side length of 20 microns is preferentially selected as the characteristic attribute pattern.

[0047] The cross marking points are marks used to identify and locate the center position and direction of the chip during the chip manufacturing process, so that the chip can be accurately identified and located in subsequent processes. Usually, there are cross marking points on each layer of the electronic layout, which can be used as the coordinate origin. However, the cross marking points may be scratched off during the wafer dicing process, resulting in incomplete or missing cross marking points in the actual chip. Therefore, in the absence of cross marking points, since the chip is square, the lower left corner position of the layout is preferentially used as the coordinate origin.

[0048] Step 104: Select a characteristic point in the characteristic attribute pattern and record the relative coordinates of the position of the characteristic point to the coordinate origin.

[0049] Specifically, select a characteristic point in the characteristic attribute pattern, determine the relative coordinates of the characteristic point to the coordinate origin, and thus determine the regional position of the characteristic attribute pattern.

[0050] Step 106: Open the package and remove the layers of the chip to be identified by physical and / or chemical methods to expose the identification layer.

[0051] Specifically, the methods of opening the package include at least one of mechanical opening, chemical opening, and laser opening; the methods of removing the layers include at least one of grinding, reactive ion etching, and wet etching.

[0052] Preferably, when the identification layer is determined to be the Poly layer, that is, the polysilicon gate layer, after opening the package, the passivation protection layer on the top of the chip and the multi-layer metal layers in the middle are removed by chemical grinding to expose the image of the bottom Poly layer.

[0053] Step 108: Use a field emission scanning electron microscope to magnify and photograph the actual image at the relative coordinate position in the identification layer, and splice the photographed images through EDA software to obtain a regional morphology image with characteristic attributes.

[0054] Specifically, use a field emission scanning electron microscope (SEM) for photographing and image splicing. Locate the regional position of the actual image corresponding to the characteristic attribute pattern in the chip identification layer according to the relative coordinates in Step 104, perform key magnification and photographing, and splice the photographed SEM images through EDA software to obtain a regional morphology image with characteristic attributes.

[0055] Since the size of a single picture taken by a field emission scanning electron microscope is small, it is usually necessary to continuously take pictures within the area position of the actual image corresponding to the feature attribute pattern, and then splice them through EDA software to form a complete regional morphology image with feature attributes for comparison.

[0056] Step 110: Compare the regional morphology image with the feature attribute pattern to determine whether the actual image of the chip is consistent with the layout; if it is consistent, identify the chip as self-designed; otherwise, identify the chip as not self-designed.

[0057] In one embodiment, the identification method further includes: performing an appearance inspection on the chip before unsealing to determine that the chip has not been unsealed.

[0058] Specifically, the appearance inspection mainly checks the integrity of the markings and the package.

[0059] In one embodiment, as shown in FIGS. 2-4, the top layer passivation protection layer and the top layer metal of the chip are ground by physical and / or chemical methods to expose the metal layer 2 (M2), and the regional morphology image with feature attributes is compared with the feature attribute pattern to determine whether the actual image of the chip is consistent with the layout. Specifically, it includes:

[0060] Step 202: Compare the wiring routes, via positions, and via quantities in the regional morphology image with feature attributes and the feature attribute pattern. If any one of the wiring routes, via positions, and via quantities is inconsistent, it is determined that the actual image of the chip is inconsistent with the layout; otherwise,

[0061] Step 204: Compare the sizes of the wirings and vias in the regional morphology image with feature attributes and the feature attribute pattern. If the size errors of the wirings and vias do not exceed the threshold, it is determined that the actual image of the chip is Figure 1 consistent with the layout; otherwise, it is determined that the actual image of the chip is inconsistent with the layout.

[0062] Specifically, when comparing the actual image of the chip with the layout, in addition to the wiring routes, via positions, and via quantities all needing to be consistent, key dimensions such as via aperture and wiring width also need to be further compared. In this embodiment, the preferred size error threshold is 10%, that is, when the error of the key dimension is within 10% of the corresponding dimension, it is determined that the actual image of the chip is Figure 1 consistent with the layout, and when the error is more than 10% (including 10%) of the corresponding dimension, it is determined that the actual image of the chip is inconsistent with the layout.

[0063] Optionally, in step 204, comparing the sizes of the wirings and vias in the regional morphology image with feature attributes and the feature attribute pattern specifically includes:

[0064] Comparing the wiring widths at multiple corresponding positions in the regional morphology image with feature attributes and the feature attribute pattern;

[0065] The regional morphology image with characteristic attributes is compared with the aperture sizes of the through holes at multiple corresponding positions in the characteristic attribute pattern.

[0066] The judgment of through-hole and wiring size usually requires the judgment results of multiple positions as the final result, and it is judged to be consistent only when multiple positions meet the requirements. The number of multiple positions can be 3, 6, 9 or others, and the specific value can be determined according to the precise requirements. For example, randomly select 9 positions of through-holes to measure the aperture, and randomly select 9 positions of wiring lines to measure the wiring width, and compare them with the layout respectively.

[0067] Figure 2A , 2B The actual image and version of the chip are given. Figure 1 The electronic layout of the characteristic attribute pattern of the metal layer 2 under the same conditions and the corresponding actual image of the chip. It can be seen from the figure that the metal wiring direction and the position and number of through holes in the two are consistent.

[0068] As a comparative example, Figure 3A , 3B The electronic layout of the metal layer characteristic attribute pattern and the corresponding actual chip image are given when the actual chip image is inconsistent with the layout. It can be seen from the figure that the wiring directions of the two are consistent, but the positions and numbers of the through holes are inconsistent.

[0069] In one embodiment, the chip is ground to the polysilicon gate layer by physical and / or chemical methods. That is, when the identification layer is selected as the Poly layer (i.e., the polysilicon gate layer), the identification method may further include:

[0070] 302, determining a standard cell (Standard Cell) used to form a gate circuit according to the polysilicon gate layer.

[0071] Specifically, the polysilicon gate layer pattern is photographed by a field emission scanning electron microscope to identify the minimum standard unit constituting the gate circuit in the polysilicon gate layer pattern.

[0072] 304 , determining whether the standard cell actually corresponding to the chip matches the standard cell information in the provided process library.

[0073] Specifically, the actual pattern of the minimum standard cell is compared with the provided standard cell library to determine whether the process library actually corresponding to the chip matches the provided process library information.

[0074] 306, if they do not match, it is determined that the chip is not independently designed; if they match, it is further determined whether the actual image of the chip is consistent with the layout. The determination steps are the same as those in the previous embodiment and will not be repeated here.

[0075] Figure 4A , 4B gives the electronic layout of the characteristic attribute pattern of the Poly layer in the case where the actual image of the chip is consistent with the layout, and the corresponding actual image of the chip. It can be seen from the figure that the polycrystalline wiring directions and the positions and quantities of the contact vias of the two are consistent. Figure 1 By obtaining the microscopic morphology of the integrated circuit and comparing and analyzing it with the design layout, the present invention identifies whether the chip is independently designed by the provider from the underlying physical structure level of the integrated circuit, ensuring the independent research and development of key chips and the security and stability of the supply chain.

[0076] Based on the same inventive concept, an embodiment of the present invention further provides a chip independent design identification device for implementing the above-mentioned chip independent design identification method. The solution provided by this device for solving problems is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the chip independent design identification device provided below can refer to the limitations on the chip independent design identification method in the above text, and will not be repeated here.

[0077] In one embodiment, as

[0078] shown, a chip independent design identification device is provided, including: Figure 5 A chip identification layer selection module, configured to select the identification level of the chip to be identified according to the provided electronic layout;

[0079] A characteristic attribute pattern determination module, configured to determine the coordinate origin and select the characteristic attribute pattern in the electronic layout corresponding to the identification level, and record the relative coordinates of the characteristic point positions in the characteristic attribute pattern to the coordinate origin;

[0080] An unsealing and layer removing module, configured to unseal and remove the layer of the chip to be identified by physical and / or chemical methods, and expose the identification level;

[0081] An actual pattern photographing module, configured to magnify and photograph the actual image at the relative coordinate position in the identification level by using a field emission scanning electron microscope, and splice the photographed images through EDA software to obtain a regional morphology image with characteristic attributes;

[0082] An independent design identification module, configured to compare the regional morphology image with characteristic attributes with the characteristic attribute pattern to determine whether the actual image of the chip is consistent with the layout; if consistent, identify the chip as independently designed; otherwise, identify the chip as not independently designed.

[0083]

[0084] The above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. A method for identifying independently designed chips, characterized in that: The identification method comprises: Select the identification level of the chip to be identified according to the provided electronic layout, and determine the coordinate origin and select the characteristic attribute pattern in the electronic layout corresponding to the identification level; Select a feature point in the feature attribute pattern, and record the relative coordinates of the feature point position to the coordinate origin; Unsealing and removing the layers of the chip to be identified by physical and / or chemical methods to expose the identification layer; Using a field emission scanning electron microscope to magnify and photograph the actual image of the relative coordinate position in the identification level, and splicing the photographed image through EDA software to obtain a regional morphology image with characteristic attributes; The regional morphological image with characteristic attributes is compared with the characteristic attribute pattern to determine whether the actual image of the chip is consistent with the layout; if they are consistent, the chip is identified as an independent design; otherwise, the chip is identified as not an independent design.

2. The identification method according to claim 1, characterized in that: The identification method further comprises: Before unsealing, the chip to be identified is visually inspected to ensure that the chip to be identified has not been unsealed.

3. The identification method according to claim 1, characterized in that: The unsealing method includes at least one of mechanical unsealing, chemical unsealing and laser unsealing; the de-layering method includes at least one of grinding, reactive ion etching and wet etching.

4. The identification method according to claim 1, characterized in that: The characteristic attribute patterns include wirings and vias.

5. The identification method according to claim 4, characterized in that: The identification layer is a metal layer.

6. The identification method according to claim 4, characterized in that: The identification layer is a polysilicon gate layer.

7. The identification method according to claim 5 or 6, characterized in that: The step of comparing the regional topography image with the characteristic attribute with the characteristic attribute pattern to determine whether the actual image of the chip is consistent with the layout includes: Compare the regional morphology image with the characteristic attribute with the wiring direction, through-hole position and through-hole quantity in the characteristic attribute pattern. If any one of the wiring direction, through-hole position and through-hole quantity is inconsistent, it is determined that the actual image of the chip is inconsistent with the layout; otherwise, The regional morphological image with characteristic attributes is compared with the sizes of wiring and through-holes in the characteristic attribute pattern. If the size errors of the wiring and through-holes do not exceed the threshold, it is judged that the actual image of the chip is consistent with the layout; otherwise, it is judged that the actual image of the chip is inconsistent with the layout.

8. The identification method according to claim 7, characterized in that: The comparing the regional topography image having the characteristic attribute with the sizes of wiring and through-holes in the characteristic attribute pattern includes: Comparing the regional topography image with the characteristic attribute with the wiring widths of a plurality of corresponding positions in the characteristic attribute pattern; The regional morphology image with the characteristic attribute is compared with the aperture sizes of the through holes at a plurality of corresponding positions in the characteristic attribute pattern.

9. The identification method according to claim 6, characterized in that: Before determining whether the actual chip image is consistent with the layout, the identification method further includes: Photographing a polysilicon gate layer pattern by a field emission scanning electron microscope, and identifying a minimum standard unit constituting a gate circuit in the polysilicon gate layer pattern; The actual pattern of the minimum standard unit is compared with the provided standard unit library to determine whether the process library actually corresponding to the chip matches the provided process library information. If not, the chip is identified as not independently designed; if matched, continue to determine whether the actual image of the chip is consistent with the layout.

10. A chip self-designed identification device, characterized in that: include: A chip identification layer selection module is used to select the identification layer of the chip to be identified according to the provided electronic layout; A characteristic attribute pattern determination module is used to determine the coordinate origin and select the characteristic attribute pattern in the electronic layout corresponding to the identification level, and record the relative coordinates of the characteristic point position in the characteristic attribute pattern to the coordinate origin; An unsealing and layer removal module is used to unseal and remove the layers of the chip to be identified by physical and / or chemical methods to expose the identification layer; An actual pattern shooting module is used to magnify and shoot the actual image of the relative coordinate position in the identification level by using a field emission scanning electron microscope, and to splice the shot images by EDA software to obtain a regional morphology image with characteristic attributes; An independently designed identification module is used to compare the regional morphological image with the characteristic attribute with the characteristic attribute pattern to determine whether the actual image of the chip is consistent with the layout; If they are consistent, the chip is identified as an independent design; otherwise, the chip is identified as not an independent design.

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