Layout legalization method for carrying out mixed row height circuit design by adopting legalization framework and bit diagram

Abstract

The invention provides a layout legalization method for carrying out hybrid line height circuit design by adopting a legalization framework and a bit diagram, and relates to the field of hybrid line height circuit design. According to the method, a legalized framework and a data structure of a bit map are adopted, layout legalization construction is conducted on the mixed row height circuit, bit mapping is conducted on the mixed row height circuit, and an algorithm used for searching for the placement position in the mixed row height circuit is compiled so that the circuit with complex constraints can be rapidly legalized. Meanwhile, the method can be improved according to the original algorithm of the hybrid row height circuit. The algorithm module can be compatible with most legalized algorithms, and a basic operation module with extremely high efficiency is provided for the algorithm module to call.

Description

Technical Field

[0001] The present invention provides a layout legalization method for hybrid row height circuit design using a legalization framework and a bitmap, which relates to the field of hybrid row height circuit design. Background Art

[0002] In traditional circuits, for the convenience of design and optimization, standard cells are usually designed to have the same height. However, with the increasing complexity of modern circuit design, in order to better balance power consumption, area, routability, and performance, standard cells begin to have different heights. Previous research work on legalization algorithms for circuits with hybrid cell heights can be divided into two categories. The first type of work only deals with the legalization problem of hybrid cell heights with the basic constraints of the legalization problem, and the main goal is to minimize the cell displacement and wire length as much as possible. The basic constraints mentioned here include cell overlap, power / ground (VDD / VSS) alignment, and site alignment. However, this type of work lacks consideration of the additional constraints brought by advanced technology nodes. The second type of work takes into account some additional constraints, such as minimum injection area (MIA), drain-to-drain docking (DDA), routability problems, and adjacent diffusion effect (NDE). However, neither of these two types of work can comprehensively solve all the constraints. With the increasing complexity of design constraints, it is almost impossible to combine many different design constraints and propose a single legalization algorithm to solve them. Summary of the Invention

[0003] In view of the above problems, the present invention provides a layout legalization method for hybrid row height circuit design using a legalization framework and a bitmap. It can be used to quickly legalize circuits with hybrid height cells. Based on the bitmap, this method can legalize the layout considering dozens of layout constraints and minimize the cell displacement. In addition, an acceleration technique based on interval mapping is proposed in this paper, which can further accelerate the search for legalized positions that do not violate the design rules.

[0004] A layout legalization method for hybrid row height circuit design using a legalization framework and a bitmap, characterized in that in the design of a hybrid row height circuit, a data structure of a bitmap is adopted to construct the layout legalization of the hybrid row height circuit, and standard cells at placeable positions that do not overlap with the already placed standard cells or pre-placed obstacles in the hybrid row height circuit are screened; the steps of the layout legalization method for hybrid row height circuit design using a legalization framework and a bitmap include:

[0005] Step 1: Construct a legalization framework for the mixed row height circuit design, including establishing the constraints for the legalization framework of the mixed row height circuit unit design, completing the standardization of the mixed row height circuit to obtain the standard cells of the mixed row height circuit, and establishing the basic operation modules for the cells of the mixed row height circuit that meet the constraints of the legalization framework and have been completed with standardization;

[0006] Step 2: Use a bitmap to construct a bitmap-based mathematical expression for the layout of the mixed row height circuit;

[0007] Step 3: Write algorithm steps based on the mixed row height circuit after the bitmap processing to find the standard cells at the placeable positions;

[0008] Step 4: After completing Steps 1, 2, and 3, perform a compatibility improvement operation according to the original algorithm used for the mixed row height circuit.

[0009] Furthermore, the construction of the legalization framework for the mixed row height circuit in Step 1 includes the following:

[0010] Step 1.1: Establish the constraints for the legalization framework of the mixed row height circuit design; the constraints for the legalization framework include the following: 1) The cells must not overlap, 2) The cells must be placed within the chip area, 3) The cells must be at the placeable positions on the row, 4) The cells must meet the power / ground alignment constraints, 5) The fence area constraints; 6) The direction constraints, 7) The pin mask alignment constraints.

[0011] Furthermore, the completion of the standardization of the mixed row height circuit in Step 1 to obtain the standard cells of the mixed row height circuit includes the following:

[0012] Step 1.2: Perform mathematical modeling on the mixed row height circuit to obtain the global layout mathematical expression C of the mixed row height circuit with n standard cells as:

[0013] C = {c 1 ,..., c n};

[0014] where c i represents a single standard cell, and each standard cell has two attributes: coordinates and direction. The width, height, initial lower left corner coordinate position, and single-row row height of the standard cell c i are respectively represented as w i , h i , (x i ′, y i ′) and H.

[0015] Furthermore, the construction of the basic operation modules for the cells of the mixed row height circuit that meet the constraints of the legalization framework and have been completed with standardization in Step 1 includes the following:

[0016] Step 1.3: The unit operations for non-standardized mixed line height circuits include unit movement, unit merging, unit separation, and unit deformation; after the standardization of the mixed line height circuit, the basic operation module includes the following:

[0017] Standardized movement of standard cells: which includes the following:

[0018] A1. Move right: Given a coordinate, a maximum displacement, and a standard cell c i , the goal is to place the standard cell at the nearest legal position to the right of the coordinate;

[0019] A2. Move left: Given a coordinate, a maximum displacement, and a standard cell c i , the goal is to place the standard cell at the nearest legal position to the left of the coordinate;

[0020] A3. Move horizontally: Given a coordinate, a maximum displacement, and a standard cell c i , the goal is to place the standard cell at the nearest legal position on the same row as the coordinate;

[0021] A4. Move in all directions: Given a coordinate, a maximum displacement, and a standard cell c i , the goal is to place the standard cell at the nearest legal position to the coordinate;

[0022] Standard cell c i Standardized merging and separation: Create a directed connection for the cells of the mixed line height circuit at two different coordinates;

[0023] Standard cell c i Standardized deformation: includes swapping the coordinates of the cells of two mixed line height circuits, flipping the cells of the mixed line height circuit, and stretching the cells of the mixed line height circuit.

[0024] Furthermore, the mathematical expressions for constructing the layout of the mixed line height circuit in Step 2 include the following:

[0025] Step 2.1: The layout legalization area of the mixed line height circuit under the legalization framework consists of rows, and each row consists of many sites; the layout legalization area is defined as a grid, and all standard cells c i must be located on the grid after the layout is completed;

[0026] Step 2.2: Use a bitmap data structure to represent the two-dimensional grid of the layout legalization area of the mixed line height circuit under the legalization framework; use a bit to represent whether the site is occupied by the standard cell c i , where the unoccupied site is marked as 0, and the occupied site is marked as 1;

[0027] Construct a bitmap with n rows and m columns, where the bitmap is defined as "bitmap" in the mathematical notation of programming. In this bitmap, each cell of the mixed row height circuit is represented by a bit. The mathematical expression of the bitmap "bitmap" of the mixed row height circuit is as follows:

[0028]

[0029] where z represents the total number of cells, and P k represents the set of the four corner coordinates of the cell k , (x ij , y ij ) represents the lower left corner coordinates of the site ij , w ij and h ij represent the width and height of the site ij respectively;

[0030] The mathematical expression of the bitmap "bitmap" of the mixed row height circuit is applicable not only to the mixed row height circuit with single row height but also to the mixed row height circuit with multiple row heights.

[0031] Furthermore, the algorithm of the mixed row height circuit according to the completed bitmap processing in step 3 includes the following:

[0032] Step 3.1.1: Establish a standard cell displacement algorithm; taking the right displacement as an example, define the initial position (x', y'), the standard cell c i , the width w, the maximum displacement d max , the row r j , the x coordinate x of the right boundary of the layout r , the site width w site ;

[0033] Step 3.1.2: To ensure that the standard cell c i does not exceed the chip area, the program expression for defining the maximum displacement d max is:

[0034] d max = min(d max , x r - x' - w);

[0035] Step 3.1.3: Align the standard cell c i with the nearest site (x', y) on the row r j ;

[0036] Step 3.1.4: Traverse the coordinates within x' and x' + d maxThe site between them, when the site does not overlap with the standard cell c i When not overlapping, call the function isPlaceable(c i , x site , y).

[0037] Among them, the isPlaceAble function is an interface provided by the design rule check module. The isPlaceAble function calls the check functions of various design constraints encapsulated in the design rule check module to determine whether the coordinates of the site meet the constraints under the legalization framework. If the constraints under the legalization framework are met, the closest placeable position (x, y) is output.

[0038] Furthermore, the hybrid row height circuit algorithm according to step 3 after bitmap processing includes the following:

[0039] Step 3.2.1: Initialize the function bitOr to convert multiple rows of bitmaps into a single row of bitmaps through bitwise "OR" operation;

[0040] Step 3.2.2: Use n 0 and n 1 to record the number of leading consecutive 0 bits and 1 bits of the bitmap respectively;

[0041] Step 3.2.3: Calculate the number of leading consecutive 1 bits through the function getLeadingOneBitNum and set them all to 0 through the function setLeadingZero;

[0042] Step 3.2.4: After completing step 3.2.3, calculate the number of leading consecutive 0 bits through the getLeadingZeroBitNum function and set them all to 1 through the function setLeadingOne;

[0043] Step 3.2.5: When n 0 - n 1 ≥ w, the loop ends, and the first consecutive 0 bits with a quantity greater than or equal to the width w of the standard cell c i are obtained, that is, the placeable position standard cell where the right side of the multi-row high standard cell c i will not overlap with other cells and obstacles is found.

[0044] Furthermore, the compatibility improvement operation according to the original algorithm adopted by the hybrid row height circuit in step 4 includes the following:

[0045] When the Abacus algorithm is adopted for the mixed row height circuit design, the Abacus algorithm takes the PlaceRow function as the core and realizes the function of this function through the same row movement, right movement and merging operations in the combination operation module.

[0046] When the legalization of the mixed row height circuit design adopts the Tetris algorithm, the Tetris algorithm is realized by calling the four-side movement function of the basic operation module.

[0047] Among them, on the basis of adopting the bitmap for the mixed row height circuit design, a data structure of interval mapping (IntervalMap) is added to speed up the search for placeable position units.

[0048] The present invention has the following advantages:

[0049] 1) It can be used to quickly legalize a circuit with mixed-height cells. This method is based on a bitmap and can legalize the layout considering dozens of layout constraints and minimize cell displacement.

[0050] 2) Greatly reduce the time required to search for placeable positions of cells when considering these design rules. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a flowchart of the algorithm system of the present invention.

[0052] Figure 2 It is a schematic diagram of the legalization framework of the present invention.

[0053] Figure 3 It is an example diagram of representing mixed-height cells with a bitmap according to the present invention.

[0054] Figure 4 It is an example diagram of representing double row height cells with a bitmap according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0055] The technical solution of the present invention will be specifically described below with reference to the drawings.

[0056] As Figure 1 shown, the steps of a layout legalization method for mixed row height circuit design using a legalization framework and a bitmap include:

[0057] Step 1: Construct a legalization framework for the mixed row height circuit design, including establishing the constraint conditions for the legalization framework of the mixed row height circuit unit design, completing the standardization of the mixed row height circuit to obtain the standard cells of the mixed row height circuit, and establishing a basic operation module for the cells of the mixed row height circuit that meets the constraint conditions of the legalization framework and has completed the standardization;

[0058] Step 2: Use a bitmap to construct a bitmap-based mathematical expression for the mixed line height circuit layout;

[0059] Step 3: Write algorithm steps according to the mixed line height circuit after bitmap processing, and find standard cells at available placement positions;

[0060] After completing Steps 1, 2, and 3, perform compatibility improvement operations according to the original algorithm used by the mixed line height circuit, and use acceleration techniques to speed up the search for available placement positions.

[0061] As Figure 2 shown, in the embodiments of the present invention, the top-level module in the legalization framework is the legalization algorithm module. Since the legalization algorithm module has been decoupled from the design rule checking module, this module has strong compatibility, and many classic legalization algorithms can be transplanted into this module, such as Abacus, Tetris, MGL, and MrDP. This module will adjust the legalization order of cells, minimize cell displacement, optimize wire length, and calculate the layout cost of cells based on the legalization algorithm used. When it is necessary to enhance the algorithm or use a better legalization algorithm, this module can be easily modified.

[0062] The decoupling of the design rule checking module of the algorithm module can be achieved through the basic operation module. When designing the legalization algorithm, there is no need to consider how to check the design rules. Only the basic operation module needs to be called to implement various operations on cells, because the basic operation module provided by the present invention will automatically call the design rule checking module to determine whether the current operation violates a certain design rule. If it is found that a design rule violation is triggered, the basic operation module will cancel this operation and continue to search for the next position through the calculation method of the legalization algorithm used.

[0063] In the embodiments of the present invention, the middle-level module of the legalization framework is the basic operation module, which can be called by the top-level legalization algorithm module. Almost all legalization algorithms can be implemented by calling the basic operation module. The basic operations provided by this module will be introduced in detail below:

[0064] a) Movement: The basic operation module includes four operations for moving cells, and their search ranges and directions are different. In order to avoid large displacements of cells during the legalization process, the maximum range for these four movement operations to search for available placement positions can be restricted in actual use. These four movement operations can meet the needs of most algorithms for moving cells. The following introduces these four movement operations:

[0065] a.1) Move right (placeRight): Given a coordinate (x, y), a maximum displacement d max and a standard cell c i, the goal is to place the standard cell c i at the nearest legal position to the right of the coordinate (x, y).

[0066] a.2) Move left (placeLeft): Given a coordinate (x, y), a maximum displacement d max and the standard cell c i , the goal is to place the standard cell c i at the nearest legal position to the left of the coordinate (x, y).

[0067] a.3) Move horizontally in the same row (placeX): Given a coordinate (x, y), a maximum displacement d max and the standard cell c i , the goal is to place the standard cell c i at the nearest legal position on the same row as the coordinate (x, y).

[0068] a.4) Move around (placeAround): Given a coordinate (x, y), a maximum displacement d max and the standard cell c i , the goal is to place the standard cell c i at the nearest legal position to the coordinate (x, y).

[0069] Algorithm 1 shows the implementation details of the move - right algorithm. Line 1 ensures that the cell does not go beyond the chip area, and line 2 ensures that the cell is located at a placeable site on the row. In lines 3 - 9, starting from the starting position of the cell, search to the right to find the nearest placeable position. Line 3 traverses the sites where the coordinate is between x' and x'+d max . When ensuring that placing on these sites will not cause any overlap, in line 4, the function isPlaceable(c i , x site , y) will be called. This is an interface provided by the design rule check module, which can judge whether the position meets all considered design rules and constraints. Once the standard cell c i can be placed at the current position, the move - right algorithm will feedback this position to the top - level legalization algorithm module, and then the top - level module will decide whether to place the cell at this position according to the algorithm used.

[0070]

[0071] The implementation of moving left is similar to moving right, only different in the search direction. Moving horizontally in the same row can be achieved by alternately calling move - right and move - left, and usually the search ranges of move - right and move - left need to be restricted during this process. Moving around can be achieved by calling moving horizontally in the same row.

[0072] The basic operation module will check with the design rule checking module to find out whether the found location violates the considered design rules.

[0073] b) Merging and separating

[0074] Some algorithms, such as Abacus, need to be able to create directed connections for two objects (cells or clusters), and the coordinates of one object will be determined by the coordinates of the other object. Therefore, a merge operation is provided in the basic operation module to implement this function. If, after the merge operation, the design rule checking module determines that an illegal layout has occurred, a separation operation is also provided in the basic operation module for the algorithm module to call to undo this merge.

[0075] c) Flipping, swapping, and stretching

[0076] Since a cell has two attributes, coordinates and direction, some design rule violations can also be resolved by flipping the cell. Therefore, only the movement operation of the cell is not enough. Thus, a flip operation is provided in the basic operation module. In addition, some legalization algorithms will optimize the maximum displacement, wire length, etc. by swapping cells, and some legalization algorithms will handle certain design rule violations by swapping cells. Therefore, the basic operation module provided by the present invention also provides a swap operation. Since some specific design rules, such as the minimum implant area (MIA) constraint, can be satisfied by stretching the cell, the basic operation module provided by the present invention also introduces a stretch operation.

[0077] In an embodiment of the present invention, the underlying module of the legalization framework is the design rule checking module. The basic operation module can access the design rule checking module to find out whether the new location or new direction to be assigned to the cell will violate some design rules that need to be considered. If the design rule checking module determines that the operation of the basic operation module will trigger a design rule violation, then the basic operation module will undo the operation and continue to find the next possible location for the target cell; otherwise, the basic operation module will complete this operation.

[0078] Figure 3 Shows an example of representing a layout layout with a bitmap. Each grid in the figure is a site. The unoccupied site is marked as 0, and the occupied site is marked as 1. The present invention provides that areas such as obstacles and fixed macro cells will be marked as 1 in the preprocessing stage. In the legalization process, when a cell finds a placeable location, that location will be marked as 1.

[0079] Based on the bitmap, the present invention can quickly identify the placeable locations of cells of various different heights that do not overlap with other already placed cells and obstacles. Figure 4Disclosed is a method of applying a bitmap to a double line height cell. Based on the starting position and height of the target cell, the present invention provides that a two-line bitmap can be obtained, and then the two-line bitmap is converted into a single-line bitmap through a bitwise "OR" operation. Assuming that the width of the target cell is 2 sites, then Figure 4 the yellow position in it is the nearest non-overlapping position to the right of the target cell. If the yellow position violates other design rules, then the search will continue to the next non-overlapping position to the right, that is, Figure 4 the green position in it. The processing method for other height cells is similar to that of the double line height cell.

[0080] Algorithm 2 gives a method for quickly implementing the above operations. In line 2, the present invention provides to use the function bitOr to convert a multi-line bitmap into a single-line bitmap through a bitwise "OR" operation. Lines 3-8 will continuously search for consecutive 0 bits with a quantity greater than or equal to the width w of the standard cell c i Similarly, the present invention provides to use n 0 and n 1 to record the number of leading consecutive 0 bits and 1 bits of the bitmap bm respectively. In line 4, the present invention provides to calculate the number of leading consecutive 1 bits through the function getLeadingOneBitNum and set them all to 0 in line 5 through the function setLeadingZero. Then, in line 6, the number of leading consecutive 0 bits is calculated through the getLeadingZeroBitNum function and set them all to 1 in line 7 through the function setLeadingOne. When n 0 - n 1 ≥ w, the loop ends, which means that the first consecutive 0 bits with a quantity greater than or equal to the width w of the cell c i have been found, that is, the nearest position to the right of the multi-line height cell c i that does not overlap with other cells and obstacles. The present invention provides to complete the calculation of the number of leading consecutive 0 bits and 1 bits within O(1) time using built-in functions. Therefore, the present invention provides that Algorithm 2 can be used to quickly find the nearest non-overlapping position to the right of the target cell.

[0081]

[0082] In an embodiment of the present invention, Algorithm 3 details the way of running the classic Abacus algorithm through a framework. The PlaceRow function is the core of the Abacus algorithm, and its function can be realized through the same-row movement (placeX), right movement (placeRight) and merge operations in the combination operation module. In line 17, if the cell c iIt does not overlap with the cluster C on the far right of the current row of the cell. The present invention provides a method to find the nearest legal position in this row using the same-row movement function. In lines 19 - 21, the standard cell c i is merged with the cluster C on the far right of the current row of the standard cell c i and the coordinates of the new cluster are calculated according to the method provided in the Abacus algorithm. If the new coordinates violate the design constraints, the separation operation of the basic operation module is used to undo this merge, and then the rightward movement function is used to continue searching for the next nearest legal position to the right.

[0083]

[0084] In an embodiment of the present invention, when the legalization of the mixed row height circuit design adopts the Tetris algorithm, the Tetris algorithm is implemented by calling the four-sided movement function of the basic operation module.

[0085]

[0086] In an embodiment of the present invention, in order to further accelerate the speed of searching for legal positions without violating the design rules, the present invention provides and designs a data structure called Interval Map. This structure significantly reduces the search space of the mixed row height circuit algorithm, so that the nearest feasible solution can be found faster. In addition, the Interval Map proposed by the present invention pre-consideres the design rules related to continuous intervals, which reduces the number of rules that must be considered during the layout operation.

[0087] The Interval Map is a data structure diagram created based on the rows of the bitmap-based mixed row height circuit. For the areas where standard cells cannot be placed, the intervals corresponding to these areas on the rows of the mixed row height circuit will be removed and excluded in the data structure diagram of the Interval Map.

[0088] With the help of the Interval Map, the present invention provides that the binary search algorithm can be used in the layout stage to obtain the interval corresponding to a specific position. It should be emphasized that not all intervals in the Interval Map represent legal positions, but it can ensure that the positions not within any interval in the interval diagram are invalid. Therefore, the present invention provides that these areas can be skipped and the legal positions can be searched only within the remaining intervals of the interval diagram.

[0089] The present invention has the following advantages:

[0090] 1) An enabling framework that is highly compatible with existing legalization algorithms and extensible is proposed. The present invention provides a complete basic operation module, decoupling the legalization algorithm module and the design rule checking module, such that when considering relatively complex multiple design rules, different legalization algorithms can be more conveniently applied to the framework provided by the present invention.

[0091] 2) At the same time, in order to significantly reduce the search time required to find placeable positions in the basic operation module, the present invention provides an innovative acceleration technique that can greatly reduce the time required to search for placeable positions of search units in the basic operation module. In actual circuit design, the framework provided by the present invention can be used to apply more legalization algorithms to the layout phase. In summary, the compatibility and extensibility of the framework of the present invention make it an efficient solution to various legalization problems in electronic design automation.

[0092] The above are the preferred embodiments of the present invention. All changes made according to the technical solution of the present invention, when the functions and effects produced do not exceed the scope of the technical solution of the present invention, fall within the protection scope of the present invention.

Claims

1. A layout legalization method for mixed row height circuit design using a legalization framework and a bitmap, characterized in that: In the design of mixed row height circuits, the legalization framework and bitmap data structure are used to construct the layout legalization of the mixed row height circuits and bitmap the mixed row height circuits, and an algorithm is written to search for possible placement positions in the mixed row height circuits; The steps of the layout legalization method for mixed row height circuit design using a legalization framework and a bitmap include: Step 1: Construct a legalization framework for hybrid line height circuit design, including establishing constraints for the legalization framework for hybrid line height circuit unit design, completing hybrid line height circuit standardization to obtain standard units for hybrid line height circuits, and establishing basic operation modules for units of hybrid line height circuits that meet the constraints of the legalization framework and complete standardization; Step 2: constructing a bitmapped mathematical expression of the mixed row height circuit layout using the bitmap; Step 3: Find the placement position of the standard cell that can be placed according to the mixed row height circuit writing algorithm steps after the bit mapping process is completed; Step 4: After completing steps 1, 2, and 3, a compatible improvement operation is performed based on the original algorithm used by the mixed row height circuit, and acceleration technology is used to speed up the search for possible placement positions.

2. A layout legalization method for hybrid line height circuit design using a legalization framework and a bitmap according to claim 1, characterized in that: The legal framework for building a hybrid line height circuit in step 1 includes the following: Step 1.1: Establish the constraints of the legalization framework for mixed row height circuit design; the constraints of the legalization framework include the following: 1) cells must not overlap, 2) cells must be placed within the chip area, 3) cells must be located in a placeable position on the row, 4) cells must satisfy power / ground alignment constraints, 5) fence area constraints; 6) direction constraints, 7) pin mask alignment constraints.

3. A layout legalization method for hybrid line height circuit design using a legalization framework and a bitmap according to claim 2, characterized in that: The standard unit of the mixed row height circuit obtained by completing the standardization of the mixed row height circuit in step 1 includes the following contents: Step 1.2: Mathematically model the mixed row height circuit and obtain the global layout mathematical expression C of the mixed row height circuit with n standard cells: C={c1,...,c n }; where c i Represents a single standard unit. Each standard unit has two attributes: coordinates and direction. The standard unit c i The width, height, initial lower left corner coordinate position and single line height are represented as w i 、h i 、(x i ′,y i ') and H.

4. A layout legalization method for hybrid line height circuit design using a legalization framework and a bitmap according to claim 3, characterized in that: The basic operation modules of the unit in step 1 that satisfies the legalization framework constraints and completes the standardized mixed row height circuit include the following: Step 1.3: The unit operations for the non-standardized mixed row height circuit include unit movement, unit merging, unit separation, and unit deformation; after completing the standardization of the mixed row height circuit, the basic operation module includes the following: Standardized movement of standard cells: This includes the following: A1. Move right: Given a coordinate, maximum displacement and standard unit c i ,The goal is to place the standard cell at the nearest legal position to the right of the coordinate; A2. Move left: Given a coordinate, maximum displacement and standard unit c i ,The goal is to place the standard cell at the nearest legal position to the left of the coordinate; A3. Moving in the same direction: Given a coordinate, maximum displacement and standard unit c i ,The goal is to place the standard cell at the nearest legal position on the same row of coordinates; A4. Move around: Given a coordinate, maximum displacement and standard unit c i ,The goal is to place the standard cell at the legal position closest to the coordinate; Standard cell c i Standardized merging and splitting: creating directed connections between cells of mixed row height circuits of two different coordinates; Standard cell c i Standardized deformation: including exchanging the coordinates of the cells of two mixed row height circuits, flipping the cells of the mixed row height circuit, and extending the cells of the mixed row height circuit.

5. A layout legalization method for hybrid line height circuit design using a legalization framework and a bitmap according to claim 4, characterized in that: The mathematical expressions for constructing the mixed row height circuit layout in step 2 include the following: Step 2.1: Layout of mixed row height circuits under the legalization framework The legalization area consists of rows, each row consists of many sites; the layout legalization area is defined as a grid, all standard cells c i All must be on the grid after layout is complete; Step 2.2: Use a bitmap data structure to represent the two-dimensional grid of the layout legalization area of ​​the mixed row height circuit under the legalization framework; use a bit to indicate whether the site site is covered by the standard cell c i Occupancy, where unoccupied sites are marked as 0 and occupied sites are marked as 1; Construct a bitmap with n rows and m columns, where the mathematical symbol of the bitmap in programming is defined as a bitmap, where each unit of the mixed row height circuit is represented by a bit in the bitmap, and the mathematical expression of the bitmap of the mixed row height circuit is as follows: Where z represents the total number of units, P k Represents cell k The set of four corner coordinates, (x ij ,y ij ) indicates site ij The lower left corner coordinate, w ij and h ij Respectively represent the site site ij The width and height of Among them, the mathematical expression of the bitmap of the mixed row height circuit is not only applicable to the mixed row height circuit of single row height, but also to the mixed row height circuit of multiple row height.

6. A layout legalization method for hybrid line height circuit design using a legalization framework and a bitmap according to claim 5, characterized in that: In step 3, the mixed row height circuit algorithm after bit mapping processing includes the following contents: Step 3.1.1: Establish the standard unit displacement algorithm; define the initial position (x', y'), standard unit c i , width w, maximum displacement d max 、Line j , the x-coordinate of the right edge of the bitmap r 、Site width w site ; Step 3.1.2: To ensure the standard unit c i Without exceeding the chip area, define the maximum displacement d max The program expression is: dmax=min(dmax,xr-x'-w); Step 3.1.3: Set the standard cell c i With line r j Align the nearest site (x',y) on the Step 3.1.4: Traverse the coordinates between x' and x'+d max The site between the site, when the site and the standard unit c i When there is no overlap, call the function isPlaceable(c i ,x site ,y), Among them, the isPlaceAble function is an interface provided by the design rule checking module. The isPlaceAble function calls the various design constraint checking functions encapsulated in the design rule checking module to determine whether the coordinates of the site site meet the constraints under the legalization framework. If the constraints under the legalization framework are met, the nearest placeable position (x, y) is output.

7. A layout legalization method for hybrid line height circuit design using a legalization framework and a bitmap according to claim 6, characterized in that: The algorithm for legalizing the mixed row height circuit after bit mapping in step 3 includes the following contents: Step 3.2.1: Initialize the function bitOr to convert the multi-line bitmap into a single-line bitmap through bitwise OR operation; Step 3.2.2: Use n0 and n1 to record the number of leading consecutive 0 bits and 1 bits of the bitmap respectively; Step 3.2.3: Calculate the number of leading consecutive 1 bits through the function getLeadingOneBitNum and set them all to 0 through the function setLeadingZero; Step 3.2.4: After completing step 3.2.3, calculate the number of leading consecutive 0 bits through the getLeadingZeroBitNum function, and set them all to 1 through the setLeadingOne function; Step 3.2.5: When n0-n1≥w, the loop ends and the first number is greater than or equal to the standard unit c. i Consecutive 0 bits of width w result in multiple row height standard cells c i The right side will not be the same as other standard units c i Possible placement locations that overlap obstacles.

8. A layout legalization method for hybrid line height circuit design using a legalization framework and a bitmap according to claim 7, characterized in that: The compatible improvement operation in step 4 according to the original algorithm adopted by the mixed row height circuit includes the following contents: When the Abacus algorithm is used for the legalization of mixed row height circuit design, the Abacus algorithm realizes its own function through the operations of row shift, right shift and merge in the basic operation module.

9. A layout legalization method for hybrid line height circuit design using a legalization framework and a bitmap according to claim 7, characterized in that: The compatible improvement operation in step 4 according to the original algorithm adopted by the mixed row height circuit includes the following contents: When the Tetris algorithm is used for the legalization of the mixed row height circuit design, the Tetris algorithm realizes its own function by calling the four-way movement function of the basic operation module.

10. The layout legalization method for hybrid line height circuit design using a legalization framework and a bitmap according to claim 1, characterized in that: The technical method for accelerating the search for standard cells that can be placed in step 4 also includes: adding a data structure for interval mapping.

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