Universal double-end current output memristor simulator

Abstract

The invention provides a universal double-end current output memristor simulator. The universal double-end current output memristor simulator comprises a double-end current output module, an operation module and an integration module. Through feedback control of the operation module, double-end current output is achieved in cooperation with the double-end current output module, and accurate operation of internal variables of the memristor is achieved in cooperation with the integration module. The designed double-end memristor simulator is compact in structure and rich in function, has the advantages of being high in universality and wide in application range, and can be widely applied to the fields of nonlinear systems, neural network calculation, encryption communication and the like.

Description

Technical Field

[0001] The present invention relates to the technical fields of electronic circuits and non-linear systems, and particularly to a general dual-terminal current-output memristor emulator. Background Art

[0002] As a non-linear electronic device with memory characteristics, the memristor emulator has shown great application potential in the fields of non-volatile storage, neural network computing, chaotic systems, etc. since its proposal. However, limited by the current manufacturing process, the commercial application of actual memristor emulators still faces many challenges. Therefore, in the prior art, a design scheme of an equivalent memristor emulator is widely adopted, that is, the current-voltage characteristics of the memristor emulator are realized through an analog circuit. In recent years, with the rapid development of applications such as chaotic signal generation, encrypted communication, and neural network computing, higher requirements have been put forward for the functionality and integration of equivalent memristor emulators. However, the existing equivalent memristor emulator technology still has many limitations, which are specifically manifested as follows:

[0003] Single function and limited application: Patent CN115499116B (A method for realizing a simple memristor hyperchaotic circuit with a large-scale parameter range) adopts a discretized single-chip microcomputer implementation method. Although it can generate chaotic signals with a large-scale parameter range, its digital circuit-based design cannot fully utilize the analog characteristics of the memristor emulator, and the circuit is complex, making it difficult to meet the requirements of efficient and compact applications.

[0004] Limitations of single-terminal memristors: The power supply part in CN113445076B (A method for reducing metal dendrites in manganese electrodeposition) uses a single-terminal equivalent memristor chaotic oscillator. In this design, one end of the memristor emulator is connected to the high input impedance terminal of AD633, and it is assumed that the current at this port is zero during the calculation. Therefore, it is not a true dual-terminal memristor emulator. This design limits the bidirectional current control ability of the memristor emulator and makes it difficult to perform complex non-linear operations.

[0005] Complex structure and cost issues of dual-terminal memristors: Although patent CN119358572A (A switchable floating-ground memristor emulator based on bidirectional symmetry characteristics) realizes the dual-terminal equivalent memristor function, there is a problem in its design that the pins of AD844 are left floating, resulting in low utilization rate. In addition, this design requires multiple commercial multipliers AD633, which not only increases the circuit complexity but also significantly increases the cost, making it difficult to meet the requirements of large-scale integration and low-cost applications. Summary of the Invention

[0006] Object of the Invention: Aiming at the deficiencies of the prior art, the present invention provides a general dual-terminal current-output memristor emulator to solve the problems of the existing equivalent memristor emulator technology in terms of complex structure, single function, low integration, and high cost.

[0007] The general dual - terminal current - output memristor emulator includes a dual - terminal current - output module, an operation module, and an integration module; The operation module contains two four - quadrant multipliers (444FQ) based on the 444 circuit; The integration module is used for memristor internal variable control; The four - quadrant multiplier (444FQ) based on the 444 circuit includes four improved TGA - SN modules (SNx), a 444 - circuit core (444Core), and a gate circuit.

[0008] The dual - terminal current - output module includes a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , an eighth resistor R 8 , a ninth resistor R 9 , a tenth resistor R 10 , an eleventh resistor R 11 , a twelfth resistor R 12 , a thirteenth resistor R 13 , a fourteenth resistor R 14 , a fifteenth resistor R 15 , a sixteenth resistor R 16 , a seventeenth resistor R 17 , a first operational amplifier U 1 , a second operational amplifier U 2 , a third operational amplifier U 3 , a fourth operational amplifier U 4 , a fifth operational amplifier U 5 , a sixth operational amplifier U 6 , a seventh operational amplifier U 7 , an eighth operational amplifier U 8 .

[0009] One end of the first resistor R 1 is the equivalent output port VM+ of the general dual - terminal current - output memristor emulator, and the other end is connected to the output terminal VR 3 of the third operational amplifier U 1 ; Both ends of the second resistor R 2 are respectively connected to the output terminal V+ of the first operational amplifier U 1 and the inverting input terminal of the second operational amplifier U 2 ; Both ends of the third resistor R 3 are respectively connected to the output terminal of the second operational amplifier U 2The output terminal -V+ and the second operational amplifier U 2 are connected to the inverting input terminal; The fourth resistor R 4 has its two ends respectively connected to the output terminal VI of the thirteenth element U of the operation module including two four-quadrant multipliers (444FQ) based on the 444 circuit and the inverting input terminal of the third operational amplifier U 13 ; 3 The fifth resistor R has its two ends respectively connected to the output terminal -V+ of the second operational amplifier U and the inverting input terminal of the third operational amplifier U 5 ; 2 The sixth resistor R 3 has its two ends respectively connected to the output terminal VR of the third operational amplifier U and the inverting input terminal of the third operational amplifier U ; 6 The seventh resistor R 3 has one end as the equivalent output port VM- of the general dual-terminal current output memristor emulator, and the other end is connected to the output terminal VR of the operational amplifier U 1 ; 3 The eighth resistor R has its two ends respectively connected to the output terminal V- of the fourth operational amplifier U and the inverting input terminal of the fifth operational amplifier U 7 ; 6 The ninth resistor R 2 has its two ends respectively connected to the output terminal -V- of the fifth operational amplifier U and the inverting input terminal of the fifth operational amplifier U ; 8 The tenth resistor R 4 has its two ends respectively connected to the output terminal -VI of the seventh operational amplifier U and the inverting input terminal of the sixth operational amplifier U 5 ; The eleventh resistor R 9 has its two ends respectively connected to the output terminal -V- of the fifth operational amplifier U and the inverting input terminal of the sixth operational amplifier U 5 ; 5 The twelfth resistor R has its two ends respectively connected to the output terminal VR of the sixth operational amplifier U and the inverting input terminal of the sixth operational amplifier U 10 ; 7 The thirteenth resistor R 6 has its two ends respectively connected to the output terminal -VI of the seventh operational amplifier U and the inverting input terminal of the sixth operational amplifier U ; 11 The fourteenth resistor R 5 has its two ends respectively connected to the output terminal -V- of the fifth operational amplifier U and the inverting input terminal of the sixth operational amplifier U 6 ; The fifteenth resistor R 12 has its two ends respectively connected to the output terminal VR of the sixth operational amplifier U and the inverting input terminal of the sixth operational amplifier U 6 ; 2 The sixteenth resistor R 6 has its two ends respectively connected to the output terminal VR of the sixth operational amplifier U and the inverting input terminal of the sixth operational amplifier U ; 13 has its two ends respectively connected to the thirteenth element U of the operation module including two four-quadrant multipliers (444FQ) based on the 444 circuit13 The output terminal VI and the seventh operational amplifier U 7 are connected to the inverting input terminal; The fourteenth resistor R 14 is respectively connected to the output terminal -VI of the seventh operational amplifier U 7 and the inverting input terminal of the seventh operational amplifier U 7 are connected; The fifteenth resistor R 15 is respectively connected to the output terminal -V+ of the second operational amplifier U 2 and the inverting input terminal of the eighth operational amplifier U 8 are connected; The sixteenth resistor R 16 is respectively connected to the output terminal V- of the fourth operational amplifier U 4 and the inverting input terminal of the eighth operational amplifier U 8 are connected; The seventeenth resistor R 17 is respectively connected to the output terminal VM of the eighth operational amplifier U 8 and the inverting input terminal of the eighth operational amplifier U 8 are connected; The output terminal of the first operational amplifier U 1 is connected to the inverting input terminal; The output terminal of the fourth operational amplifier U 4 is connected to the inverting input terminal; The operational amplifier U 2 , U 3 , U 5 , U 6 , U 7 , U 8 The non-inverting input terminals are grounded.

[0010] The operation module includes the eighteenth resistor R 18 , the nineteenth resistor R 19 , the ninth operational amplifier U 9 , the twelfth component U 12 , the thirteenth component U 13 , where the twelfth component U 12 , the thirteenth component U 13 is a four-quadrant multiplier (444FQ) based on a 444 circuit.

[0011] The eighteenth resistor R 18 is respectively connected to the output terminal VM of the eighth operational amplifier U 8 in the differential current output module and the inverting input terminal of the ninth operational amplifier U 9 are connected; The nineteenth resistor R 19 is respectively connected to the output terminal of the ninth operational amplifier U 9 and the ninth operational amplifier U9 is connected to the inverting input terminal; The twelfth element U 12 has its input terminal X connected to the output terminal VM of the eighth operational amplifier U 8 in the dual - ended current output module, its input terminal Y is connected to the output terminal z of the tenth operational amplifier U 10 in the integration module for memristor internal variable control, and its input terminal Z is connected to the output terminal 9 ; The thirteenth element U 13 has its input terminal X connected to the output terminal VM of the eighth operational amplifier U 8 in the dual - ended current output module, its input terminal Y is supplied with a +1V voltage by an independent power supply, and its input terminal Z is connected to the cathode of the first diode D 1 in the integration module for memristor internal variable control; The non - inverting input terminal of the operational amplifier U 9 is grounded.

[0012] The integration module includes the twentieth resistor R 20 , the twenty - first resistor R 21 , the twenty - second resistor R 22 , the twenty - third resistor R 23 , the first capacitor C 1 , the first diode D 1 , the tenth operational amplifier U 10 , the eleventh operational amplifier U 11 .

[0013] The two ends of the twentieth resistor R 20 are respectively connected to the output terminal of the twelfth element U 12 in the operation module including two four - quadrant multipliers (444FQ) based on the 444 circuit and the inverting input terminal of the tenth operational amplifier U 10 ; The two ends of the twenty - first resistor R 21 are respectively connected to the output terminal z of the tenth operational amplifier U 10 and the inverting input terminal of the tenth operational amplifier U 10 ; The two ends of the twenty - second resistor R 22 are respectively connected to the output terminal z of the tenth operational amplifier U 10 and the inverting input terminal of the eleventh operational amplifier U 11 ; The two ends of the twenty - third resistor R 23 are respectively connected to the cathode of the first diode D 1 and the inverting input terminal of the eleventh operational amplifier U 11 ; The two ends of the first capacitor C 1 are respectively connected to the tenth operational amplifier U10 The output terminal z is connected to the inverting input terminal of the tenth operational amplifier U 10 ; The anode of the first diode D 1 is connected to the output terminal of the eleventh operational amplifier U 11 , and the cathode is connected to the input terminal Z of the thirteenth component U of the operational module including two four-quadrant multipliers (444FQ) based on the 444 circuit 13 ; The non-inverting input terminals of the operational amplifiers U 10 , U 11 are grounded

[0014] The general dual-terminal current output memristor emulator is a combination of two single-terminal floating ground memristor emulators

[0015] When constructing the general dual-terminal current output memristor emulator with an equivalent circuit, the following formula is obtained (1), where V represents the voltage across the memristor emulator, I represents the current flowing through the memristor emulator, VM+ and VM- represent the voltage values of both ends of the memristor emulator with respect to ground, VR 1 and VR 2 represent the voltage values of the outputs of two controlled voltage sources with respect to ground, and R 1 and R 7 represent the resistance values

[0016] By transforming formula (1), the relationship between calculating VR 1 and VR 2 and the voltage values VM+ and VM- of both ends of the memristor emulator with respect to ground and the current memductance W of the memristor emulator is obtained (2), where W (S, V) represents the memductance function of the memristor emulator, and S is the state variable

[0017] The present invention has the following beneficial effects: Compact structure: By adopting a four-quadrant multiplier based on a 444 circuit module, the high integration of its three input ports and the interior avoids the use of multiple discrete components in traditional designs, significantly reducing the circuit complexity and power consumption

[0018] Rich functions: Through the collaborative design of the dual-terminal equivalent memristor structure and the four-quadrant multiplier, complex non-linear operations and bidirectional current control are realized, providing an efficient solution for applications such as non-linear systems and neural network calculations

[0019] Low cost: By optimizing the circuit design and improving the component utilization rate, the use of high-cost commercial multipliers in traditional designs is avoided, significantly reducing the manufacturing cost

[0020] The present invention designs a general dual - terminal current - output memristor emulator, which solves the deficiencies of existing equivalent memristor emulator technologies in terms of structure, function, and cost, and provides an efficient, compact, and low - cost solution for fields such as non - linear systems, neural network computing, and encrypted communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is the internal structure diagram of a general dual - terminal current - output memristor emulator provided by an embodiment of the present invention.

[0022] Figure 2 It is the four - quadrant multiplier (444FQ) based on the 444 circuit and its package schematic diagram.

[0023] Figure 3 It is the improved TGA - SN (SNx) and its package schematic diagram.

[0024] Figure 4 It is the frequency response schematic diagram of a general dual - terminal current - output memristor emulator provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0025] The following further detailed description of the present invention will be made in conjunction with the accompanying drawings and specific embodiments, and the above - mentioned and / or other advantages of the present invention will become clearer.

[0026] As Figure 1 shown, an embodiment of the present invention provides a general dual - terminal current - output memristor emulator, which includes a dual - terminal current - output module, an operation module, and an integration module; The operation module includes two four - quadrant multipliers (444FQ) based on the 444 circuit; The integration module is used for controlling the internal variables of the memristor; The four - quadrant multiplier (444FQ) based on the 444 circuit includes four improved TGA - SN modules (SNx), a 444 - circuit core (444Core), and a gate circuit.

[0027] As Figure 1 shown, the dual - terminal current - output module includes a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , an eighth resistor R 8 , a ninth resistor R 9 , a tenth resistor R 10 , an eleventh resistor R11 , the twelfth resistor R 12 , the thirteenth resistor R 13 , the fourteenth resistor R 14 , the fifteenth resistor R 15 , the sixteenth resistor R 16 , the seventeenth resistor R 17 , the first operational amplifier U 1 , the second operational amplifier U 2 , the third operational amplifier U 3 , the fourth operational amplifier U 4 , the fifth operational amplifier U 5 , the sixth operational amplifier U 6 , the seventh operational amplifier U 7 , the eighth operational amplifier U 8 ; One end of the first resistor R 1 is the equivalent output port VM+ of the general dual-terminal current output memristor emulator, and the other end is connected to the output terminal VR 3 of the third operational amplifier U 1 ; both ends of the second resistor R 2 are respectively connected to the output terminal V+ of the first operational amplifier U 1 and the inverting input terminal of the second operational amplifier U 2 ; both ends of the third resistor R 3 are respectively connected to the output terminal -V+ of the second operational amplifier U 2 and the inverting input terminal of the second operational amplifier U 2 ; both ends of the fourth resistor R 4 are respectively connected to the output terminal VI of the thirteenth component U 13 of the operation module including two four-quadrant multipliers (444FQ) based on the 444 circuit and the inverting input terminal of the third operational amplifier U 3 ; both ends of the fifth resistor R 5 are respectively connected to the output terminal -V+ of the second operational amplifier U 2 and the inverting input terminal of the third operational amplifier U 3 ; both ends of the sixth resistor R 6 are respectively connected to the output terminal VR 3 of the third operational amplifier U 1 and the inverting input terminal of the third operational amplifier U 3 ; one end of the seventh resistor R 7 is the equivalent output port VM- of the general dual-terminal current output memristor emulator, and the other end is connected to the output terminal VR 6 of the operational amplifier U 2 ; both ends of the eighth resistor R 8 are respectively connected to the output terminal V- of the fourth operational amplifier U 4 and the inverting input terminal of the fifth operational amplifier U 5 ; both ends of the ninth resistor R 9 are respectively connected to the fifth operational amplifier U5 The output terminal -V- and the fifth operational amplifier U 5 are connected to the inverting input terminal of; the tenth resistor R 10 The two ends of which are respectively connected to the seventh operational amplifier U 7 The output terminal -VI of and the sixth operational amplifier U 6 are connected to the inverting input terminal of; the eleventh resistor R 11 The two ends of which are respectively connected to the fifth operational amplifier U 5 The output terminal -V- of and the sixth operational amplifier U 6 are connected to the inverting input terminal of; the twelfth resistor R 12 The two ends of which are respectively connected to the sixth operational amplifier U 6 The output terminal VR of 2 and the sixth operational amplifier U 6 are connected to the inverting input terminal of; the thirteenth resistor R 13 The two ends of which are respectively connected to the thirteenth element U of the operational module including two four - quadrant multipliers (444FQ) based on the 444 circuit 13 The output terminal VI of and the seventh operational amplifier U 7 are connected to the inverting input terminal of; the fourteenth resistor R 14 The two ends of which are respectively connected to the seventh operational amplifier U 7 The output terminal -VI of and the seventh operational amplifier U 7 are connected to the inverting input terminal of; the fifteenth resistor R 15 The two ends of which are respectively connected to the second operational amplifier U 2 The output terminal -V+ of and the eighth operational amplifier U 8 are connected to the inverting input terminal of; the sixteenth resistor R 16 The two ends of which are respectively connected to the fourth operational amplifier U 4 The output terminal V- of and the eighth operational amplifier U 8 are connected to the inverting input terminal of; the seventeenth resistor R 17 The two ends of which are respectively connected to the eighth operational amplifier U 8 The output terminal VM of and the eighth operational amplifier U 8 are connected to the inverting input terminal of; the first operational amplifier U 1 The output terminal of is connected to the inverting input terminal; the output terminal of the fourth operational amplifier U 4 is connected to the inverting input terminal; the operational amplifier U 2 , U 3 , U 5 , U 6 , U 7 , U 8 The non - inverting input terminal of is grounded.

[0028] As Figure 1 shown, the operational module includes the eighteenth resistor R 18 , the nineteenth resistor R 19 , the ninth operational amplifier U 9 , the twelfth element U 12 , the thirteenth element U13 , where the twelfth component U 12 and the thirteenth component U 13 is a four-quadrant multiplier (444FQ) based on the 444 circuit; The eighteenth resistor R 18 is respectively connected at both ends to the output terminal VM of the eighth operational amplifier U 8 of the differential current output module and the inverting input terminal of the ninth operational amplifier U 9 ; The nineteenth resistor R 19 is respectively connected at both ends to the output terminal of the ninth operational amplifier U 9 and the inverting input terminal of the ninth operational amplifier U 9 ; The input terminal X of the twelfth component U 12 is connected to the output terminal VM of the eighth operational amplifier U 8 of the differential current output module, the input terminal Y is connected to the output terminal z of the tenth operational amplifier U 10 of the integration module for memristor internal variable control, and the input terminal Z is connected to the output terminal of the ninth operational amplifier U 9 ; The input terminal X of the thirteenth component U 13 is connected to the output terminal VM of the eighth operational amplifier U 8 of the differential current output module, the input terminal Y is provided with a +1V voltage by an independent power supply, and the input terminal Z is connected to the cathode of the first diode D 1 of the integration module for memristor internal variable control; The non-inverting input terminal of the operational amplifier U 9 is grounded.

[0029] As Figure 1 shown, the integration module includes the twentieth resistor R 20 , the twenty-first resistor R 21 , the twenty-second resistor R 22 , the twenty-third resistor R 23 , the first capacitor C 1 , the first diode D 1 , the tenth operational amplifier U 10 , the eleventh operational amplifier U 11 ; The twentieth resistor R 20 is respectively connected at both ends to the output terminal of the twelfth component U 12 of the operational module including two four-quadrant multipliers (444FQ) based on the 444 circuit and the inverting input terminal of the tenth operational amplifier U 10 ; The twenty-first resistor R 21 is respectively connected at both ends to the output terminal z of the tenth operational amplifier U 10 and the inverting input terminal of the tenth operational amplifier U 10 ; The twenty-second resistor R 22 is respectively connected at both ends to the output terminal z of the tenth operational amplifier U 10 and the eleventh operational amplifier U11 is connected to the inverting input terminal; the twenty-third resistor R 23 has its two ends respectively connected to the cathode of the first diode D 1 and the inverting input terminal of the eleventh operational amplifier U 11 ; the first capacitor C 1 has its two ends respectively connected to the output terminal z of the tenth operational amplifier U 10 and the inverting input terminal of the tenth operational amplifier U 10 ; the anode of the first diode D 1 is connected to the output terminal of the eleventh operational amplifier U 11 , and the cathode is connected to the input terminal Z of the thirteenth component U of the operational module including two four-quadrant multipliers (444FQ) based on the 444 circuit 13 ; the non-inverting input terminals of the operational amplifiers U 10 , U 11 are grounded.

[0030] As Figure 2 shown Figure 1 the four-quadrant multiplier based on the 444 circuit in 24 includes the twenty-fourth resistor R 25 , the twenty-fifth resistor R 26 , the twenty-sixth resistor R 27 , the twenty-seventh resistor R 28 , the twenty-eighth resistor R 29 , the twenty-ninth resistor R 30 , the thirtieth resistor R 31 , the thirty-first resistor R 32 , the thirty-second resistor R 33 , the thirty-third resistor R 34 , the thirty-fourth resistor R 35 , the thirty-fifth resistor R 36 , the thirty-sixth resistor R 37 , the fourteenth component U 14 , the fifteenth component U 15 , the sixteenth component U 16 , the seventeenth component U 17 , the eighteenth component U 18 , the nineteenth operational amplifier U 19 , the twentieth operational amplifier U 20 , the twenty-first operational amplifier U 21 , the twenty-second NOT gate U 22 , the twenty-third NOT gate U 23 , the twenty-fourth NOT gate U 24 , the twenty-fifth XOR gate U 25 , the twenty-sixth XOR gate U 26 , the twenty-seventh operational amplifier U 27 , where the fourteenth component U 14, the fifteenth component U 15 , the sixteenth component U 16 , the eighteenth component U 18 is an improved TGA-SN module (SNx), the seventeenth component is the 444 circuit core; the twenty-fourth resistor R 24 is respectively connected at both ends to the negative power supply VEE for supplying power to the analog circuit and the inverting input terminal of the nineteenth operational amplifier U 19 ; the twenty-fifth resistor R 25 is respectively connected at both ends to the output terminal O 14 of the fourteenth component U 2 (A) and the inverting input terminal of the nineteenth operational amplifier U 19 ; the twenty-sixth resistor R 26 is respectively connected at both ends to the output terminal of the nineteenth operational amplifier U 19 and the inverting input terminal of the nineteenth operational amplifier U 19 ; the twenty-seventh resistor R 27 is respectively connected at both ends to the output terminal of the nineteenth operational amplifier U 19 and the input terminal of the twenty-second NOT gate U 22 ; the twenty-eighth resistor R 28 is respectively connected at both ends to the negative power supply VEE for supplying power to the analog circuit and the inverting input terminal of the twentieth operational amplifier U 20 ; the twenty-ninth resistor R 29 is respectively connected at both ends to the output terminal O 15 of the fifteenth component U 2 (B) and the inverting input terminal of the twentieth operational amplifier U 20 ; the thirtieth resistor R 30 is respectively connected at both ends to the output terminal of the twentieth operational amplifier U 20 and the inverting input terminal of the twentieth operational amplifier U 20 ; the thirty-first resistor R 31 is respectively connected at both ends to the output terminal of the twentieth operational amplifier U 20 and the input terminal of the twenty-third NOT gate U 23 ; the thirty-second resistor R 32 is respectively connected at both ends to the negative power supply VEE for supplying power to the analog circuit and the inverting input terminal of the twenty-first operational amplifier U 21 ; the thirty-third resistor R 33 is respectively connected at both ends to the output terminal O 16 of the sixteenth component U 2 (C) and the inverting input terminal of the twenty-first operational amplifier U 21 ; the thirty-fourth resistor R 34 is respectively connected at both ends to the output terminal of the sixth operational amplifier U 6 and the inverting input terminal of the twenty-first operational amplifier U 21 ; the thirty-fifth resistor R 35 is respectively connected at both ends to the twenty-first operational amplifier U21 's output terminal is connected to the input terminal of the twenty-fourth NOT gate U 24 ; The thirty-sixth resistor R 36 is connected at both ends to the power supply VCC that powers the digital gate circuit and the input terminal Y of the eighteenth component U 18 ; The thirty-seventh resistor R 37 is connected at both ends to the input terminal Y of the eighteenth component U 18 and the ground; The twenty-second NOT gate U 22 , the twenty-third NOT gate U 23 's outputs are respectively connected to the two input terminals of the twenty-five XOR gate U 25 ; The twenty-fifth XOR gate U 25 and the twenty-fourth NOT gate U 24 's outputs are respectively connected to the two input terminals of the twenty-sixth XOR gate U 26 ; The output terminal of the twenty-sixth XOR gate U 26 is connected to the non-inverting input terminal of the twenty-seventh operational amplifier U 27 ; The inverting input terminal and the output terminal of the twenty-seventh operational amplifier U 27 are connected and connected to the input terminal Z of the eighteenth component U 18 ; The input terminals X and Y of the fourteenth component U 14 are connected as the equivalent input terminal X of the four-quadrant multiplier based on the 444 circuit; The input terminal Z of the fourteenth component U 14 is grounded, and the output terminal O 1 is connected to the input terminal X of the seventeenth component U 17 ; The input terminals X and Y of the fifteenth component U 15 are connected as the equivalent input terminal Y of the four-quadrant multiplier based on the 444 circuit; The input terminal Z of the fifteenth component U 15 is grounded, and the output terminal O 1 is connected to the input terminal Y of the seventeenth component U 17 ; The input terminals X and Y of the sixteenth component U 16 are connected as the equivalent input terminal Z of the four-quadrant multiplier based on the 444 circuit; The input terminal Z of the sixteenth component U 16 is grounded, and the output terminal O 1 is connected to the input terminal Z of the seventeenth component U 17 ; The output terminal O 17 of the seventeenth component U 1 is connected to the input terminal W, and the output terminal O 2 is connected to the input terminal X of the eighteenth component U 18 ; The output terminal O 18 of the eighteenth component U 1 serves as the equivalent output terminal O of the four-quadrant multiplier based on the 444 circuit; The output terminal O 2 is left floating and not connected; Operational amplifier U 19 , U20 , the non-inverting input terminal of U 21 is grounded.

[0031] As Figure 3 shown, Figure 2 the improved TGA-SN module (SNx) in 38 includes the thirty-eighth resistor R 39 , the thirty-ninth resistor R 40 , the fortieth resistor R 41 , the forty-first resistor R 42 , the forty-second resistor R 1 , the first transistor Q 28 , the twenty-eighth operational amplifier U 29 , the twenty-ninth operational amplifier U 2 ; the second diode D 38 The two ends of the thirty-eighth resistor R 28 are respectively connected to the output terminal of the twenty-eighth operational amplifier U 1 and the base of the first transistor Q 39 ; one end of the thirty-ninth resistor R 29 is the equivalent input port X of the improved TGA-SN module, and the other end is connected to the inverting input terminal of the twenty-ninth operational amplifier U 40 ; the two ends of the fortieth resistor R 29 are respectively connected to the output terminal of the twenty-ninth operational amplifier U 29 and the inverting input terminal of the twenty-ninth operational amplifier U 41 ; one end of the forty-first resistor R 29 is the equivalent input port X of the improved TGA-SN module, and the other end is connected to the non-inverting input terminal of the twenty-ninth operational amplifier U 42 ; one end of the forty-second resistor R 1 is the equivalent output port O 29 of the improved TGA-SN module, and the other end is connected to the output terminal of the twenty-ninth operational amplifier U 1 ; the collector of the first transistor Q 29 is connected to the non-inverting input terminal of the twenty-ninth operational amplifier U 28 , the emitter is grounded; the inverting input terminal of the twenty-eighth operational amplifier U 2 is the equivalent input port Y of the improved TGA-SN module, the non-inverting input terminal is the equivalent input port Z of the improved TGA-SN module, and the output terminal is the equivalent output port O

[0032] As Figure 4As shown in the figure (the input voltage is a sinusoidal signal with a peak-to-peak value of 10V. The horizontal axis represents the voltage difference between the two ends of the memristor emulator; the vertical axis represents the current flowing through the memristor emulator), when the input voltage is a sinusoidal signal with a peak-to-peak value of 10V, the universal two-terminal current output memristor emulator of the present invention exhibits a good hysteresis loop, which can intuitively understand the memristor characteristics of the circuit. Figure 1 The internal structure can clarify its dual-terminal current output capability. Therefore, the universal dual-terminal current output memristor simulator of the present invention can be directly connected to the circuit like a resistor, without single-end grounding, thus expanding the application range of the memristor.

[0033] Common single-ended memristor emulators usually adopt a structure with one end grounded and the other end output. Its equivalent model can be simplified to a combination of a resistor and a controlled voltage source. Specifically, the output current of the single-ended memristor emulator is controlled by a single-ended external voltage value, and the output of the controlled voltage source is dynamically adjusted through internal state variables, thereby realizing the memory effect and nonlinear characteristics of the memristor emulator. Although this design is simple and easy to implement, it is difficult to meet the needs of complex circuit design due to its limitations of unidirectional current control.

[0034] The equivalent model of the two-terminal memristor emulator can be seen as a combination of two single-terminal memristor emulators, but additional circuit elements are needed to support bidirectional current control and calculation of internal state variables. Its core is two controlled voltage sources, two resistors and an internal state variable calculation module.

[0035] like Figure 1 As shown in the figure, the two ends of the memristor simulator are represented by VM+ and VM-, and VR 1 and VR 2 Represents the voltage value of the output of the two controlled voltage sources to ground. By controlling the output of the controlled voltage source, the resistor R 1 and R 7 An equivalent current is generated on the

[0036] For the charge-controlled (flow-controlled) memristor emulator, the generalized expression is: (1), Here V represents the voltage across the memristor, I represents the current flowing inside the memristor, S represents the internal variable of the memristor, and M(S,I) is a function that represents the change law of the resistance value of the memristor with the state variable S and the current I. This function describes the impedance characteristics of the memristor. Specifically, M represents the resistance of the memristor, and its change reflects the historical behavior of the memristor, which is the accumulation effect of the current. It is the derivative of the state variable S with respect to time, indicating the rate of change of the internal state of the memristor emulator, and g is a function that describes the dynamic changes of the internal state variable.

[0037] As Figure 1 shown, when constructed with an equivalent circuit, from the consistency and directionality of the current, there is: (2), In Figure 1 , VM+, VM-, VR 1 , VR 2 represent circuit ports, and here represent the voltage values of the corresponding ports. Specifically, here VM+ and VM- represent the voltages of both ends of the memristor emulator with respect to ground, and VR 1 and VR 2 represent the voltages of the outputs of two controlled voltage sources with respect to ground. In Figure 1 , R 1 , R 7 represent circuit element resistors, and here represent the specific resistance values of the corresponding resistors.

[0038] Therefore: (3), By transforming Equation (2), the relationships between the voltages of the outputs of the two controlled voltage sources VR 1 and VR 2 with respect to ground, the voltages VM+ and VM- at both ends of the memristor emulator, and the current resistance M of the memristor emulator are calculated.

[0039] Obviously is a repeated term and can be implemented using a four-quadrant multiplier based on 444.

[0040] Similarly, for a magnetically controlled (voltage-controlled) memristor emulator, its general expression is: (4), where h is a function describing the dynamic change of the internal state variable. W(S, I) is a function representing the variation law of the resistance value of the memristor emulator with the state variable S and the current I. This function describes the impedance characteristics of the memristor emulator. Specifically, W represents the conductance of the memristor emulator, and its change reflects the historical behavior of the memristor emulator, which is the accumulation effect of magnetic flux here.

[0041] As Figure 1 shown, when constructed with an equivalent circuit, from the consistency and directionality of the current, there is: (5), In Figure 1 , VM+, VM-, VR 1 , VR 2 represent circuit ports, and here represent the voltage values of the corresponding ports. Specifically, here VM+ and VM- represent the voltages of both ends of the memristor emulator with respect to ground, and VR 1and VR 2 Represents the voltage value of the output of the two controlled voltage sources to ground. Figure 1 In, R 1 , R 7 Represents the resistance of a circuit component, and here it represents the specific resistance value of the corresponding resistor.

[0042] so: (6), By transforming equation (5), VR 1 and VR 2 The relationship between the voltage values ​​of the outputs of the two controlled voltage sources to ground, the voltages VM+ and VM- at both ends of the memristor emulator, and the current memristor W of the memristor emulator.

[0043] Apparently is a repeating term and can be implemented using a 444-based four-quadrant multiplier (444FQ).

[0044] like Figure 1 As shown, op amp U 1 , U 2 , U 3 , U 4 , U 5 , U 6 , U 7 Completed the controlled voltage source VR 1 and VR 2 Calculation, op amp U 8 Converts the double-ended voltage into a single-ended voltage for use by other modules. Component U 13 The four-quadrant multiplier based on 444 realizes the operation of repeated items in the derivation process. For the charge-controlled (current-controlled) memristor emulator, the input terminal X of the four-quadrant multiplier based on 444 is connected to VM + −VM - , the input terminal Y is connected to the memristor function M(S,I), and the input terminal Z is connected to the unit voltage 1V; for the magnetically controlled (voltage-controlled) memristor emulator, the input terminal X of the four-quadrant multiplier based on 444 is connected to VM+−VM- (the + in VM+ is not an operator, but part of the name), the input terminal Y is connected to the memristor function W(S,I), and the input terminal Z is connected to the unit voltage 1V.

[0045] The operation of the memristor function M (S, I) or memristor function W (S, V) of the memristor simulator can be freely designed. Here, the following specific two-terminal memristor simulator is established: (7), This model describes a two-terminal memristor emulator, where the current is related to the voltage through the memristor function W(S,V)=10|S|, which is determined by the absolute value of the state variable S. The state variable S is updated over time according to the change rules of the voltage V and S itself, reflecting the memory effect of the memristor emulator. The behavior of the system is manifested as a nonlinear coupling between current, voltage and state.

[0046] like Figure 1 As shown, component U 12 The four-quadrant multiplier based on 444 realizes the multiplication and division operations in the internal variable derivative of the memristor simulator. 10 The integral operation of the internal variables of the memristor simulator is realized, and the operational amplifier U 11 The calculation of memristor function of memristor simulator is realized.

[0047] The present invention provides a universal two-terminal current output memristor emulator. There are many methods and ways to implement the technical solution. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention. All components not specified in this embodiment can be implemented by existing technologies.

Claims

1. A universal two-terminal current output memristor emulator, characterized in that: It includes a two-terminal current output module, an operation module and an integration module; The operation module includes two four-quadrant multipliers based on 444 circuits; The integration module is used for controlling the internal variables of the memristor; The four-quadrant multiplier based on the 444 circuit includes four improved TGA-SN modules, a 444 circuit core and gate circuits.

2. A universal two-terminal current output memristor emulator according to claim 1, characterized in that: The two-terminal current output module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R 10 11th resistor R 11 , the twelfth resistor R 12 、Thirteenth resistor R 13 , the fourteenth resistor R 14 , the fifteenth resistor R 15 16th resistor R 16 17th resistor R 17 , first op amp U1, second op amp U2, third op amp U3, fourth op amp U4, fifth op amp U5, sixth op amp U6, seventh op amp U7, eighth op amp U8.

3. A universal two-terminal current output memristor emulator according to claim 2, characterized in that: One end of the first resistor R1 is an equivalent output port VM+ of a universal two-terminal current output memristor simulator, and the other end is connected to an output terminal VR1 of the third operational amplifier U3; The two ends of the second resistor R2 are respectively connected to the output terminal V+ of the first operational amplifier U1 and the inverting input terminal of the second operational amplifier U2; The two ends of the third resistor R3 are respectively connected to the output terminal -V+ of the second operational amplifier U2 and the inverting input terminal of the second operational amplifier U2; The two ends of the fourth resistor R4 are respectively connected to the thirteenth element U of the operation module including two four-quadrant multipliers based on the 444 circuit. 13 The output terminal VI is connected to the inverting input terminal of the third operational amplifier U3; The two ends of the fifth resistor R5 are respectively connected to the output terminal -V+ of the second operational amplifier U2 and the inverting input terminal of the third operational amplifier U3; The two ends of the sixth resistor R6 are respectively connected to the output terminal VR1 of the third operational amplifier U3 and the inverting input terminal of the third operational amplifier U3; One end of the seventh resistor R7 is the equivalent output port VM- of the universal two-terminal current output memristor simulator, and the other end is connected to the output terminal VR2 of the operational amplifier U6; The two ends of the eighth resistor R8 are respectively connected to the output terminal V- of the fourth operational amplifier U4 and the inverting input terminal of the fifth operational amplifier U5; The two ends of the ninth resistor R9 are respectively connected to the output terminal -V- of the fifth operational amplifier U5 and the inverting input terminal of the fifth operational amplifier U5; The tenth resistor R 10 The two ends are respectively connected to the output terminal -VI of the seventh operational amplifier U7 and the inverting input terminal of the sixth operational amplifier U6; The eleventh resistor R 11 The two ends are respectively connected to the output terminal -V- of the fifth operational amplifier U5 and the inverting input terminal of the sixth operational amplifier U6; The twelfth resistor R 12 The two ends are respectively connected to the output terminal VR2 of the sixth operational amplifier U6 and the inverting input terminal of the sixth operational amplifier U6; The thirteenth resistor R 13 The two ends are connected to the thirteenth element U of the operation module including two four-quadrant multipliers based on the 444 circuit. 13 The output terminal VI is connected to the inverting input terminal of the seventh operational amplifier U7; The fourteenth resistor R 14 The two ends are respectively connected to the output terminal -VI of the seventh operational amplifier U7 and the inverting input terminal of the seventh operational amplifier U7; The fifteenth resistor R 15 The two ends are respectively connected to the output terminal -V+ of the second operational amplifier U2 and the inverting input terminal of the eighth operational amplifier U8; The sixteenth resistor R 16 The two ends are respectively connected to the output terminal V- of the fourth operational amplifier U4 and the inverting input terminal of the eighth operational amplifier U8; The seventeenth resistor R 17 The two ends are respectively connected to the output terminal VM of the eighth operational amplifier U8 and the inverting input terminal of the eighth operational amplifier U8; The output terminal of the first operational amplifier U1 is connected to the reverse input terminal; The output terminal of the fourth operational amplifier U4 is connected to the reverse input terminal; The non-inverting input terminals of op amps U2, U3, U5, U6, U7, and U8 are grounded.

4. A universal two-terminal current output memristor emulator according to claim 3, characterized in that: The operation module includes an eighteenth resistor R 18 , 19th resistor R 19 , the ninth operational amplifier U9, the twelfth component U 12 、Thirteenth Component U 13 , where the twelfth element U 12 、Thirteenth Component U 13 It is a four-quadrant multiplier based on the 444 circuit.

5. A universal two-terminal current output memristor emulator according to claim 4, characterized in that: The eighteenth resistor R 18 The two ends are respectively connected to the output terminal VM of the eighth operational amplifier U8 of the double-terminal current output module and the inverting input terminal of the ninth operational amplifier U9; The nineteenth resistor R 19 The two ends are respectively connected to the output end of the ninth operational amplifier U9 and the inverting input end of the ninth operational amplifier U9; The twelfth element U 12 The input terminal X is connected to the output terminal VM of the eighth operational amplifier U8 of the two-terminal current output module, and the input terminal Y is connected to the tenth operational amplifier U8 of the integral module for controlling the internal variable of the memristor. 10 The output terminal z is connected to the output terminal of the ninth operational amplifier U9; the input terminal Z is connected to the output terminal of the ninth operational amplifier U9; The thirteenth element U 13 The input terminal X is connected to the output terminal VM of the eighth operational amplifier U8 of the two-terminal current output module, the input terminal Y is provided with a +1V voltage by an independent power supply, and the input terminal Z is connected to the cathode of the first diode D1 of the integration module for controlling the internal variable of the memristor; The non-inverting input terminal of the operational amplifier U9 is grounded.

6. A universal two-terminal current output memristor emulator according to claim 5, characterized in that: The integration module includes a 20th resistor R 20 、The twenty-first resistor R 21 、22nd resistor R 22 、23rd resistor R 23 , the first capacitor C1, the first diode D1, the tenth operational amplifier U 10 、11th op amp U 11 .

7. A universal two-terminal current output memristor emulator according to claim 6, characterized in that: The 20th resistor R 20 The two ends are connected to the twelfth element U of the operation module including two four-quadrant multipliers based on the 444 circuit. 12 The output terminal and the tenth operational amplifier U 10 is connected to the inverting input terminal of; The twenty-first resistor R 21 The two ends are connected to the tenth operational amplifier U 10 The output terminal z and the tenth operational amplifier U 10 is connected to the inverting input terminal of; The twenty-second resistor R 22 The two ends are connected to the tenth operational amplifier U 10 The output terminal z and the eleventh operational amplifier U 11 is connected to the inverting input terminal of; The twenty-third resistor R 23 The two ends are connected to the cathode of the first diode D1 and the eleventh operational amplifier U 11 is connected to the inverting input terminal of; The two ends of the first capacitor C1 are respectively connected to the tenth operational amplifier U 10 The output terminal z and the tenth operational amplifier U 10 is connected to the inverting input terminal of; The anode of the first diode D1 is connected to the eleventh operational amplifier U 11 The output end of the circuit is connected to the cathode of the circuit and the thirteenth element U of the operation module including two four-quadrant multipliers based on the 444 circuit. 13 The input terminal Z is connected; Op amp U 10 , U 11 The non-inverting input terminal is grounded.

8. A universal two-terminal current output memristor emulator according to claim 7, characterized in that: The universal two-terminal current output memristor emulator is a combination of two single-terminal floating memristor emulators.

9. A universal two-terminal current output memristor emulator according to claim 8, characterized in that: When the universal two-terminal current output memristor simulator is constructed using an equivalent circuit, the following formula is obtained: （1）， Among them, V represents the voltage across the memristor emulator, I represents the current flowing inside the memristor emulator, VM+ and VM- represent the voltage values ​​of the two ends of the memristor emulator to ground, VR1 and VR2 represent the voltage values ​​of the outputs of the two controlled voltage sources to ground, and R1 and R7 represent the resistance values ​​of the resistors.

10. The universal two-terminal current output memristor emulator according to claim 9, characterized in that: By transforming formula (1), we can obtain the relationship between VR1 and VR2 and the ground voltages VM+ and VM- at both ends of the memristor emulator and the current memristor of the memristor emulator: （2）， Where W (S, V) represents the memristor function of the memristor simulator, and S is the state variable.

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