Inference calculation circuit system suitable for Mama block

Abstract

The invention belongs to the related technical field of circuit design, and discloses a reasoning calculation circuit system suitable for Mama block, which is characterized in that an input F generates F1 through a normalization circuit, F1 is projected through a memristor array to generate F2 and F3, F2 is activated to generate F4, F3 is subjected to convolution through the memristor array and then is activated to generate Xt, F1 is projected through the memristor array to generate S, and F3 is subjected to convolution through the memristor array and then is activated to generate Xt; after the S passes through the memristor array, e index operation is carried out to generate an M * N-dimensional matrix A; the Xt is projected through a memristor array to generate B and C; performing element multiplication on Xt through a memristor array to generate D; in the N * M-dimensional hidden state calculation circuit array, the hidden state calculation circuit in the nth row and the mth column obtains Xtm, Am, n, Bn and Sm to carry out hidden state calculation to obtain Htn, m, and a multiplication and addition circuit carries out multiplication and addition operation on Ht, B, C and D to obtain Yt; f4 and Yt pass through a multiplication circuit and then are projected through a memristor array to obtain F5, and F5 and F are superposed through a summing circuit to obtain output. Reasoning calculation is achieved through the circuit, operation time can be shortened, and power consumption is saved.

Description

Technical Field

[0001] The present invention belongs to the technical field related to circuit design, and more specifically, relates to an inference calculation circuit system applicable to Mamba block. Background Art

[0002] The Mamba model is a new type of linear time series model that combines the advantages of CNN and transformer. It can capture global information while maintaining linear complexity. And through a parameterized selection mechanism, the Mamba model can selectively choose or ignore specific data according to the characteristics of the input data. Therefore, it does not require a huge parameter storage matrix. When dealing with many problems, its performance is often better than that of the transformer model, making it the preferred choice for the new generation of large language model architectures.

[0003] The basis of the Mamba model is the Mamba block. A large Mamba model consists of many Mamba blocks. The core of the Mamba Block lies in its Selective State Spaces. After performing linear projection and convolution operations, relevant information in long sequences is efficiently captured through the selective state space, with linear time complexity. This enables it to perform well when dealing with very long sequences. And because it relaxes the strict state transitions of traditional state space models, it is more adaptable and flexible.

[0004] Due to the complex control and data movement of the Mamba block and the complex calculation process of the internal selection space state of the Mamba block, there has been no circuit implementation. Currently, model inference calculations are all performed through GPUs. However, when using GPUs for inference, problems such as the separation of memory and computing under the von Neumann architecture are often faced, and the transfer of data from storage to the computing unit often consumes a large amount of time and power.

[0005] Therefore, there is a need to design a circuit system for Mamba block inference calculation to reduce the operation time and save power. Summary of the Invention

[0006] Aiming at the above defects or improvement requirements of the prior art, the present invention provides an inference calculation circuit system applicable to Mamba block, aiming to implement the inference calculation of Mamba block through circuits, reduce the operation time, and save power.

[0007] To achieve the above object, the present invention provides an inference calculation circuit system applicable to Mamba block, which includes; The first circuit structure includes a normalization circuit, a first to a second memristor array, and an activation circuit. The K-dimensional input vector F is normalized by the normalization circuit to generate a vector F1. The vector F1 is projected twice by the first memristor array to generate an M-dimensional vector F2 and an M-dimensional vector F3. The vector F2 is activated by the activation circuit to generate an M-dimensional vector F4. The vector F3 is convolved by the second memristor array and then activated by the activation circuit to generate an M-dimensional vector Xt, where t is the time index. The second circuit structure includes a third to a sixth memristor array. The vector F1 is projected by the third memristor array to generate an M-dimensional vector S. The vector S is element-wise multiplied with each column of the M * N-dimensional fifth memristor array to generate an M * N-dimensional matrix, and the e-exponential calculation circuit performs e-exponential operations on the elements of the matrix to generate an M * N-dimensional matrix A. The vector Xt is projected twice by the fourth memristor array to generate an N-dimensional vector B and an N-dimensional vector C. The vector Xt is element-wise multiplied by the sixth memristor array to generate an M-dimensional vector D. The selective state space calculation circuit structure includes an N * M-dimensional hidden state calculation circuit array and M multiply-accumulate circuits. The hidden state calculation circuit in the nth row and mth column obtains the mth element Xt of the vector Xt m and the element A in the mth row and nth column of the matrix A m,n and the nth element B of the vector B n and the mth element S of the vector S m to perform hidden state calculation and obtain the state element Ht in the nth row and mth column. n,m The state elements obtained by the hidden state calculation circuit array form an N * M-dimensional state matrix Ht. The M columns in the matrix Ht are respectively input into M multiply-accumulate circuits to perform multiply-accumulate operations with the vector C and the vector D to obtain an M-dimensional vector Yt. The result fusion circuit structure includes a multiplication circuit, a seventh memristor array, and a summation circuit. The vector F4 and the vector Yt are element-wise multiplied by the multiplication circuit and then projected by the seventh memristor array to obtain a K-dimensional vector F5. The vector F5 and the vector F are superimposed by the summation circuit to obtain a K-dimensional output vector.

[0008] Optionally, each hidden state calculation circuit includes switches S1~S2, capacitors C1~C2, operational amplifiers U1~U4, a first-branch multiplier, a second-branch multiplier, and multiple resistors. In the hidden state calculation circuit in the nth row and mth column: The non-inverting input terminal of the operational amplifier U1 is grounded through the capacitor C1 and connected to the output terminal of the operational amplifier U4 through the switch S1, and the inverting input terminal is connected to its output terminal. The first-branch multiplier respectively obtains the element A m,nPerform a multiplication operation on the output result of operational amplifier U1, and connect the multiplication result to the inverting input terminal of operational amplifier U2 through a resistor; The second-branch multiplier separately obtains elements S m , element Xt m , element B n to perform a multiplication operation, and connect the multiplication result to the inverting input terminal of operational amplifier U2 through a resistor; The non-inverting input terminal of operational amplifier U2 is grounded, the inverting input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the inverting input terminal of operational amplifier U3 through a resistor; The non-inverting input terminal of operational amplifier U3 is grounded, the inverting input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the non-inverting input terminal of operational amplifier U4 through switch S2; The non-inverting input terminal of operational amplifier U4 is grounded through capacitor C2, the inverting input terminal is connected to its output terminal, and its output terminal outputs the state element Ht n,m ; Among them, switch S1 is controlled by clock signal CL 0 , and switch S2 is controlled by clock signal CL 1 . In the first transfer cycle, switch S2 is turned on and switch S1 is turned off. The hidden state calculation circuit completes the state calculation at the current moment, and operational amplifier U4 outputs the state element. In subsequent transfer cycles, the states of switch S1 and switch S2 are opposite. In the early stage of the transfer cycle, switch S1 is turned on and switch S2 is turned off, so that the state element H(t - 1) n,m output by U4 at the previous moment (t - 1) is stored in capacitor C1, then switch S1 is turned off and switch S2 is turned on, so that the hidden state calculation circuit completes the state calculation at the current moment t, and operational amplifier U4 outputs the state element Ht n,m .

[0009] Optionally, the second-branch multiplier includes multiplier G2 and multiplier G3. Multiplier G2 obtains elements S m and element Xt m to perform a multiplication operation. Multiplier G3 obtains element B n and the multiplication result of multiplier G2 and performs a multiplication operation to output the multiplication result of the second-branch multiplier.

[0010] Optionally, the K-dimensional input vector F is normalized by the normalization circuit to generate vector F1, where vector F is composed of K voltage signals V I1 ~ V IK ; The normalization circuit is a root-mean-square normalization circuit. The root-mean-square normalization circuit includes a root-mean-square circuit and K normalization branches. The K normalization branches perform normalization processing in one-to-one correspondence with the K voltage signals, and each normalization branch includes an operational amplifier, a multiplier, and a resistor; In the k-th normalization branch: The inverting input terminal of operational amplifier U7 obtains the voltage signal V through a resistor Ik , its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U8 through a resistor; Multiplier G4 respectively obtains the output result V of the RMS circuit RMS and the output result of operational amplifier U7 and performs a multiplication operation, and the multiplication result is connected to the inverting input terminal of operational amplifier U7 through a resistor; The inverting input terminal of operational amplifier U8 is connected to its output terminal through a resistor, and its non-inverting input terminal is grounded; Multiplier G4 respectively obtains the voltage parameter g i and the output result of operational amplifier U8 and performs a multiplication operation, and outputs the normalized result V of the voltage signal V Ik , where g Ok is the trained parameter. i

[0011] Optionally, the RMS circuit includes K receiving branches, multiplier G6, operational amplifier U5 and operational amplifier U6, where The K receiving branches respectively receive K voltage signals V I1 ~V IK , and in each receiving branch, the received voltage signal is squared by a multiplier and then connected to the inverting input terminal of operational amplifier U5 through a resistor; The non-inverting input terminal of operational amplifier U5 is grounded, its inverting input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the inverting input terminal of operational amplifier U6 through a resistor; The non-inverting input terminal of operational amplifier U6 is grounded, and the signal at the output terminal is squared by multiplier G6 and then connected to the inverting input terminal of operational amplifier U6 through a resistor, and the output terminal of operational amplifier U6 outputs the output result V of the RMS circuit RMS .

[0012] Optionally, the e exponential calculation circuit includes operational amplifiers U9~U11, multiplier G7 and resistors; Multiplier G7 accesses the external voltage signal V to be calculated for the e exponential j and performs a square operation and then is grounded through two resistors; The inverting input terminal of operational amplifier U9 is connected to three branches. The first branch accesses the voltage signal V through a resistor j , the second branch is connected to the other end of the grounding resistor through a resistor, the third branch is connected to the output terminal of operational amplifier U9 through a resistor, the non-inverting input terminal of operational amplifier U9 is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U10 through a resistor; The inverting input terminal of operational amplifier U10 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U11 through a resistor; The inverting input terminal of operational amplifier U11 is connected to an external 1V voltage source through a resistor and connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U12 through a resistor; The inverting input terminal of operational amplifier U12 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the result V of performing an exponential calculation on the voltage signal V j for the exponential calculation of V ej .

[0013] Optionally, the activation circuit is a Silu activation circuit, and the Silu activation circuit includes an exponential calculation circuit, operational amplifiers U13 to U16, multipliers G8 to G9, and resistors; among them, The exponential calculation circuit is used to obtain the voltage V to be activated i and after performing an exponential calculation, it is connected to the inverting input terminal of operational amplifier U13 through a resistor; The inverting input terminal of operational amplifier U13 is connected to an external 1V voltage source through a resistor and connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U14 through a resistor; The inverting input terminal of operational amplifier U14 is connected to its output terminal through a resistor, and its non-inverting input terminal is grounded; Multiplier G8 respectively obtains the voltage V i and the output result of the exponential calculation circuit and performs a multiplication operation and then is connected to the inverting input terminal of operational amplifier U15 through a resistor; Multiplier G9 respectively obtains the output result of operational amplifier U14 and the output result of operational amplifier U15 and performs a multiplication operation and then is connected to the inverting input terminal of U15 through a resistor; The non-inverting input terminal of operational amplifier U15 is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U16 through a resistor; The inverting input terminal of operational amplifier U16 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the activation result V of voltage V i as V o .

[0014] Optionally, the m-th multiply-accumulate circuit is used to obtain the m-th column in matrix Ht, vector C, and the m-th element D in vector D m and perform calculations; each multiply-accumulate circuit includes N multiplication branches, operational amplifiers U17 to U20, and resistors; In the m-th multiply-accumulate circuit: The n-th multiplication branch obtains the element Ht in matrix Ht n,mand the m-th element C in vector C m After performing a multiplication operation, it is connected to the inverting input terminal of operational amplifier U17 through a resistor; The inverting input terminal of operational amplifier U17 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U18 through a resistor; The inverting input terminal of operational amplifier U18 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U19 through a resistor; The inverting input terminal of operational amplifier U19 accesses the element D in vector D through a resistor m and is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U20 through a resistor; The inverting input terminal of operational amplifier U20 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the m-th element Yt in vector Yt m .

[0015] Optionally, the summing circuit is used to superimpose the elements at the same positions in vector F5 and vector F; The summing circuit includes operational amplifiers U21 to U22 and resistors, where: The inverting input terminal of operational amplifier U21 accesses the voltage signal V of one of the elements in vector F5 through a resistor F5 and accesses the voltage signal V of the element at the corresponding position in vector F through a resistor F and is also connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U22 through a resistor; The inverting input terminal of operational amplifier U22 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the superimposed result.

[0016] Optionally, the memristor array is a 1T1M memristor array.

[0017] Generally speaking, compared with the prior art through the above technical solutions conceived by the present invention, the present invention mainly has the following beneficial effects.

[0018] 1. The inference calculation circuit system proposed by the present invention uses a memristor array to store weight parameters, and at the same time can complete the calculation of the input and weight parameters, realizing the integration of storage and calculation, and its power consumption is greatly reduced compared with the traditional von Neumann architecture with separate storage and calculation.

[0019] 2. The inference calculation circuit system proposed by the present invention analyzes the selective state space calculation, designs the selective state space calculation circuit structure, and combines the N*M-dimensional hidden state calculation circuit array and M multiplication-addition circuits to implement the selective state space calculation. The inference of the Mamba block is realized through the circuit, and the circuit uses analog signals for calculation, avoiding the consumption of unnecessary digital-to-analog converters (DACs) and analog-to-digital converters (ADCs). At the same time, compared with the large amount of storage and calculation resources required by a high-precision digital signal calculation system, the resource overhead is further reduced.

[0020] 3. By correctly integrating all the above-mentioned circuit modules, the circuit system realizes the full acceleration of the inference calculation for the Mamba block, reduces redundant data calculations, and significantly improves the calculation efficiency compared with a general GPU. At the same time, through correct integration and control, it can independently and correctly generate the output vector. Therefore, this module can be further used as a basic unit for large-scale integration in complex large model generation tasks.

[0021] 4. Further, in the hidden state calculation circuit provided by the embodiment, U1 and U4 serve as source followers to stably maintain the voltage stored in the capacitor. U2 and U3 together form an adder, and through this circuit design, the addition of A⊙H(t - 1) and S⊙B⊙Xt can be quickly and accurately realized.

[0022] 5. Further, in the root mean square normalization circuit provided by the embodiment, the operational amplifier U5 is used to aggregate the currents of all branches after the square operation. U6 and G6 together realize the square root operation to obtain the result V of the root mean square calculation of the input. RMS ,U7 and G4 are used to realize the division operation between V Ik and V RMS , but the operation result is the opposite number, and the operational amplifier U8 is required to reverse it to obtain the correct division result. Finally, it is multiplied by gi through G5 to quickly and accurately obtain the root mean square normalization result.

[0023] 6. Further, in the e-exponent calculation circuit provided by the embodiment, after G7 performs the square operation, it is divided by two sections of resistors R to realize 1 / 2 V j 2 , and U9 and U10 form an adder to perform the addition of V j and 1 / 2 V j 2 . U11 and U12 also form an adder to realize 1 + V j + 1 / 2V j 2 , and the calculation of the e-exponent through Taylor expansion is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic structural diagram of the Mamba block.

[0025] Figure 2 It is a schematic structural diagram of the inference computing circuit system applicable to the Mamba block in an embodiment of the present invention.

[0026] Figure 3 It is a schematic structural diagram of the memristor array in an embodiment of the present invention.

[0027] Figure 4 It is a schematic structural diagram of the hidden state calculation circuit in an embodiment of the present invention.

[0028] Figure 5 It is a timing diagram of each clock signal in an embodiment of the present invention.

[0029] Figure 6 It is a schematic structural diagram of the root mean square normalization circuit in an embodiment of the present invention.

[0030] Figure 7 It is a schematic structural diagram of the e-exponent calculation circuit in an embodiment of the present invention.

[0031] Figure 8 It is a schematic structural diagram of the Silu activation circuit in an embodiment of the present invention.

[0032] Figure 9 It is a schematic structural diagram of the multiply-accumulate circuit in an embodiment of the present invention.

[0033] Figure 10 It is a schematic structural diagram of the summing circuit in an embodiment of the present invention. Detailed implementation manners

[0034] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0035] For ease of understanding, the working process of the Mamba block is first introduced, as Figure 1The following is a schematic diagram of the structure of the Mamba block. The input vector is first projected and dimensionally elevated to obtain two vectors after projection and dimensional elevation. One of the projected vectors is successively subjected to one-dimensional convolution and Silu activation, and then enters the spatial state calculation part. After completing the spatial state calculation, it performs element-wise multiplication with the other projected and Silu-activated vector. The resulting value is dimensionally reduced through projection to make its dimension the same as that of the input vector. The vector after projection and dimensional reduction is summed with the input vector by residual, and finally the operation of the Mamba block is completed to generate the output vector.

[0036] The Mamba block is a trainable module. In the present invention, it is aimed at the already trained Mamba block and how to implement it through a circuit when put into application. Therefore, the trainable parameters in this module are all determined in advance through training, that is, the parameters stored in all memristor arrays in the present invention are determined in advance.

[0037] As Figure 2 shown is a schematic diagram of the structure of an inference calculation circuit system applicable to the Mamba block in an embodiment of the present invention. This circuit system can be divided into four parts, namely the first circuit structure, the second circuit structure, the selective state space calculation circuit structure, and the result fusion circuit structure. Among them, the first circuit structure implements the Figure 1 pre-normalization, projection, and activation operations in the early stage. The second circuit structure and the selective state space calculation circuit structure implement the Figure 1 selective state space calculation operations in the Figure 1 middle and late stages. The result fusion circuit structure implements the data fusion operations in the middle and late stages. It should be noted that in the circuit, all signals are analog signals, and the elements in the vectors and matrices described in the solution are all analog signals. The following will explain each circuit structure in detail.

[0038] The first circuit structure includes a normalization circuit, the first to second memristor arrays, and an activation circuit. The K-dimensional input vector F is normalized by the normalization circuit to generate the vector F1. The vector F1 is projected twice by the first memristor array to generate the M-dimensional vector F2 and the M-dimensional vector F3. The vector F2 is activated by the activation circuit to generate the M-dimensional vector F4. The vector F3 is subjected to convolution calculation by the second memristor array and then activated by the activation circuit to generate the M-dimensional vector Xt, where t is the time index.

[0039] Specifically, each signal in the K-dimensional input vector F respectively passes through a transistor controlled by a step signal and enters a normalization circuit. After normalization, a K-dimensional vector F1 is obtained. The K-dimensional vector F1 is input into the memristor array 1 for projection. Through projection, the signal can be dimensionally enhanced to obtain an M-dimensional vector F2 and an M-dimensional vector F3. Among them, the M-dimensional vector F3 enters the memristor array 2 for convolution operation, and after an activation operation, an M-dimensional vector Xt is obtained. The M-dimensional vector F2 directly undergoes an activation operation to obtain an M-dimensional vector F4.

[0040] The second circuit structure includes the third to sixth memristor arrays. The vector F1 undergoes projection through the third memristor array to generate an M-dimensional vector S. The vector S performs an element-wise multiplication with each column of the M * N-dimensional fifth memristor array to generate an M * N-dimensional matrix, and the e-exponential calculation circuit performs an e-exponential operation on each element of the matrix to generate an M * N-dimensional matrix A; the vector Xt undergoes two projections through the fourth memristor array to generate an N-dimensional vector B and an N-dimensional vector C; the vector Xt performs an element-wise multiplication through the sixth memristor array to generate an M-dimensional vector D.

[0041] The function of the second circuit structure is to generate the intermediate parameters B, C, and D required for selective state space calculation.

[0042] Specifically, the K-dimensional vector F1 undergoes projection through the memristor array 3 to generate an M-dimensional vector S. The vector S performs an element-wise multiplication with each column of the M * N-dimensional memristor array 5 to generate an M * N-dimensional matrix, and the e-exponential calculation circuit performs an e-exponential operation on each element of the matrix to generate an M * N-dimensional matrix A. Assuming that the weight parameter stored in the memristor array 5 is σ5, then the matrix A = exp(S’⊙σ5), where S’ represents the matrix obtained by replicating the vector S N times. The vector Xt undergoes two projections through the memristor array 4 to generate an N-dimensional vector B and an N-dimensional vector C. The vector Xt performs an element-wise multiplication through the memristor array 6 to generate an M-dimensional vector D. Assuming that the weight parameter stored in the memristor array 6 is σ6, then D = σ6⊙Xt, and ⊙ represents element-wise multiplication. Among them, the element-wise multiplication between vectors refers to the weighted operation of the elements in the same position of the two vectors.

[0043] The selective state space calculation circuit structure includes an N * M-dimensional hidden state calculation circuit array and M multiply-accumulate circuits. The hidden state calculation circuit in the nth row and mth column obtains the mth element Xt in the vector Xt m 、the element A in the mth row and nth column of the matrix A m,n 、the nth element B in the vector B n 、the mth element S in the vector S m to perform hidden state calculation and obtain the state element Ht in the nth row and mth column n,m, the state elements obtained by the hidden state calculation circuit array form an N * M - dimensional state matrix Ht. Each of the M columns in the matrix Ht corresponds one - to - one to the input of M multiply - add circuits to perform a multiply - add operation with vectors C and D, obtaining an M - dimensional vector Yt.

[0044] The selective state space calculation belongs to the most core structure of the Mamba block, and this operation involves complex calculations of multiple parameters. In the Mamba block, the formula for the selective state space calculation is as follows: Yt = C * Ht+D; Ht = A⊙H(t - 1)+S⊙B⊙Xt.

[0045] In the present invention, by analyzing this calculation process, combined with the N * M - dimensional hidden state calculation circuit array and M multiply - add circuits, the selective state space calculation is realized.

[0046] Among them, the hidden state calculation circuit array realizes the calculation of Ht = A⊙H(t - 1)+S⊙B⊙Xt.

[0047] Specifically, the hidden state calculation circuit in the n - th row and m - th column obtains the m - th element Xt in the vector Xt m , the element A in the m - th row and n - th column of the matrix A m,n , the n - th element B in the vector B n , the m - th element S in the vector S m to perform a hidden state calculation, obtaining the state element Ht in the n - th row and m - th column n,m . For example, the hidden state calculation circuit 1_1 obtains Xt 1 , A 1,1 , B 1 , S 1 to perform a hidden state calculation, obtaining Ht 1,1 , the hidden state calculation circuit 1_M obtains Xt M , A M,1 , B 1 , S M to perform a hidden state calculation, obtaining Ht 1,M , the hidden state calculation circuit N_1 obtains Xt 1 , A 1,N , B N , S 1 to perform a hidden state calculation, obtaining Ht N,1 , the hidden state calculation circuit N_M obtains Xt M , A M,N , B N , S M to perform a hidden state calculation, obtaining Ht N,MThe state elements obtained by the hidden state calculation circuit array form an N*M-dimensional state matrix Ht.

[0048] M multiplication and addition circuits implement the calculation of Yt = C*Ht + D.

[0049] Specifically, M columns in the matrix Ht correspond one-to-one to the input of M multiplication and addition circuits for performing multiplication and addition operations with the vector C and the vector D to obtain an M-dimensional vector Yt.

[0050] The result fusion circuit structure includes a multiplication circuit, a seventh memristor array, and a summation circuit. The vector F4 and the vector Yt are element-wise multiplied by the multiplication circuit and then projected by the seventh memristor array to obtain a K-dimensional vector F5. After the vector F5 and the vector F are superimposed by the summation circuit, a K-dimensional output vector is obtained.

[0051] Among them, the purpose of the memristor array 7 is to restore the dimension to the dimension of the output vector.

[0052] As Figure 3 shown is the structural schematic diagram of the memristor array in an embodiment of the present invention. The memristor array includes a plurality of 1T1M memristor units formed in an array form. The memristor in the 1T1M unit is used to store fixed weight values. After the array receives the input signal, it outputs an analog voltage signal after matrix multiplication addition or element multiplication processing. Specifically, the word line WL is used to control the on / off of the corresponding row of memristors. When the circuit starts to work, all WLs are at a high level, the transistor is turned on, and the memristor starts to calculate. Because the conductance of each memristor unit M ij is G ij , that is, G ij = 1 / R ij , the input voltage signal X 1 ~X i , after inputting into the memristor array, the input voltage signal is multiplied by the voltage and conductance of different memristor units to obtain current. In the array, the current is added on one output. I sum1 ~I sumj is the sum of the currents corresponding to the output V 1 ~V j part. After passing through the resistor R s and the operational amplifier for current-to-voltage conversion, the current I sum1 ~I sumj is converted into the corresponding output voltage V 1 ~V j .

[0053] As Figure 4The figure shows a schematic diagram of the structure of the hidden state calculation circuit in an embodiment of the present invention. Each hidden state calculation circuit includes switches S1 to S2, capacitors C1 to C2, operational amplifiers U1 to U4, a first branch multiplier, a second branch multiplier, and a plurality of resistors.

[0054] Taking the hidden state calculation circuit in the nth row and mth column as an example for illustration.

[0055] The non-inverting input terminal of operational amplifier U1 is grounded through capacitor C1 and connected to the output terminal of operational amplifier U4 through switch S1, and the inverting input terminal is connected to its output terminal; The first branch multiplier respectively obtains element A m,n and performs a multiplication operation with the output result of operational amplifier U1, and the multiplication result is connected to the inverting input terminal of operational amplifier U2 through a resistor; The second branch multiplier respectively obtains element S m , element Xt m , element B n and performs a multiplication operation, and the multiplication result is connected to the inverting input terminal of operational amplifier U2 through a resistor; The non-inverting input terminal of operational amplifier U2 is grounded, the inverting input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the inverting input terminal of operational amplifier U3 through a resistor; The non-inverting input terminal of operational amplifier U3 is grounded, the inverting input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the non-inverting input terminal of operational amplifier U4 through switch S2; The non-inverting input terminal of operational amplifier U4 is grounded through capacitor C2, the inverting input terminal is connected to its output terminal, and its output terminal outputs the state element Ht n,m .

[0056] Furthermore, the second branch multiplier includes multiplier G2 and multiplier G3. Multiplier G2 obtains element S m and element Xt m and performs a multiplication operation. Multiplier G3 obtains element B n and the multiplication result of multiplier G2 and performs a multiplication operation, and outputs the multiplication result of the second branch multiplier.

[0057] Among them, switch S1 is controlled by clock signal CL 0 , and switch S2 is controlled by clock signal CL 1 . As Figure 5 shown is the timing diagram of each clock signal in an embodiment of the present invention.

[0058] During the first transfer cycle, switch S2 is turned on and switch S1 is turned off. The hidden state calculation circuit completes the state calculation at the current moment, and operational amplifier U4 outputs the state element. In subsequent transfer cycles, the states of switches S1 and S2 are opposite. In the early stage of the transfer cycle, switch S1 is turned on and switch S2 is turned off, so that the state element H(t - 1) output by U4 at the previous moment (t - 1) n,m is stored in capacitor C1. Then, switch S1 is turned off and switch S2 is turned on, enabling the hidden state calculation circuit to complete the state calculation at the current moment t, and operational amplifier U4 outputs the state element Ht n,m .

[0059] When the circuit is powered on, there will be signal fluctuations for a period of time. When the circuit stabilizes, the step signal becomes high level to turn on, and at the same time the circuit starts to work. The initial voltages of capacitors C1 and C2 are both 0. Capacitor C1 stores H(t - 1), and capacitor C2 stores Ht. In the first cycle, CL 0 is at a low level, that is, switch S1 is open and not closed. In the first half of the cycle, CL 1 is at a low level, and the circuit calculation before switch S2 is performed to calculate Ht = A⊙H(t - 1)+ S⊙B⊙Xt to calculate Ht n,m as an example. As Figure 3 shown, when CL 1 is at a high level, switch S2 closes, and the circuit charges capacitor C2, that is, a new H t is obtained, stored and held. When the next cycle starts, CL 0 is at a high level, CL 1 is at a low level, switch S1 closes, S2 opens, and capacitor C2 charges and discharges capacitor C1 through R c to realize the conversion of the hidden state H t as H t-1 , and at the same time the circuit performs the operation of A⊙H(t - 1)+S⊙B⊙Xt. When CL 0 is at a low level, CL 1 is at a high level, switch S1 opens, switch S2 closes, and capacitor C 2 is charged and discharged to realize the calculation of Ht at the new moment, thus realizing the storage, holding and conversion of Ht, and continuously calculating new outputs by analogy.

[0060] In the hidden state calculation circuit provided in this embodiment, U1 and U4 serve as source followers to stably hold the voltage stored in the capacitor. U2 and U3 together form an adder. Through this circuit design, the addition of A⊙H(t - 1) and S⊙B⊙Xt can be quickly and accurately realized.

[0061] In one embodiment, the normalization circuit is a root mean square (RMS) normalization circuit. The K-dimensional input vector F is normalized by the normalization circuit to generate a vector F1. Among them, the vector F is composed of K voltage signals V I1 ~ V IK .

[0062] The formula for RMS normalization is: V ok =g i ×V Ik / V RMS ; ; In the formula, R / R f =1 / K, where K is the dimension of the input vector, and g i is a trained parameter given by voltage. V ok is the voltage signal after normalization of V Ik , and V RMS is the RMS result.

[0063] As Figure 6 shown, it is a schematic structural diagram of the RMS normalization circuit in an embodiment of the present invention.

[0064] The RMS normalization circuit includes an RMS circuit and K normalization branches. The K normalization branches perform normalization processing in one-to-one correspondence with the K voltage signals. Each normalization branch includes an operational amplifier, a multiplier, and a resistor.

[0065] In the k-th normalization branch: The inverting input terminal of the operational amplifier U7 obtains the voltage signal V Ik through a resistor. Its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U8 through a resistor; The multiplier G4 respectively obtains the output result V RMS of the RMS circuit and the output result of the operational amplifier U7 and performs a multiplication operation. The multiplication result is connected to the inverting input terminal of the operational amplifier U7 through a resistor; The inverting input terminal of the operational amplifier U8 is connected to its output terminal through a resistor, and its non-inverting input terminal is grounded; The multiplier G4 respectively obtains the voltage parameter g i and the output result of the operational amplifier U8 and performs a multiplication operation, and outputs the normalized result V Ik of the voltage signal V Ok .

[0066] In one embodiment, the RMS circuit includes K receiving branches, a multiplier G6, an operational amplifier U5, and an operational amplifier U6. Among them, the K receiving branches respectively receive the K voltage signals V I1 ~ V IK, in each receiving branch, the received voltage signal is first squared by a multiplier and then connected to the inverting input terminal of operational amplifier U5 through a resistor; The non-inverting input terminal of operational amplifier U5 is grounded. Its inverting input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the inverting input terminal of operational amplifier U6 through a resistor; The non-inverting input terminal of operational amplifier U6 is grounded. The signal at the output terminal is squared by multiplier G6 and then connected to the inverting input terminal of operational amplifier U6 through a resistor. The output terminal of operational amplifier U6 outputs the output result V of the root mean square circuit RMS .

[0067] In the root mean square normalization circuit provided in this embodiment, operational amplifier U5 is used to aggregate the currents of all the squared branches, and U6 and G6 together implement the square root operation to obtain the result V of the root mean square calculation of the input RMS , U7 and G4 are used to implement V Ik and V RMS The division operation of, but its operation result is the opposite number, and operational amplifier U8 is needed to reverse it to obtain the correct division result. Finally, it is multiplied by gi through G5 to obtain the root mean square normalization result.

[0068] In one embodiment, the e-exponent calculation circuit calculates the e-exponent in the way of Taylor expansion, and the calculation formula is: V ek =1 + V j + 1 / 2V j 2 ; In the formula, V j is the voltage signal to be calculated for the e-exponent, and V ek is the e-exponent calculation result of V j .

[0069] As Figure 7 shown is the structural schematic diagram of the e-exponent calculation circuit in an embodiment of the present invention.

[0070] The e-exponent calculation circuit includes operational amplifiers U9 to U11, multiplier G7 and resistors; Multiplier G7 accesses the external voltage signal V to be calculated for the e-exponent j and after squaring operation, it is grounded through two resistors; The inverting input terminal of operational amplifier U9 is connected to three branches. The first branch accesses the voltage signal V through a resistor j , the second branch is connected to the other end of the grounding resistor through a resistor, and the third branch is connected to the output terminal of operational amplifier U9 through a resistor. The non-inverting input terminal of operational amplifier U9 is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U10 through a resistor; The inverting input terminal of operational amplifier U10 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U11 through a resistor; The inverting input terminal of operational amplifier U11 is connected to an external 1V voltage source through a resistor and to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U12 through a resistor; The inverting input terminal of operational amplifier U12 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the result V j of the exponential calculation of the voltage signal V ej .

[0071] In the exponential calculation circuit provided in this embodiment, after G7 performs a squaring operation, it is divided by two resistors R to achieve 1 / 2 V j 2 , U9 and U10 form an adder for adding V j and 1 / 2 V j 2 , U11 and U12 also form an adder to achieve 1 + V j + 1 / 2V j 2 , realizing the calculation of the exponential function by Taylor expansion.

[0072] In one embodiment, the activation circuit is a Silu activation circuit, and the calculation formula of Silu activation is: ; In the formula, V i is the voltage signal to be activated, and V o is the activation result of V i .

[0073] As Figure 8 shown is the structural schematic diagram of the Silu activation circuit in an embodiment of the present invention.

[0074] The Silu activation circuit includes an exponential calculation circuit, operational amplifiers U13 to U16, multipliers G8 to G9, and resistors; among them: The exponential calculation circuit is used to obtain the voltage V i to be activated and, after performing exponential calculation, is connected to the inverting input terminal of operational amplifier U13 through a resistor; The inverting input terminal of operational amplifier U13 is connected to an external 1V voltage source through a resistor and to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U14 through a resistor; The inverting input terminal of operational amplifier U14 is connected to its output terminal through a resistor, and its non-inverting input terminal is grounded; The multiplier G8 respectively obtains the voltage V i and the output result of the e-exponent calculation circuit, performs a multiplication operation, and then is connected to the inverting input terminal of the operational amplifier U15 through a resistor; The multiplier G9 respectively obtains the output result of the operational amplifier U14 and the output result of the operational amplifier U15, performs a multiplication operation, and then is connected to the inverting input terminal of U15 through a resistor; The non-inverting input terminal of the operational amplifier U15 is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U16 through a resistor; The inverting input terminal of the operational amplifier U16 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the activation result V of the voltage V i ; o .

[0075] In the Silu activation circuit provided in this embodiment, U13 and U14 together form an adder to complete the addition of the result of the e-exponent calculation circuit and the voltage of 1V. U15 and G9 complete the division operation, but the result is the opposite of the correct value. Therefore, the final U16 is required to perform inversion to obtain the correct Silu activation result.

[0076] Specifically, the multiplication and addition formula executed by the m-th multiplication and addition circuit is: .

[0077] As Figure 9 shown is the structural schematic diagram of the multiplication and addition circuit in an embodiment of the present invention. Each multiplication and addition circuit includes N multiplication branches, operational amplifiers U17~U20, and resistors.

[0078] In the m-th multiplication and addition circuit: The n-th multiplication branch obtains the element Ht in the matrix Ht n,m and the m-th element C in the vector C m performs a multiplication operation and then is connected to the inverting input terminal of the operational amplifier U17 through a resistor; The inverting input terminal of the operational amplifier U17 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U18 through a resistor; The inverting input terminal of the operational amplifier U18 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U19 through a resistor; The inverting input terminal of the operational amplifier U19 accesses the element D in the vector D through a resistor m and is connected to its output terminal through a resistor. Its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U20 through a resistor; The inverting input terminal of the operational amplifier U20 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the m-th element Yt in the vector Yt m .

[0079] In the multiplication and addition circuit provided in this embodiment, U17 and U18 are used to add all the multiplication calculation results. U19 and U20 also jointly form an adder to add with Dm to obtain the final multiplication and addition result.

[0080] As Figure 10 shown is a schematic structural diagram of the summing circuit in an embodiment of the present invention.

[0081] The summing circuit includes operational amplifiers U21~U22 and resistors, where: The inverting input terminal of the operational amplifier U21 accesses the voltage signal V of one element of the vector F5 through a resistor F5 and accesses the voltage signal V of the element at the corresponding position of the vector F through a resistor F , and is also connected to its output terminal through a resistor. Its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U22 through a resistor; The inverting input terminal of the operational amplifier U22 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the superposition result.

[0082] In the summing circuit provided in this embodiment, U21 and U22 jointly form an adder to realize the voltage addition of V F and V F5 .

[0083] The above circuit system applicable to Mamba block inference calculation includes multiple memristor arrays, an in-memory hidden state calculation circuit, a normalization circuit, a Silu activation circuit, a multiplication and addition circuit, and a summing circuit. Among them, the memristor array is responsible for matrix multiplication and addition calculations and element multiplication operations. The in-memory hidden state calculation circuit is used to calculate, store, and transfer the hidden state of the Mamba block. Various functional circuits implement various types of analog signal calculations, including root mean square calculation, Silu activation calculation, multiplication and addition operations, and summing operations. All circuit modules are integrated together in sequence to complete the inference calculation of the Mamba block from the input vector to the output vector.

[0084] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as these combinations of technical features do not conflict, they should be considered as within the scope described in this specification. It should be noted that the "in an embodiment of the present invention", "for example", "for another example", etc. in the present invention are intended to illustrate the present invention and are not used to limit the present invention.

[0085] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention.

Claims

1. An inference calculation circuit system suitable for Mamba block, characterized in that: include; A first circuit structure includes a normalization circuit, a first to a second memristor array and an activation circuit, wherein a K-dimensional input vector F is normalized by the normalization circuit to generate a vector F1, vector F1 is projected twice by the first memristor array to generate an M-dimensional vector F2 and an M-dimensional vector F3, vector F2 is activated by the activation circuit to generate an M-dimensional vector F4, vector F3 is convolved by the second memristor array and then activated by the activation circuit to generate an M-dimensional vector Xt, where t is a time index; The second circuit structure includes the third to sixth memristor arrays, the vector F1 is projected through the third memristor array to generate an M-dimensional vector S, the vector S is element-wise multiplied with each column of the M*N-dimensional fifth memristor array to generate an M*N-dimensional matrix, and the e-exponential operation is performed on each element of the matrix through an e-exponential calculation circuit to generate an M*N-dimensional matrix A; the vector Xt is projected twice through the fourth memristor array to generate an N-dimensional vector B and an N-dimensional vector C; the vector Xt is element-wise multiplied through the sixth memristor array to generate an M-dimensional vector D; The selective state space calculation circuit structure includes an N*M dimensional hidden state calculation circuit array and M multiplication and addition circuits, wherein the hidden state calculation circuit in the nth row and the mth column obtains the mth element Xt in the vector Xt m , the element A in the mth row and nth column of the matrix A m,n , the nth element B in vector B n , the mth element S in the vector S m Perform hidden state calculation to obtain the state element Ht of the nth row and mth column n,m The state elements obtained by the hidden state calculation circuit array constitute an N*M dimensional state matrix Ht. The M columns in the matrix Ht are input into M multiplication and addition circuits one by one to perform multiplication and addition operations with vector C and vector D to obtain an M dimensional vector Yt. The result fusion circuit structure includes a multiplication circuit, a seventh memristor array and a summing circuit. Vector F4 and vector Yt are element-wise multiplied by the multiplication circuit and then projected by the seventh memristor array to obtain a K-dimensional vector F5. Vector F5 and vector F are superimposed by the summing circuit to obtain a K-dimensional output vector.

2. The inference computing circuit system according to claim 1, wherein: Each hidden state calculation circuit includes switches S1-S2, capacitors C1-C2, operational amplifiers U1-U4, a first branch multiplier, a second branch multiplier and a plurality of resistors; In the hidden state calculation circuit at row n and column m: The non-inverting input terminal of the operational amplifier U1 is grounded through the capacitor C1 and connected to the output terminal of the operational amplifier U4 through the switch S1, and the inverting input terminal is connected to its output terminal; The first branch multiplier obtains the element A m,n The multiplication operation is performed with the output result of the operational amplifier U1, and the multiplication result is connected to the inverting input terminal of the operational amplifier U2 through a resistor; The second branch multiplier obtains the elements S m , element Xt m Element B n Perform multiplication operation, and the multiplication result is connected to the inverting input terminal of the operational amplifier U2 through a resistor; The non-inverting input terminal of the operational amplifier U2 is grounded, the inverting input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the inverting input terminal of the operational amplifier U3 through a resistor; The non-inverting input terminal of the operational amplifier U3 is grounded, the inverting input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the non-inverting input terminal of the operational amplifier U4 through a switch S2; The positive input terminal of the operational amplifier U4 is connected to the ground through the capacitor C2, and the negative input terminal is connected to its output terminal, and its output terminal outputs the state element Ht n,m ; Among them, switch S1 is controlled by clock signal CL0, and switch S2 is controlled by clock signal CL1. In the first transfer cycle, switch S2 is turned on and switch S1 is turned off. The hidden state calculation circuit completes the state calculation at the current moment, and op amp U4 outputs the state element. In the subsequent transfer cycle, the states of switches S1 and S2 are opposite. In the early stage of the transfer cycle, switch S1 is turned on and switch S2 is turned off, so that the state element H(t-1) output by U4 at the previous moment (t-1) is n,m After being stored in capacitor C1, switch S1 is turned off and switch S2 is turned on, so that the hidden state calculation circuit completes the state calculation at the current time t, and op amp U4 outputs the state element Ht n,m .

3. The inference calculation circuit system according to claim 2, characterized in that: The second branch multiplier includes a multiplier G2 and a multiplier G3. The multiplier G2 obtains the element S m and element Xt m Perform multiplication operation, multiplier G3 obtains element B n The multiplication result of the multiplier G2 is multiplied together and the multiplication result of the second branch multiplier is output.

4. The inference calculation circuit system according to claim 1, characterized in that: The K-dimensional input vector F is normalized by the normalization circuit to generate a vector F1, wherein the vector F is composed of K voltage signals V I1 ~ V IK composition; The normalization circuit is a root mean square normalization circuit, which includes a root mean square circuit and K normalization branches, the K normalization branches correspond to the K voltage signals one by one and perform normalization processing, and each normalization branch includes an operational amplifier, a multiplier and a resistor; In the kth normalization branch: The inverting input terminal of the operational amplifier U7 obtains the voltage signal V through the resistor. Ik , its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U8 through a resistor; Multiplier G4 obtains the output result V of the RMS circuit respectively RMS The multiplication operation is performed with the output result of the operational amplifier U7, and the multiplication result is connected to the inverting input terminal of the operational amplifier U7 through a resistor; The inverting input terminal of the operational amplifier U8 is connected to its output terminal through a resistor, and its non-inverting input terminal is grounded; Multiplier G4 obtains voltage parameters g i The output of the op amp U8 is multiplied and the output voltage signal V Ik The normalized result V Ok , where g i are the trained parameters.

5. The inference calculation circuit system according to claim 4, characterized in that: The RMS circuit includes K receiving branches, a multiplier G6, an operational amplifier U5 and an operational amplifier U6, wherein: The K receiving branches receive K voltage signals V I1 ~ V IK In each receiving branch, the received voltage signal is firstly squared by a multiplier and then connected to the inverting input terminal of the operational amplifier U5 through a resistor; The non-inverting input terminal of the operational amplifier U5 is grounded, the inverting input terminal thereof is connected to its output terminal via a resistor, and the output terminal thereof is connected to the inverting input terminal of the operational amplifier U6 via a resistor; The positive input terminal of the operational amplifier U6 is grounded, and the signal at the output terminal is squared by the multiplier G6 and then connected to the negative input terminal of the operational amplifier U6 through a resistor. The output terminal of the operational amplifier U6 outputs the output result V of the RMS circuit. RMS .

6. The inference computing circuit system according to claim 1, wherein: The e-index calculation circuit includes operational amplifiers U9-U11, a multiplier G7 and a resistor; Multiplier G7 receives the external voltage signal V to be used for e-exponential calculation. j And after the square operation, it is grounded through two resistors; The inverting input of op amp U9 is connected to three branches. The first branch is connected to the voltage signal V through a resistor. j , the second branch is connected to the other end of the grounding resistor through a resistor, the third branch is connected to the output end of the operational amplifier U9 through a resistor, the non-inverting input end of the operational amplifier U9 is grounded, and its output end is connected to the inverting input end of the operational amplifier U10 through a resistor; The inverting input terminal of the operational amplifier U10 is connected to its output terminal through a resistor, the non-inverting input terminal thereof is grounded, and the output terminal thereof is connected to the inverting input terminal of the operational amplifier U11 through a resistor; The inverting input terminal of the operational amplifier U11 is connected to an external 1V voltage source through a resistor and is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U12 through a resistor; The inverting input terminal of the operational amplifier U12 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs a voltage signal V j The result of e index calculation V ej .

7. The inference calculation circuit system according to any one of claims 1 to 6, characterized in that: The activation circuit is a Silu activation circuit, which includes an e-exponential calculation circuit, operational amplifiers U13-U16, multipliers G8-G9 and resistors; wherein, The e index calculation circuit is used to obtain the voltage V to be activated i After the e exponential calculation is performed, it is connected to the inverting input terminal of the operational amplifier U13 through a resistor; The inverting input terminal of the operational amplifier U13 is connected to an external 1V voltage source through a resistor and is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U14 through a bandgap. The inverting input terminal of the operational amplifier U14 is connected to its output terminal through a resistor, and its non-inverting input terminal is grounded; Multiplier G8 obtains voltage V i The output result of the e-index calculation circuit is multiplied and then connected to the inverting input terminal of the operational amplifier U15 through a resistor; The multiplier G9 obtains the output result of the operational amplifier U14 and the output result of the operational amplifier U15 respectively, performs multiplication operation, and then connects to the inverting input terminal of U15 through a resistor; The non-inverting input terminal of the operational amplifier U15 is grounded, and the output terminal thereof is connected to the inverting input terminal of the operational amplifier U16 through a resistor; The inverting input of the operational amplifier U16 is connected to its output through a resistor, its non-inverting input is grounded, and its output outputs a voltage V i The activation result V o .

8. The inference calculation circuit system according to any one of claims 1 to 6, characterized in that: The mth multiplication and addition circuit is used to obtain the mth column in the matrix Ht, the vector C, and the mth element D in the vector D. m And perform calculations; each multiplication-addition circuit includes N multiplication branches, operational amplifiers U17~U20 and resistors; In the mth multiplication-addition circuit: The nth multiplication branch obtains the element Ht in the matrix Ht n,m The mth element C in the sum vector C m After the multiplication operation, it is connected to the inverting input terminal of the operational amplifier U17 through a resistor; The inverting input terminal of the operational amplifier U17 is connected to its output terminal via a resistor, the non-inverting input terminal thereof is grounded, and the output terminal thereof is connected to the inverting input terminal of the operational amplifier U18 via a resistor; The inverting input terminal of the operational amplifier U18 is connected to its output terminal via a resistor, the non-inverting input terminal thereof is grounded, and the output terminal thereof is connected to the inverting input terminal of the operational amplifier U19 via a resistor; The inverting input of op amp U19 is connected to element D in vector D through a resistor. m and connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U20 through a resistor; The inverting input of the operational amplifier U20 is connected to its output through a resistor, its non-inverting input is grounded, and its output outputs the mth element Yt in the vector Yt. m .

9. The inference calculation circuit system according to any one of claims 1 to 6, characterized in that: The summing circuit is used to superimpose the elements at the same position in the vector F5 and the vector F; The summing circuit includes operational amplifiers U21-U22 and resistors, wherein: The inverting input of the op amp U21 is connected to the voltage signal V of one element of the vector F5 through a resistor. F5 , and access the voltage signal V of the element at the corresponding position of the vector F through a resistor F , and is also connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U22 through a resistor; The inverting input terminal of the operational amplifier U22 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the superposition result.

10. The inference calculation circuit system according to any one of claims 1 to 6, characterized in that: The memristor array is a 1T1M memristor array.

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