In-phase modulation pull-up circuit

Abstract

The invention relates to an in-phase modulation pull-up circuit, which belongs to the technical field of liquid crystal panel driving circuits and comprises a pull-up unit and an in-phase modulation unit. Wherein the pull-up unit is composed of two double-gate regulation thin film transistors, and the in-phase modulation unit is composed of two phase inverters. According to the invention, the problem of insufficient charging of a Q point or poor potential maintaining capability caused by positive and negative offset of threshold voltage on an oxide GOA can be solved at the same time, the stability and uniformity of GOA driving of a liquid crystal display are realized, and the reliability and quality of a liquid crystal display product are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of liquid crystal panel manufacturing. Specifically, the present invention relates to a in-phase modulation pull-up circuit. Background Art

[0002] GOA is the abbreviation of Gate Driven on Array, which means gate drive integration on the array substrate and can realize the function of progressive scanning drive of the liquid crystal panel. In traditional active matrix liquid crystal displays, the row scanning signal is realized by an external integrated circuit (G-COF). When using GOA drive, on the basis that only a few control signals are provided by the external circuit, a row scanning drive circuit is fabricated using the same process as that of thin film transistors (TFTs) to realize the progressive scanning drive function. Therefore, by using GOA drive, the integrated circuits related to scanning drive are saved, and the manufacturing cost of the liquid crystal display is reduced. According to the driving principle of the liquid crystal panel, the row scanning drive circuit actually functions as a shift register. Under the action of the control signal of the external circuit, a shift pulse signal is generated. This shift pulse signal not only drives the pixels of the current row to turn on the TFT, but also serves as the start signal of the next row (the first row is triggered by the frame start signal STV) and the end signal of the previous row for control.

[0003] The GOA drive design reduces the manufacturing cost of the liquid crystal panel. Oxide thin film transistors have become an important part of the next-generation display technology due to their high mobility characteristics. However, due to the threshold voltage offset characteristics of oxide thin film transistors, problems such as uniformity and stability also exist, causing the threshold voltage of the device to shift positively / negatively. As Figure 3 shown, the curve 2 shifts in the direction of curve 1, which easily leads to leakage problems, such as causing leakage in the pull-up unit in GOA, resulting in insufficient holding of the potential at point Q. And the shift of curve 2 to curve 3 easily leads to charging problems, such as insufficient charging in the pull-up unit circuit of GOA. It is difficult to effectively solve the above problems of insufficient charging or weak potential holding ability only from the perspective of process or circuit design. Summary of the Invention

[0004] To solve the above problems, the present invention proposes a in-phase modulation pull-up circuit for solving the problems of insufficient Q-point charging or weak potential holding ability caused by the positive / negative shift of the threshold voltage in oxide GOA.

[0005] The present invention provides a in-phase modulation pull-up circuit, including:

[0006] a pull-up unit and an in-phase modulation unit;

[0007] Wherein, the pull-up unit is composed of a dual-gate controlled thin film transistor T1 and a dual-gate controlled thin film transistor T2, and includes:

[0008] The drain of the dual-gate controlled thin-film transistor T1 is connected to the source of the dual-gate controlled thin-film transistor T2.

[0009] The source of the dual-gate controlled thin-film transistor T1 is used to externally connect to the Q-point terminal of the GOA circuit.

[0010] The drain of the dual-gate controlled thin-film transistor T2 is used to externally connect to the high-level VGH terminal of the GOA circuit.

[0011] The top-gate electrodes of the dual-gate controlled thin-film transistor T1 and the dual-gate controlled thin-film transistor T2 are connected and used to connect to the output electrode of the in-phase modulation unit.

[0012] The bottom-gate electrodes of the dual-gate controlled thin-film transistor T1 and the dual-gate controlled thin-film transistor T2 are connected and used to connect to the input electrode of the in-phase modulation unit and the STN terminal of the externally connected GOA circuit.

[0013] The in-phase modulation unit is composed of an inverter A and an inverter B; among them,

[0014] The high-level electrode of the inverter A is connected to the high-level electrode of the inverter B and used to externally connect to the high-level V GH terminal;

[0015] The low-level electrode of the inverter A is connected to the low-level electrode of the inverter B and used to externally connect to the low-level V SSQ terminal;

[0016] The input electrode of the inverter A serves as the input electrode of the in-phase modulation unit and is used to externally connect to the STN terminal of the GOA circuit.

[0017] The output electrode of the inverter A is connected to the input electrode of the inverter B;

[0018] The output electrode of the inverter B serves as the output electrode of the in-phase modulation unit and is connected to the top-gate electrodes of the dual-gate controlled thin-film transistor T1 and the dual-gate controlled thin-film transistor T2.

[0019] Furthermore, the inverter A is composed of a transistor T3 and a transistor T4, where:

[0020] The drain of the transistor T3 is connected to the gate and serves as the high-level electrode of the inverter A for externally connecting to the high-level V GH terminal;

[0021] The source of the transistor T4 is used to externally connect to the low-level V SSQ terminal.

[0022] Furthermore, the gate of the transistor T4 serves as the input electrode of the inverter A and is used to externally connect to the STN terminal of the GOA circuit.

[0023] Further, the drain of the transistor T4 is connected to the source of the transistor T3, serving as the output electrode of the inverter A and being connected to the input electrode of the inverter B.

[0024] Further, the inverter B is composed of the transistor T5 and the transistor T6, where:

[0025] The drain of the transistor T5 is connected to the gate, serving as the high-level electrode of the inverter B for externally connecting to the high level V of the GOA circuit GH terminal;

[0026] The source of the transistor T6 is used for externally connecting to the low level V of the GOA circuit SSQ terminal.

[0027] Further, the gate of the transistor T6 serves as the input electrode of the inverter B and is connected to the output electrode of the inverter A.

[0028] Further, the drain of the transistor T6 is connected to the source of the transistor T5 to serve as the output electrode of the inverter B.

[0029] Further, the equipotential points with the same function inside the in-phase modulation pull-up circuit are internally electrically connected and have a unified wiring port for the external circuit.

[0030] The advantages of the present invention compared with the prior art are as follows:

[0031] The present invention can simultaneously solve the problems of insufficient Q-point charging or weak potential holding ability caused by the positive and negative shifts of the threshold voltage on the oxide GOA, realize the stability and uniformity of the GOA driving of the liquid crystal display, and improve the reliability and quality of the liquid crystal display product. Description of the Drawings

[0032] Figure 1 is a circuit diagram of an in-phase modulation pull-up circuit provided by an embodiment of the present invention.

[0033] Figure 2 is a connection schematic diagram of an in-phase modulation pull-up circuit applied in a GOA circuit provided by an embodiment of the present invention.

[0034] Figure 3 is a schematic diagram of the offset of the uniformity curve of a conventional high-mobility oxide transistor provided by an embodiment of the present invention.

[0035] Figure 4 is a modulation effect characteristic curve of a pull-up unit provided by an embodiment of the present invention.

[0036] Figure 5 is a modulation effect characteristic curve of an in-phase modulation unit provided by an embodiment of the present invention.

[0037] Figure 6 It is the waveform and timing diagram when a in-phase modulation pull-up circuit provided by an embodiment of the present invention is working. Specific embodiments

[0038] Next, the technical solutions in the embodiments of the present application will be clearly described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0039] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually of the same type, and the number of objects is not limited. For example, the first object can be one or multiple. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the related objects before and after are in an "or" relationship.

[0040] Method embodiment

[0041] The present invention mainly solves the stability problem of GOA driving in a liquid crystal display, and provides an in-phase modulation pull-up circuit, as shown in the attached Figure 1 figure, specifically including:

[0042] A pull-up unit and an in-phase modulation unit;

[0043] Among them, the pull-up unit is composed of dual-gate controlled thin film transistors T1 and T2, including:

[0044] The drain of the dual-gate controlled thin film transistor T1 is connected to the source of the dual-gate controlled thin film transistor T2;

[0045] The source of the dual-gate controlled thin film transistor T1 is used to externally connect to the Q point terminal of the GOA circuit;

[0046] The drain of the dual-gate controlled thin film transistor T2 is used to externally connect to the high-level V GH terminal;

[0047] The top gate electrodes of the dual-gate controlled thin film transistors T1 and T2 are connected and used to connect to the output electrode of the in-phase modulation unit, that is, the T point in the figure;

[0048] The bottom gate electrodes of the dual-gate controlled thin film transistors T1 and T2 are connected and used to connect to the input electrode of the in-phase modulation unit and the STN terminal of the externally connected GOA circuit;

[0049] The in-phase modulation unit is composed of inverter A and inverter B; among them,

[0050] The high-level electrode of inverter A is connected to the high-level electrode of inverter B, and is used to externally connect the high level V GH terminal;

[0051] The low-level electrode of inverter A is connected to the low-level electrode of inverter B, and is used to externally connect the low level V SSQ terminal;

[0052] The input electrode of inverter A serves as the input electrode of the in-phase modulation unit and is used to externally connect the STN terminal of the GOA circuit;

[0053] The output electrode of inverter A is connected to the input electrode of inverter B;

[0054] The output electrode of inverter B serves as the output electrode of the in-phase modulation unit and is connected to the top gate electrodes of double-gate control thin film transistors T1 and T2.

[0055] Further, inverter A is composed of transistor T3 and transistor T4, where:

[0056] The drain of transistor T3 is connected to the gate, and serves as the high-level electrode of inverter A for externally connecting the high level V GH terminal;

[0057] The source of transistor T4 is used to externally connect the low level V SSQ terminal;

[0058] The gate of transistor T4 serves as the input electrode of inverter A and is used to externally connect the STN terminal of the GOA circuit;

[0059] The drain of transistor T4 is connected to the source of transistor T3, and serves as the output electrode of inverter A and is connected to the input electrode of inverter B.

[0060] Further, inverter B is composed of transistor T5 and transistor T6, where:

[0061] The drain of transistor T5 is connected to the gate, and serves as the high-level electrode of inverter B for externally connecting the high level V GH terminal;

[0062] The source of transistor T6 is used to externally connect the low level V SSQ terminal;

[0063] The gate of transistor T6 serves as the input electrode of inverter B and is connected to the output electrode of inverter A;

[0064] The drain of transistor T6 is connected to the source of transistor T5 to serve as the output electrode of inverter B.

[0065] Preferably, in the above circuit structure, the electrode ends of equipotential points with the same function are internally electrically connected and have a unified wiring port for the external circuit. For example, the source of transistor T4 is connected to the source of transistor T6, and the gate of transistor T4 is connected to the bottom gate electrodes of T1 and T2.

[0066] Exemplarily, the in-phase modulation pull-up circuit described in the present invention is arranged in the GOA circuit, as Figure 2 shown.

[0067] Figure 2 In the dashed block diagram in, the pull-up unit of the prior art only has T11 and only has the functions of turning on and off, and cannot perform in-phase modulation of the threshold voltage.

[0068] Figure 2 The in-phase modulation pull-up circuit in is composed of T11, T12, T81, T82, T83, and T84. Among them, the pull-up units are T11 and T12, both of which have a double-gate transistor structure and have the ability of double-gate modulation. Transistors T11 and T12 are mainly used for charging the Q point end of the GOA circuit.

[0069] The threshold voltage of the pull-up unit of the present invention is controllable and adjustable. The double-gate modulation effect curve of the pull-up unit of the present invention is as Figure 4 shown: Under the high-level V GH modulation, the threshold voltage of the Q point end of the pull-up unit has a negative offset, as seen in the V GH modulation curve; under the low-level V SSQ modulation, the threshold voltage of the Q point end of the pull-up unit has a positive offset, as seen in the V SSQ modulation curve. The middle curve is the initial curve without modulation.

[0070] Figure 2 The in-phase modulation unit in is T81, T82, T83, and T84. This unit is connected to V GH at high level and to V SSQ at low level. Its typical input-output characteristics are as Figure 5 shown: When the input is a positive voltage, such as the input is V STNH , its output is V GH ; when the input voltage is a negative voltage, such as the input is V STNL , its output is V SSQ .

[0071] Specific working process:

[0072] 1. During the Q point charging stage, the STN end of the GOA circuit outputs a high potential (V STNH), the transistors T11 and T12 are turned on. Since the input is at a high potential, the T point of the circuit will output V GH (as shown in Figure 5 ). The high potential at the T point will negatively modulate the threshold voltages of T11 and T12 (as shown in Figure 4 ). Thus, the on-state currents of the transistors T11 and T12 are increased, and the charging ability of the transistors is enhanced.

[0073] 2. After the charging of the Q point is completed, the STN outputs a low potential (V STNL ), and the transistors T11 and T12 are turned off. Since the input is at a low potential, the T point of the module will output V SSQ (as shown in Figure 5 ). The low potential at the T point will positively modulate the threshold voltages of T11 and T12 (as shown in Figure 4 ). Thus, the leakage problem of the transistors T11 and T12 is improved.

[0074] The waveforms and timing diagrams during specific operation are as shown in Figure 6 , Figure 6 which contains the waveforms of the STN, T, and Q signals. It can be seen from Figure 6 that the in-phase modulation pull-up circuit adopting the in-phase modulation structure has better pull-up ability and the ability to prevent the potential leakage of the Q point.

[0075] The STN signal of the GOA circuit is a periodic square wave signal, which is used to turn on or off the transistors T11 and T12 within a specified working interval.

[0076] The function of the T signal is to output a square wave signal in the same direction as the STN signal to modulate the threshold voltages of the transistors T11 and T12. When the STN is at a high potential, the T signal outputs V GH to negatively adjust the threshold voltages of the transistors T11 and T12, thereby increasing the on-state currents when the transistors T11 and T12 are turned on, so as to make the potential of the Q point quickly charge to an appropriate voltage as much as possible. When the STN is at a low potential, the T signal outputs V GL to positively adjust the threshold voltages of the transistors T11 and T12, thereby reducing the leakage current when the transistors T11 and T12 are in the off state. So as to keep the potential of the Q point stable.

[0077] The Q signal of the GOA circuit is a static operating point of the circuit, which is used to charge and discharge corresponding voltages within a specified working cycle to turn on or off the transistors T21 and T22, thereby realizing the step-by-step output of the row scanning square wave signal G(N) and the next-level STN signal.

[0078] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them fall within the protection scope of the present application.

Claims

1. A co-phase modulation pull-up circuit, characterized in that: include: A pull-up unit and an in-phase modulation unit; The pull-up unit is composed of a dual-gate control thin film transistor T1 and a dual-gate control thin film transistor T2, including: The drain of the double-gate control thin film transistor T1 is connected to the source of the double-gate control thin film transistor T2; The source of the dual-gate control thin film transistor T1 is used to connect to the Q point of the GOA circuit; The drain of the dual-gate control thin film transistor T2 is used to connect to the high level VGH terminal of the GOA circuit; The top gate electrodes of the dual-gate control thin film transistor T1 and the dual-gate control thin film transistor T2 are connected to each other and are used to connect to the output electrode of the in-phase modulation unit; The bottom gate electrodes of the dual-gate control thin film transistor T1 and the dual-gate control thin film transistor T2 are connected to each other, and are used to connect the input electrode of the in-phase modulation unit and the STN terminal of the external GOA circuit; The in-phase modulation unit is composed of an inverter A and an inverter B; wherein, The high level electrode of inverter A is connected to the high level electrode of inverter B, which is used to connect the high level V of the GOA circuit. GH end; The low level electrode of inverter A is connected to the low level electrode of inverter B, which is used to connect the low level V of the GOA circuit. SSQ end; The input electrode of the inverter A is used as the input electrode of the in-phase modulation unit and is used to connect to the STN terminal of the GOA circuit; The output electrode of inverter A is connected to the input electrode of inverter B; The output electrode of the inverter B serves as the output electrode of the in-phase modulation unit and is connected to the top gate electrodes of the dual-gate control thin film transistor T1 and the dual-gate control thin film transistor T2.

2. The in-phase modulation pull-up circuit according to claim 1, characterized in that: The inverter A is composed of a transistor T3 and a transistor T4, wherein: The drain of the transistor T3 is connected to the gate, and serves as the high level electrode of the inverter A for connecting the high level V of the GOA circuit. GH end; The source of transistor T4 is used to connect the low level V of the GOA circuit. SSQ end.

3. The in-phase modulation pull-up circuit according to claim 2, characterized in that: The gate of the transistor T4 serves as the input electrode of the inverter A and is used to be externally connected to the STN terminal of the GOA circuit.

4. The in-phase modulation pull-up circuit according to claim 2, characterized in that: The drain of the transistor T4 is connected to the source of the transistor T3 , and the output electrode of the inverter A is connected to the input electrode of the inverter B.

5. The in-phase modulation pull-up circuit according to claim 1, characterized in that: The inverter B is composed of a transistor T5 and a transistor T6, wherein: The drain and gate of the transistor T5 are connected to each other, and serve as the high level electrode of the inverter B for connecting to the high level V of the GOA circuit. GH end; The source of transistor T6 is used to connect the low level V of the GOA circuit. SSQ end.

6. The in-phase modulation pull-up circuit according to claim 5, characterized in that: The gate of the transistor T6 serves as the input electrode of the inverter B and is connected to the output electrode of the inverter A.

7. The in-phase modulation pull-up circuit according to claim 5, characterized in that: The drain of the transistor T6 is connected to the source of the transistor T5 as the output electrode of the inverter B.

8. The in-phase modulation pull-up circuit according to claim 1, characterized in that: The equipotential points with the same function inside the in-phase modulation pull-up circuit are internally electrically connected and have a unified wiring port for the external circuit.

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