Semiconductor memory device

Abstract

Disclosed is a semiconductor memory device, and the semiconductor memory device includes: a first chip including: a cell region including memory cells; and a dummy region including a dummy cell transistor; and a second chip including a core circuit and a peripheral circuit configured to control an operation of the memory cell, the first chip and the second chip being stacked in a vertical direction. The dummy region of the first chip may include at least one variable resistor including a dummy cell transistor.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0171494, filed with the Korean Intellectual Property Office on November 30, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments relate to a semiconductor memory device. Background Art

[0003] Semiconductor memory devices are used to store data and are classified into volatile memory devices and non-volatile memory devices. A volatile memory device loses the data stored therein when its power supply is interrupted. A dynamic random access memory (DRAM), a type of volatile memory device, is used in various fields such as mobile systems, servers, or graphic devices.

[0004] Due to an increasing demand for high-density integration of semiconductor memory devices, semiconductor memory devices having a stacked structure are being developed. For example, semiconductor memory devices having a cell-on-periphery (CoP) structure are being developed, in which memory cells for storing data and circuits for driving the memory cells are implemented and then the memory cells and the circuits are stacked on an additional wafer. Summary of the Invention

[0005] Example embodiments provide a semiconductor memory device that can ensure a chip size gain using a CoP structure.

[0006] According to an example embodiment, a semiconductor memory device includes: a first chip including: a cell region including memory cells; and a dummy region including a set of dummy cell transistors; and a second chip including a core circuit and a peripheral circuit configured to control operations of the memory cells, the second chip being stacked on at least a part of the first chip in a vertical direction. The dummy region of the first chip may include at least one variable resistor including the set of dummy cell transistors.

[0007] According to an example embodiment, a semiconductor memory device includes: a first chip including: a cell region including memory cells; and a dummy region including a set of dummy cell transistors; and a second chip including a core circuit and a peripheral circuit configured to control operations of the memory cells, the second chip being stacked with at least a part of the first chip in a vertical direction. The dummy region of the first chip may include: a first variable resistor including a first subset of the dummy cell transistors electrically connected in series with each other among the set of dummy cell transistors; and a second variable resistor including a second subset of the dummy cell transistors electrically connected in series with each other among the set of dummy cell transistors. The second chip may include an amplifier and a transfer transistor. The first variable resistor, the second variable resistor, the amplifier, and the transfer transistor may be included in a low dropout (LDO) regulator.

[0008] According to an example embodiment, a semiconductor memory device includes: a first chip including: a cell region including memory cells; and a dummy region including dummy cell transistors; and a second chip including a core circuit and a peripheral circuit configured to control operations of the memory cells, the first chip and the second chip being stacked in a vertical direction. The dummy cell transistors are vertical channel transistors. The dummy region of the first chip may include a plurality of variable resistors, each variable resistor including the dummy cell transistors electrically connected in series with each other among the dummy cell transistors. A corresponding resistance value of each of the plurality of variable resistors may be independently controlled based on a voltage applied to a gate line of the dummy cell transistors included in the corresponding variable resistor among the dummy cell transistors included in the plurality of variable resistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 is a conceptual diagram showing a configuration of a semiconductor memory device according to an example embodiment.

[0011] Figure 2A is a diagram showing a layout of a semiconductor memory device according to the related art.

[0012] Figure 2B is a diagram showing a layout of a semiconductor memory device according to an example embodiment.

[0013] Figure 2C is a diagram showing a layout of a semiconductor memory device according to an example embodiment.

[0014] Figure 3A is a diagram showing when from Figure 1A diagram showing an example of the structure of a semiconductor memory device according to an exemplary embodiment as observed in the direction “A”.

[0015] Figure 3B Shows Figure 3A A diagram showing an example of a cross-section of a cell region and a core region of a semiconductor memory device.

[0016] Figure 3C Shows Figure 3A A diagram showing an example of a cross-section of a cell region and a core region of a semiconductor memory device.

[0017] Figure 4 Shows when observed in Figure 1 A diagram showing an example of the structure of a semiconductor memory device according to an exemplary embodiment as observed in the direction “A”.

[0018] Figure 5A A diagram showing a dummy cell transistor according to an exemplary embodiment.

[0019] Figure 5B A graph showing the relationship between the gate voltage and the drain current of a dummy cell transistor.

[0020] Figure 5C Shows the use of Figure 5A A diagram showing an example of a variable resistor implemented using a dummy cell transistor.

[0021] Figure 5D A diagram showing the structure of a variable resistor according to an exemplary embodiment.

[0022] Figure 5E Shows using circuit symbols Figure 5D A diagram of a variable resistor.

[0023] Figure 5F A diagram showing the structure of a variable resistor according to an exemplary embodiment.

[0024] Figure 5G Shows using circuit symbols Figure 5F A diagram of a variable resistor.

[0025] Figure 6A A diagram showing the structure of a low dropout (LDO) regulator according to an exemplary embodiment.

[0026] Figure 6B A diagram showing an example of the structure of a semiconductor memory device according to an exemplary embodiment.

[0027] Figure 6C Is Figure 6B An enlarged diagram of an LDO regulator.

[0028] Figure 7A It is a diagram showing the operation of adjusting the output voltage of an LDO regulator.

[0029] Figure 7B It is a diagram showing the operation of adjusting the output voltage of an LDO regulator.

[0030] Figure 7C It is a diagram showing the operation of adjusting the output voltage of an LDO regulator.

[0031] Figure 7D It is a diagram showing the operation of adjusting the output voltage of an LDO regulator.

[0032] Figure 8A It is a diagram showing an example of the configuration of a semiconductor memory device according to an exemplary embodiment.

[0033] Figure 8B It is Figure 8A an enlarged diagram of the voltage divider.

[0034] Figure 9 It is a diagram showing an example of the configuration of a semiconductor memory device according to an exemplary embodiment.

[0035] Figure 10 It is a block diagram showing an example of the configuration of a semiconductor memory system according to an exemplary embodiment.

[0036] Figure 11 It is a block diagram showing an example of a semiconductor memory device according to an exemplary embodiment.

[0037] Figure 12 It is a diagram showing an example of the configuration of a memory cell array according to an exemplary embodiment.

[0038] Figure 13A It is a diagram showing the layout of a memory cell array according to an exemplary embodiment.

[0039] Figure 13B It is a diagram showing Figure 13A a perspective view of the memory cell array.

[0040] Figure 13C It is a cross-sectional view taken along Figure 13A lines X-X1' and Y-Y1'. Detailed Description

[0041] Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings.

[0042] In various exemplary embodiments, terms such as "first", "second", etc. may modify various elements, regardless of the order and / or importance of the corresponding elements, and do not limit the corresponding elements.

[0043] Figure 1 is a conceptual diagram showing the configuration of a semiconductor memory device according to an exemplary embodiment.

[0044] Referring to Figure 1 , the semiconductor memory device 1000 may include a first chip 100 and a second chip 200. The first chip 100 and the second chip 200 may have a stacked structure. For example, the first chip 100 and the second chip 200 may have a cell-on-periphery (CoP) structure.

[0045] The CoP structure may be a structure in which a first wafer including a plurality of memory cells and a second wafer including a core circuit and a peripheral circuit are each manufactured and then the first wafer is stacked on the second wafer to electrically connect the first wafer and the second wafer. Hereinafter, the first wafer on which the memory cells are disposed may be referred to as a cell wafer or a first chip. In addition, the second wafer on which a core circuit and / or a peripheral circuit for controlling the operation of the memory cells is disposed may be referred to as a core / peripheral wafer or a second chip.

[0046] According to an exemplary embodiment, the first chip 100 and the second chip 200 of the CoP structure may be electrically connected to each other by a bonding method. For example, the first chip 100 and the second chip 200 may be electrically connected to each other by bonding a first bonding metal formed at the lowermost part of the first chip 100 and a second bonding metal formed at the uppermost part of the second chip 200. According to an exemplary embodiment, the first chip 100 and the second chip 200 of the CoP structure may be electrically connected to each other by a through-silicon via (TSV) method.

[0047] The first chip 100 may include memory cells. According to an exemplary embodiment, the first chip 100 may include cell regions 110-1 and 110-2 including memory cells, and a remaining region (e.g., a dummy region) 120 that does not include memory cells.

[0048] In an exemplary embodiment, the first chip 100 may include a first cell region 110-1 and a second cell region 110-2 spaced apart from each other. In addition, the first chip 100 may include a dummy region 120 disposed between the first cell region 110-1 and the second cell region 110-2. However, the exemplary embodiment is not limited thereto, and the number and positions of the cell regions and the dummy region may vary according to the exemplary embodiment.

[0049] The unit regions 110-1 and 110-2 may include a memory cell array. The memory cell array may include a plurality of memory cells formed at intersections of word lines and bit lines. According to an example embodiment, the memory cell array may include a plurality of cell array mats divided for each region processed or controlled by a sub-word line driver.

[0050] The second chip 200 may include a core circuit and a peripheral circuit for controlling operations of memory cells included in the first chip 100. The core circuit may include, for example, a sub-word line driver, a bit line sense amplifier, a row decoder (or X decoder), and a column decoder (or Y decoder). The peripheral circuit may include various circuits for decoding commands and controlling input / output of addresses and / or data. For example, the peripheral circuit may include control logic, an address buffer, a delay locked loop (DLL), a data input / output buffer, a power circuit, etc. The power circuit may generate various DC voltages required for operations of the semiconductor memory device 1000.

[0051] The second chip 200 may include a core region 210-1 and 210-2 where the core circuit is disposed, and a peripheral circuit region 220 where the peripheral circuit is disposed. In this case, according to an example embodiment, the core regions 210-1 and 210-2 may correspond to the unit regions 110-1 and 110-2, and the peripheral circuit region 220 may correspond to the dummy region 120. For example, when the first chip 100 and the second chip 200 are bonded, the unit regions 110-1 and 110-2 may be stacked with the core regions 210-1 and 210-2, and the dummy region 120 may be stacked with the peripheral circuit region 220, but the example embodiment is not limited thereto.

[0052] In an example embodiment, the second chip 200 may include a first core region 210-1 and a second core region 210-2. The first core region 210-1 includes a first core circuit corresponding to memory cells included in the first unit region 110-1, and the second core region 210-2 includes a second core circuit corresponding to memory cells included in the second unit region 110-2. In this case, the first core region 210-1 and the second core region 210-2 may be spaced apart from each other. Additionally, the second chip 200 may include a peripheral circuit region 220 disposed between the first core region 210-1 and the second core region 210-2. In this case, the peripheral circuit region 220 may include the above-described peripheral circuit.

[0053] The number and position of the core region and the peripheral circuit region are not limited to the above examples and can vary according to the exemplary embodiments. However, the number and position of the core region of the second chip 200 should correspond to the number and position of the cell regions of the first chip 100, and the number and position of the peripheral circuit region of the second chip 200 should correspond to the number and position of the dummy regions of the first chip 100.

[0054] As described above, the second chip 200 may include a peripheral circuit region 220. Since the peripheral circuits are provided in the peripheral circuit region 220, no core circuits are provided in the peripheral circuit region 220. When there is no corresponding core circuit, the memory cells may be inoperable even though they exist. Therefore, the memory cells may not be provided in the dummy region 120 corresponding to the peripheral circuit region 220. For example, the first chip 100 should include a dummy region, which is the remaining region where no memory cells for data storage are provided.

[0055] According to the exemplary embodiments, a variable resistor can be implemented using the dummy region 120. For example, the dummy region 120 may include dummy cell transistors. The dummy cell transistors can be used as variable resistors in the linear operation region. Therefore, in the exemplary embodiments, a variable resistor can be implemented in the dummy region 120 by connecting the dummy cell transistors in series. In this case, the resistance value of the variable resistor can be controlled by adjusting the gate voltage of the dummy cell transistors connected in series in the linear operation region.

[0056] The variable resistor implemented in the dummy region 120 can be used for the operation of the peripheral circuits. For example, the variable resistor of the dummy region 120 can be used to implement a voltage divider, and the intermediate voltage generated by the voltage divider can be set as the reference voltage of the peripheral circuits. Additionally, the variable resistor in the dummy region 120 can also be used as a variable resistor for adjusting the output voltage of a low dropout (LDO) regulator. However, the exemplary embodiments are not limited thereto, and the variable resistor in the dummy region 120 can be used for various other peripheral circuits that require a variable resistor.

[0057] According to the above embodiments, the variable resistor in the dummy region 120 can be used instead of the active resistor of a general semiconductor memory device. Therefore, a chip size gain of the semiconductor memory device 1000 can be obtained.

[0058] For example, in the case of a general semiconductor memory device, the resistors used in a DC voltage generation circuit or an input / output circuit are implemented as active resistors in a peripheral circuit region (e.g., Figure 2Areference numeral 54). Accordingly, the level of the DC voltage generated by the DC voltage generation circuit or the level of the DC voltage used in the input / output circuit can be adjusted by changing the resistance ratio of the active resistor, for example, by using a test mode register set (TMRS). However, according to an exemplary embodiment, a variable resistor can be implemented using dummy cell transistors included in the dummy region 120 of the first chip 100. Accordingly, the active resistor implemented in the peripheral circuit region in the general semiconductor memory device can be replaced with the variable resistor in the dummy region 120. In this case, a chip size gain can be ensured by the space occupied by the active resistor.

[0059] Hereinafter, reference will be made to Figure 2A and Figure 2B to describe the layout of the semiconductor memory device according to an exemplary embodiment.

[0060] Figure 2A is a diagram showing the layout of a general semiconductor memory device. In the general semiconductor memory device, a memory cell array, a core circuit, and a peripheral circuit can be implemented on a single chip 50.

[0061] Referring to Figure 2A , a cell core including a cell array pad having a predetermined size, a sub-word line driver SWD, a bit line sense amplifier BLSA, and a coupling region Conj can be provided in a first region 51 of the chip 50. The cell core can be provided in a matrix form within the chip 50. For example, when a region 60 of the chip 50 is enlarged, the enlarged region 60 is shown below the arrow. For example, a plurality of sub-word line drivers SWD can be provided between a plurality of cell array pads in one direction, and a plurality of bit line sense amplifiers BLSA can be provided between the cell array pads in another direction. A plurality of coupling regions Conj can be respectively provided between the plurality of sub-word line drivers SWD and the plurality of bit line sense amplifiers BLSA. According to an exemplary embodiment, a DC voltage repeater (or a DC voltage driver) can be provided in the coupling region Conj.

[0062] A row decoder can be arranged in a second region 52 of the chip 50, and a column decoder can be provided in a third region 53 of the chip 50. In addition, control logic, an address buffer, a DLL, a data input / output buffer, a power supply circuit, etc. can be provided in a fourth region 54 of the chip 50.

[0063] Figure 2B is a diagram showing the layout of the semiconductor memory device according to an exemplary embodiment. Referring to Figure 2B , the semiconductor memory device 1000A can have a CoP structure in which a first chip 100A implementing memory cells and a second chip 200A implementing a core circuit and a peripheral circuit are bonded to each other.

[0064] The first chip 100A may include a first cell region 110-1 and a second cell region 110-2. Additionally, the first chip 100A may include a dummy region 120A disposed between the first cell region 110-1 and the second cell region 110-2. Each of the first cell region 110-1 and the second cell region 110-2 may include a plurality of cell array pads 111.

[0065] Compared with the first region 51 of the cell core where Figure 2A it is arranged, there may be no sub-word line driver SWD, bit line sense amplifier BLSA, or conjugation region Conj around each cell array pad 111 of the first chip 100A. In this case, the sub-word line driver SWD, bit line sense amplifier BLSA, and conjugation region Conj for driving each cell array pad 111 may be disposed in the first regions 201 corresponding to the cell array pads 111 in the core regions 210-1 and 210-2 of the second chip 200A.

[0066] The second chip 200A may include a first core region 210-1 and a second core region 210-2. The first core region 210-1 and the second core region 210-2 may respectively correspond to the first cell region 110-1 and the second cell region 110-2. For example, the first core region 210-1 may include a first core circuit corresponding to the cell array pads 111 included in the first cell region 110-1. The second core region 210-2 may include a second core circuit corresponding to the cell array pads 111 included in the second cell region 110-2.

[0067] In this case, the first core circuit and the second core circuit may include a sub-word line driver SWD, a bit line sense amplifier BLSA, and a conjugation region Conj for driving each cell array pad 111. Additionally, according to an exemplary embodiment, the first core circuit and the second core circuit may include a row decoder and a column decoder. The row decoder may be included in the second region 26 in the core regions 210-1 and 210-2, and the column decoder may be included in the third region 27 in the core regions 210-1 and 210-2, but the exemplary embodiment is not limited thereto.

[0068] The second chip 200A may include a peripheral circuit region 220A disposed between a first core region 210-1 and a second core region 210-2. The peripheral circuit region 220A may include peripheral circuits to control the operations of the first core circuit and the second core circuit. For example, the peripheral circuit region 220A may include various circuits for decoding commands and controlling the input and / or output of addresses and data. In an exemplary embodiment, the peripheral circuit region 220A may include control logic, an address buffer, a DLL, a data input / output buffer, a power circuit, etc., but the exemplary embodiment is not limited thereto.

[0069] The core circuits may not be disposed in the peripheral circuit region 220A. Accordingly, memory cells may not be disposed in a dummy region 120A corresponding to the peripheral circuit region 220A. According to an exemplary embodiment, the dummy region 120A may include a plurality of dummy cell transistors. When memory cells are formed in cell regions 110-1 and 110-2, the dummy cell transistors may be formed together in the dummy region 120A, but the exemplary embodiment is not limited thereto. According to an exemplary embodiment, the dummy cell transistors may be vertical channel transistors. The vertical channel transistors may include a channel layer extending in a vertical direction with respect to a substrate of the first chip 100A.

[0070] The dummy region 120A may include variable resistors formed using the dummy cell transistors. For example, the dummy region 120A may include a plurality of variable resistors, each of the plurality of variable resistors including dummy cell transistors connected in series. In this case, the resistance value of each variable resistor may vary according to a voltage applied to a gate electrode of the dummy cell transistors included in the corresponding variable resistor. In some embodiments, the dummy region 120A may include a set of variable resistors, and each variable resistor in the set of variable resistors may include a subset of the dummy cell transistors electrically connected in series with each other among the set of dummy cell transistors.

[0071] The variable resistors implemented in the dummy region 120A may be used in various ways for the operations of the peripheral circuits included in the peripheral circuit region 220A.

[0072] In an exemplary embodiment, the dummy region 120A may include a voltage divider including a plurality of variable resistors connected in series. The voltage divider may generate at least one intermediate voltage based on a power supply voltage applied through a pad formed on an upper portion of the first chip 100A. In this case, the at least one intermediate voltage may have a value obtained by dividing the power supply voltage by a ratio of the resistance values of the variable resistors included in the voltage divider. The intermediate voltage generated by the voltage divider may be provided as a reference voltage to the peripheral circuits among the peripheral circuits included in the peripheral circuit region 220A of the second chip 200A that require a reference voltage.

[0073] In addition, in the exemplary embodiment, the variable resistor in the dummy region 120A can be used as a component of a low dropout (LDO) regulator. For example, the semiconductor memory device 1000A can include an LDO regulator including a first variable resistor and a second variable resistor connected in series, an amplifier, and a transfer transistor. In this case, the variable resistor implemented in the dummy region 120A of the first chip 100A can be used as the first variable resistor and the second variable resistor of the LDO regulator. The amplifier and the transfer transistor can be implemented in the peripheral circuit region 220A of the second chip 200A. The output voltage of the LDO regulator can vary according to the ratio of the resistance values of the first variable resistor and the second variable resistor, and can be used as the power supply for the peripheral circuits included in the peripheral circuit region 220A.

[0074] It should be noted that Figure 2B the layout shown in Figure 2B is only an example, and the layout of the semiconductor memory device 1000A according to the exemplary embodiment is not limited to

[0075] the layout shown in Figure 2C For example, the row decoder and the column decoder can be classified as peripheral circuits rather than core circuits. In this case, as Figure 2B shown in

[0076] Figure 2C is a diagram showing the layout of a semiconductor memory device according to an exemplary embodiment. Referring to Figure 2C , the semiconductor memory device 1000A' can have a CoP structure in which a first chip 100A' that implements memory cells and a second chip 200A' that implements a core circuit and peripheral circuits are bonded to each other.

[0077] The first chip 100A' can include a dummy region 120A' and eight cell regions 110 where memory cells are provided. In this case, the dummy region 120A' can be all regions of the first chip 100A' except for the cell regions 110. As described above, the variable resistor can be implemented in the dummy region 120A'.

[0078] The second chip 200A' can include eight core regions 210 corresponding to the eight cell regions 110 respectively. Each core region 210 can include a sub-word line driver SWD and a bit line sense amplifier BLSA.

[0079] The second chip 200A' may include a peripheral circuit region 220A'. In this case, the peripheral circuit region 220A' may be all regions of the second chip 200A' other than the core region 210. For example, the peripheral circuit region 220A' may include not only the region 220A where the peripheral circuits described in Figure 2B are provided, but also the region 28 where the row decoder is provided and the region 29 where the column decoder is provided.

[0080] Figure 3A is a diagram illustrating an example of the configuration of a semiconductor memory device according to an exemplary embodiment when viewed from direction "A" of Figure 1 . The semiconductor memory device 1000B may be an example of the semiconductor memory devices 1000, 1000A, and 1000A' of Figure 1 , Figure 2B and Figure 2C , but the exemplary embodiment is not limited thereto. Referring to Figure 3A , the semiconductor memory device 1000B may include a first chip 100B and a second chip 200B.

[0081] The first chip 100B and the second chip 200B may have a CoP structure in which the first chip 100B is stacked on the second chip 200B. According to the exemplary embodiment, the first chip 100B and the second chip 200B may be electrically connected to each other by bonding a first bonding metal 10 formed on the lowermost (middle) portion of the first chip 100B to a second bonding metal 20 formed on the uppermost (middle) portion of the second chip 200B. In this case, the materials included in the first bonding metal 10 and the second bonding metal 20 may be copper (Cu). In this case, the bonding method of the first chip 100B and the second chip 200B may be referred to as a Cu-Cu bonding method. However, the exemplary embodiment is not limited thereto. According to the exemplary embodiment, the first bonding metal 10 and the second bonding metal 20 may be formed of other metal materials such as aluminum (Al) or tungsten (W).

[0082] The first chip 100B may include a first cell region 110-1 and a second cell region 110-2. In addition, the first chip 100B may include a dummy region 120B provided between the first cell region 110-1 and the second cell region 110-2. Each of the first cell region 110-1 and the second cell region 110-2 may include memory cells.

[0083] The second chip 200B may include a first core region 210-1 and a second core region 210-2. The first core region 210-1 and the second core region 210-2 may respectively correspond to the first unit region 110-1 and the second unit region 110-2. For example, the first core region 210-1 may include a first core circuit corresponding to memory cells included in the first unit region 110-1. The second core region 210-2 may include a second core circuit corresponding to memory cells included in the second unit region 110-2.

[0084] The second chip 200B may include a peripheral circuit region 220B disposed between the first core region 210-1 and the second core region 210-2. The peripheral circuit region 220B may include peripheral circuits to control the operations of the first core circuit and the second core circuit.

[0085] In some embodiments, the core circuits may not be disposed in the peripheral circuit region 220B. Accordingly, memory cells may not be disposed in the dummy region 120B corresponding to the peripheral circuit region 220B. According to an example embodiment, a variable resistor connected to the peripheral circuits included in the peripheral circuit region 220B may be implemented in the dummy region 120B.

[0086] Each of the first chip 100B and the second chip 200B may include a plurality of metal layers. For example, the first chip 100B may include a plurality of metal layers under the memory cells. The second chip 200B may include a plurality of metal layers over the core circuits and the peripheral circuits.

[0087] According to an example embodiment, signals generated from the core circuits of the second chip 200B may be transmitted to the second bonding metal 20 through the metal layers and vias 42 of the second chip 200B. The signals transmitted to the second bonding metal 20 may be transmitted to the first chip 100B through the first bonding metal 10. The signals transmitted to the first chip 100B may be transmitted to a word line or a bit line connected to the memory cells through the metal layers and vias 41 of the first chip 100B.

[0088] Figure 3B is a cross-section taken along a word line Figure 3A of an example of a unit region and a core region of a semiconductor memory device.

[0089] Referring to Figure 3B , the unit regions 110-1 and 110-2 may include a plurality of memory cells formed at intersections of a plurality of word lines WL and a plurality of bit lines BL. In this case, according to an example embodiment, each memory cell may be a dynamic random access memory (DRAM) cell including a vertical channel transistor 35 and a capacitor 34, but the example embodiment is not limited thereto.

[0090] As described above, the first chip 100B may include a plurality of metal layers 30, 31, 32, and 33 formed under the memory cells. According to an example embodiment, each of the plurality of metal layers 30, 31, 32, and 33 may be implemented using various materials such as aluminum, copper, or tungsten. For example, in an example embodiment, the first metal layer 30 and the second metal layer 31 among the plurality of metal layers 30, 31, 32, and 33 may be copper layers, and the third metal layer 32 and the fourth metal layer 33 may be tungsten layers. However, the example embodiment is not limited thereto. The drive signal transmitted to the sub-word line driver SWD of the first chip 100B through the first bonding metal 10 and the second bonding metal 20 may be applied to the word line WL through the plurality of metal layers 30, 31, 32, and 33 and the via 41.

[0091] The core regions 210-1 and 210-2 may include core circuits corresponding to the memory cells. For example, the core regions 210-1 and 210-2 may include sub-word line drivers SWD disposed under the corresponding unit array pads. For example, unlike the memory cells in the cell regions 110-1 and 110-2, the sub-word line driver SWD may be implemented using horizontal channel transistors. However, the example embodiment is not limited thereto.

[0092] The drive signal generated by the sub-word line driver SWD may be transmitted to the second bonding metal 20 through a plurality of metal layers 71, 72, 73, 74, and 75 formed on the upper portion of the sub-word line driver SWD and the via 42. In this case, according to an example embodiment, each of the plurality of metal layers 71, 72, 73, 74, and 75 included in the core regions 210-1 and 210-2 may be implemented using various materials such as aluminum, copper, or tungsten.

[0093] Figure 3C is a diagram showing an example of a cross-section of a cell region and a core region of a semiconductor memory device taken along a bit line. In the description Figure 3A will omit the description that is repeated with what has already been described in Figure 3C and Figure 3A and Figure 3B will be omitted.

[0094] Referring to Figure 3C , the core regions 210-1 and 210-2 may include bit line sense amplifiers BLSA disposed under the corresponding unit array pads. For example, unlike the memory cells in the cell regions 110-1 and 110-2, the bit line sense amplifier BLSA may be implemented using horizontal channel transistors. However, the example embodiment is not limited thereto.

[0095] When the voltage at the bit line BL changes due to a memory cell connected to a selected word line, a signal corresponding to the voltage change can be transmitted through the plurality of metal layers 30, 31, 32, and 33 and the via 41 to the first bonding metal 10. The signal transmitted to the second chip 200B through the first bonding metal 10 and the second bonding metal 20 can be applied to the bit line sense amplifier BLSA through the plurality of metal layers 71, 72, 73, 74, and 75 and the via 42.

[0096] Figure 3B and Figure 3C FIG. 6 shows an example of a cross-section of the cell regions 110-1 and 110-2 and the core regions 210-1 and 210-2, but each of the dummy region 120B and the peripheral circuit region 220B may also include a plurality of metal layers. For example, the plurality of metal layers 30, 31, 32, and 33 included in the cell regions 110-1 and 110-2 may also be included in the dummy region 120B, and the plurality of metal layers 71, 72, 73, 74, and 75 included in the core regions 210-1 and 210-2 may also be included in the peripheral circuit region 220B.

[0097] Figure 4 is a diagram showing an example of the configuration of a semiconductor memory device according to an exemplary embodiment when viewed from direction "A" of FIG. The semiconductor memory device 1000C may be Figure 1 an example of the semiconductor memory devices 1000, 1000A, 1000A', and 1000B of Figure 1 , Figure 2B , Figure 2C and Figure 3A , but the exemplary embodiment is not limited thereto. In the description Figure 4 of

[0098] reference will be made to Figure 4 FIG. 7, the semiconductor memory device 1000C may include a first chip 100C and a second chip 200C. The first chip 100C may include a pad region. The pad region may be a region where pads electrically connected to an external device are formed. As shown in the drawings, the pad region may be formed on the upper portion of the first chip 100C, but the exemplary embodiment is not limited thereto. Through the pads of the pad region, an address, data, a power supply voltage, etc. may be externally applied to the semiconductor memory device 1000C.

[0099] The dummy region 120C of the first chip 100C may include dummy cell transistors. According to an exemplary embodiment, when memory cells are formed in the cell regions 110-1 and 110-2, the dummy cell transistors may be formed together in one region 121 of the remaining region 120C, but the exemplary embodiment is not limited thereto. As described above, the dummy cell transistors in the dummy region 120C may be used to implement a variable resistor, and the variable resistor implemented in the dummy region 120C may be used in various ways for the operation of the peripheral circuits included in the peripheral circuit region 220B.

[0100] The first chip 100C may include a via 41A connected to the first bonding metal 10 within the dummy region 120C. The second chip 200C may include a via 42A connected to the second bonding metal 20 within the peripheral circuit region 220B. In this case, the via 41A may connect the first bonding metal 10 to a pad in the pad region or connect the first bonding metal 10 to the variable resistor. Additionally, the via 42A may connect the second bonding metal 20 to the peripheral circuit. Accordingly, according to the exemplary embodiment, the variable resistor formed in the dummy region 120C of the first chip 100C may be connected to the peripheral circuit through the via 41A formed in the first chip 100C, the first bonding metal 10, the second bonding metal 20, and the via 42A formed in the second chip 200C.

[0101] Hereinafter, Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F and Figure 5G variable resistors according to various embodiments will be described. Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F and Figure 5G The dummy cell transistors and variable resistors described in

[0102] Figure 5A may all be included in the above-described dummy regions 120, 120A, 120A', 120B, or 120C.

[0102] Figure 5A is a diagram showing a dummy cell transistor according to an exemplary embodiment. Referring to Figure 5A, the dummy cell transistor 70 may be a vertical channel transistor. In this case, the dummy cell transistor 70 may include a channel layer 21, a first gate electrode 22, and a second gate electrode 23. The channel layer 21 has a length that increases in the vertical direction with respect to the substrate of the first chip 100, 100A, 100A', 100B, or 100C. The first gate electrode 22 is disposed on one side of the channel layer 21, and the second gate electrode 23 is disposed on the other side of the channel layer 21.

[0103] For example, the bottom of the channel layer 21 may serve as a first source / drain region (not shown), and the upper portion of the channel layer 21 may serve as a second source / drain region. The portion of the channel layer 21 between the first source / drain region and the second source / drain region may serve as a channel region (not shown).

[0104] The dummy cell transistor 70 may be an N-type metal oxide semiconductor (NMOS) transistor. However, the exemplary embodiments are not limited thereto.

[0105] Figure 5B is a graph showing Figure 5A the relationship between the gate voltage and the drain current of the dummy cell transistor shown. In Figure 5B , V RG represents the first gate voltage applied to the first gate electrode 22, and V RBG represents the second gate voltage applied to the second gate electrode 23.

[0106] Referring to Figure 5B , the drain current of the dummy cell transistor 70 may increase as the gate voltage V RG or V RBG increases in the linear operation region. Since the change in the drain current represents a change in the resistance value, the dummy cell transistor 70 in the linear operation region may operate as a variable resistor having a resistance value adjusted based on the gate voltage V RG or V RBG .

[0107] Figure 5C is a diagram showing an example of a variable resistor implemented using Figure 5A the dummy cell transistor. Referring to Figure 5C , the resistance value of the variable resistor 77 (or the variable resistor R between node A and node B) may change according to at least one of the gate voltages V RG and V RBG . In this case, according to the exemplary embodiments, the gate voltages V RG and V RBG can be independently controlled. In the exemplary embodiments, the gate voltages V RG and V RBGIt may be provided by the DC voltage supply circuits of the peripheral circuit regions 220, 220A, 220A', or 220B, but the exemplary embodiments are not limited thereto.

[0108] Figure 5D and Figure 5E are diagrams showing a variable resistor according to an exemplary embodiment. Figure 5D is a diagram showing the structure of a variable resistor according to an exemplary embodiment, and Figure 5E is a diagram showing the Figure 5D variable resistor using circuit symbols.

[0109] Referring together to Figure 5D and Figure 5E , the variable resistor 80 may include a predetermined number of dummy unit transistors connected in series. In this case, the source regions of each of the dummy unit transistors may be connected to the drain regions of adjacent dummy unit transistors through interconnects 84, and the drain regions of each of the dummy unit transistors may be connected to the source regions of adjacent dummy unit transistors through interconnects 84.

[0110] Each of the dummy unit transistors may include a channel layer 81, a first gate electrode 82, and a second gate electrode 83, with the first gate electrode 82 disposed on one side of the channel layer 81 and the second gate electrode 83 disposed on the other side of the channel layer 81. In this case, the first gate electrodes 82 of the dummy unit transistors included in the variable resistor 80 may be connected to each other to form a first gate line, and the second gate electrodes 83 of the dummy unit transistors included in the variable resistor 80 may be connected to each other to form a second gate line.

[0111] A first gate voltage V RG may be applied to the first gate line, and a second gate voltage V RBG may be applied to the second gate line. Accordingly, the resistance value of the variable resistor 80 may vary according to at least one of the gate voltages V RG and V RBG . In this case, according to an exemplary embodiment, the gate voltages V RG and V RBG may be independently controlled. In an exemplary embodiment, the gate voltages V RG and V RBG may be provided from the DC voltage supply circuits of the peripheral circuit regions 220, 220A, 220A', or 220B, but the exemplary embodiments are not limited thereto.

[0112] Figure 5F and Figure 5G are diagrams showing a variable resistor according to an exemplary embodiment. Figure 5F is a diagram showing the structure of a variable resistor according to an exemplary embodiment, andFigure 5G is a diagram showing a variable resistor using circuit symbols Figure 5F .

[0113] Referring together to Figure 5F and Figure 5G , the dummy regions 120, 120A, 120A', 120B, and 120C may each include a plurality of variable resistors R1 and R2 each including dummy unit transistors connected in series. In this case, the source regions of each of the dummy unit transistors included in the variable resistor R1 or R2 may be connected to the drain regions of adjacent dummy unit transistors through interconnects 94, and the drain regions of each of the dummy unit transistors may be connected to the source regions of adjacent dummy unit transistors through interconnects 94. According to an exemplary embodiment, the first variable resistor R1 and the second variable resistor R2 may be connected in series with each other through an interconnect 95. In some embodiments, the first variable resistor R1 is between node A and node B, and the second variable resistor R2 is between node B and node C.

[0114] Each dummy unit transistor of the first variable resistor R1 may include a channel layer 91-1, a first gate electrode 92-1, and a second gate electrode 93-1, the first gate electrode 92-1 being disposed on one side of the channel layer 91-1, and the second gate electrode 93-1 being disposed on the other side of the channel layer 91-1. In this case, the first gate electrodes 92-1 of the dummy unit transistors included in the first variable resistor R1 may be connected to each other to form a first gate line, and the second gate electrodes 93-1 of the dummy unit transistors included in the first variable resistor R1 may be connected to each other to form a second gate line.

[0115] Each dummy unit transistor of the second variable resistor R2 may also include a channel layer 91-2, a first gate electrode 92-2, and a second gate electrode 93-2. In this case, the first gate electrodes 92-2 of the dummy unit transistors included in the second variable resistor R2 may be connected to each other to form a first gate line, and the second gate electrodes 93-2 of the dummy unit transistors included in the second variable resistor R2 may be connected to each other to form a second gate line.

[0116] A first gate voltage V R1G may be applied to the first gate line of the first variable resistor R1, and a second gate voltage V R1BG may be applied to the second gate line of the first variable resistor R1. Accordingly, the resistance value of the first variable resistor R1 may vary according to at least one of the gate voltages V R1G and V R1BG . In this case, according to an exemplary embodiment, the gate voltages V R1G and V R1BG may be independently controlled.

[0117] The first gate voltage V R2G can be applied to the first gate line of the second variable resistor R2, and the second gate voltage V R2BG can be applied to the second gate line of the second variable resistor R2. Accordingly, the resistance value of the second variable resistor R2 can vary according to at least one of the gate voltages V R2G and V R2BG . In this case, according to the exemplary embodiment, the gate voltages V R2G and V R2BG can be controlled independently.

[0118] In addition, according to the exemplary embodiment, the resistance values of the series-connected variable resistors R1 and R2 can be controlled independently. For example, the gate voltages V R1G and V R2G can be controlled independently. According to the exemplary embodiment, the gate voltages V R1BG and V R2BG can be controlled independently or together.

[0119] In the exemplary embodiment, the gate voltages V R1G , V R2G , V R1BG , and V R2BG can be supplied from the DC voltage supply circuits of the peripheral circuit regions 220, 220A, 220A', and 220B, but the exemplary embodiment is not limited thereto.

[0120] Figure 5F and Figure 5G show examples in which two variable resistors R1 and R2 are connected in series, but the exemplary embodiment is not limited thereto. In some embodiments, three or more variable resistors can be connected in series, and each variable resistor can have an independently controllable resistance value.

[0121] Hereinafter, examples of using the variable resistor according to the exemplary embodiment will be described with reference to Figure 6A , Figure 6B and Figure 6C .

[0122] Figure 6A is a diagram showing the configuration of an LDO voltage regulator according to the exemplary embodiment. Referring to Figure 6A , the LDO voltage regulator 700 can include a first variable resistor R1 and a second variable resistor R2 connected in series, an amplifier 710, and a transfer transistor 720.

[0123] The amplifier 710 can include a first input terminal (-), a second input terminal (+), and an output terminal. The first input terminal (-) is connected to the reference voltage V REF, the second input terminal (+) is commonly connected to one end of the first variable resistor and one end of the second variable resistor, and the output terminal is connected to the gate terminal of the transfer transistor 720. The amplifier 710 can generate an output voltage based on the difference between the feedback voltage V FB input through the second input terminal (+) and the reference voltage V REF input through the first input terminal (-), and the generated output voltage can be applied to the gate terminal of the transfer transistor 720 through the output terminal.

[0124] The transfer transistor 720 can include a gate terminal, a source terminal, and a drain terminal. The gate terminal is connected to the output terminal of the amplifier 710, the source terminal is connected to the power supply voltage VDD, and the drain terminal is connected to the other end of the first variable resistor R1. The transfer transistor 720 can be a P-type metal oxide semiconductor (PMOS) transistor, and can supply a drain current to the other end of the first variable resistor R1 based on the output voltage of the amplifier 710.

[0125] The other end of the second variable resistor R2 can be grounded.

[0126] The output voltage V OUT of the LDO regulator 700 output from the drain terminal of the transfer transistor 720 can vary according to the ratio of the resistance values of the first variable resistor and the second variable resistor.

[0127] For example, when the feedback voltage V FB decreases, the drain current of the transfer transistor 720 can increase, so that the output voltage V OUT of the LDO regulator 700 can increase. On the contrary, when the feedback voltage V FB increases, the drain current of the transfer transistor 720 can decrease, so that the output voltage V OUT of the LDO regulator 700 can decrease. Therefore, the output voltage V FB of the LDO regulator 700 can be controlled by adjusting the feedback voltage V OUT .

[0128] The feedback voltage V FB can be adjusted by the ratio of the resistance values of the first variable resistor R1 and the second variable resistor R2. Therefore, the output voltage V OUT of the LDO regulator 700 can be adjusted by adjusting the resistance values of the first variable resistor R1 and the second variable resistor R2. For example, when the resistance value of the first variable resistor R1 increases or the resistance value of the second variable resistor R2 decreases, the feedback voltage V FB can decrease. Therefore, the output voltage V OUTcan increase. Conversely, when the resistance value of the first variable resistor R1 decreases or the resistance value of the second variable resistor R2 increases, the feedback voltage V FB can increase. Accordingly, the output voltage V of the LDO regulator 700 OUT can decrease.

[0129] Figure 6B is a diagram showing a configuration of a semiconductor memory device according to an exemplary embodiment. The semiconductor memory device 1000D may be an example of the semiconductor memory devices 1000, 1000A, 1000A', 1000B, and 1000C described above, but the exemplary embodiment is not limited thereto. In the description Figure 6B will omit the description that is repeated with the content already described above. According to the exemplary embodiment, the semiconductor memory device 1000D may include the LDO regulator 700 described in Figure 6A .

[0130] Referring to Figure 6B , the semiconductor memory device 1000D may include a first chip 100D and a second chip 200D having a CoP structure. In this case, among the components of the LDO regulator 700 in Figure 6A , a dummy region 120D of the first chip 100D may include a first variable resistor R1 and a second variable resistor R2 connected in series. A peripheral circuit region 220D of the second chip 200D may include Figure 6A the amplifier 710 and the transfer transistor 720 of the LDO regulator 700. The first variable resistor R1 and the second variable resistor R2 of the first chip 100D and the amplifier 710 and the transfer transistor 720 of the second chip 200D may be connected to each other through a first bonding metal 10 and a second bonding metal 20.

[0131] A pad region of the first chip 100D may include a power pad 45. The power supply voltage VDD applied to the first chip 100D through the power pad 45 may be applied to the source terminal of the transfer transistor 720 through the first bonding metal 10 and the second bonding metal 20.

[0132] Although not shown in the drawings, the second chip 200D may include a DC voltage generation circuit to generate a reference voltage V REF . The reference voltage V generated by the DC voltage generation circuit REF may be applied to the first input terminal (-) of the amplifier 710.

[0133] The output voltage V of the LDO regulator OUTIt can vary according to the ratio of the resistance values of the first variable resistor R1 and the second variable resistor R2, and can be used as a power supply for the peripheral circuit included in the peripheral circuit region 220D. Therefore, at least a part of the peripheral circuit of the second chip 200D can use the output voltage V of the LDO regulator 700 OUT operation.

[0134] In an exemplary embodiment, the first chip 100D may include vertical-channel transistors, and the second chip 200D may include horizontal-channel transistors. Therefore, the memory cells included in the cell regions 110-1 and 110-2 and the dummy cell transistors included in the dummy region 120D can be implemented using vertical-channel transistors, and the circuits included in the core regions 210-1 and 210-2 and the peripheral circuit region 220D can be implemented using horizontal-channel transistors.

[0135] Figure 6C is a diagram showing Figure 6B an enlarged view of the LDO regulator. Referring to Figure 6C , the first variable resistor R1 and the second variable resistor R2 can be implemented using the dummy cell transistors included in the dummy region 120D. Each of the first variable resistor R1 and the second variable resistor R2 may include a predetermined number of dummy cell transistors connected in series. In addition, the first variable resistor R1 and the second variable resistor R2 may be connected in series.

[0136] The first gate electrode and the second gate electrode of the dummy cell transistors included in the first variable resistor R1 may form a first gate line and a second gate line, respectively. The first gate voltage V R1G can be applied to the first gate line of the first variable resistor R1, and the second gate voltage V R1BG can be applied to the second gate line of the first variable resistor R1. Therefore, the resistance value of the first variable resistor R1 can vary according to at least one of the gate voltages V R1G and V R1BG . In this case, according to the exemplary embodiment, the gate voltages V R1G and V R1BG can be independently controlled.

[0137] The first gate electrode and the second gate electrode of the dummy cell transistors included in the second variable resistor R2 may also form a first gate line and a second gate line, respectively. The first gate voltage V R2G can be applied to the first gate line of the second variable resistor R2, and the second gate voltage V R2BG can be applied to the second gate line of the second variable resistor R2. Therefore, the resistance value of the second variable resistor R2 can vary according to the gate voltage V R2Gand V R2BG varies according to at least one of them. In this case, according to the exemplary embodiment, the gate voltages V R2G and V R2BG can be controlled independently.

[0138] The resistance values of the series-connected variable resistors R1 and R2 can be controlled independently. For example, the gate voltages V R1G and V R2G can be controlled independently. According to the exemplary embodiment, the gate voltages V R1BG and V R2BG can be controlled independently or together.

[0139] Although not shown in the drawings, the peripheral circuit region 220D may include at least one DC voltage generation circuit that generates the gate voltages V R1G , V R2G , V R1BG and V R2BG . The gate voltages V R1G , V R2G , V R1BG and V R2BG generated by the DC voltage generation circuit can be applied to the first gate line and the second gate line of the variable resistors R1 and R2 through the first bonding metal 10 and the second bonding metal 20.

[0140] Figure 7A , Figure 7B , Figure 7C and Figure 7D are diagrams showing the operation of adjusting the output voltage of the LDO regulator that regulates Figure 6A , Figure 6B and Figure 6C . Figure 7A and Figure 7B show the case where the output voltage of the LDO regulator increases, and Figure 7C and Figure 7D show the case where the output voltage of the LDO regulator decreases.

[0141] As described above, the output voltage V FB of the LDO regulator 700 can be adjusted by adjusting the feedback voltage V OUT . The feedback voltage V FB can be adjusted based on the ratio of the resistance values of the first variable resistor R1 and the second variable resistor R2, so that the output voltage V OUT of the LDO regulator 700 can be adjusted by adjusting the resistance values of the first variable resistor R1 and the second variable resistor R2.

[0142] For example, when the resistance value of the first variable resistor R1 increases or the resistance value of the second variable resistor R2 decreases, the feedback voltage VFB can be decreased. Therefore, the output voltage V of the LDO regulator 700 OUT can be increased.

[0143] Referring together to Figure 5B and Figure 7A , when the gate voltage V R2G and / or V R2BG increases, the drain current of the dummy cell transistor included in the second variable resistor R2 can increase, so that the resistance value of the second variable resistor R2 can be decreased. Referring together to Figure 5B and Figure 7B , when the gate voltage V R1G and / or V R1BG decreases, the drain current of the dummy cell transistor included in the first variable resistor R1 can decrease, so that the resistance value of the first variable resistor R1 can be increased. Therefore, when adjusting the gate voltages V Figure 7A and Figure 7B as shown in R1G V R2G V R1BG and V R2BG , the feedback voltage V of the LDO regulator 700 FB can be decreased. Therefore, the output voltage V of the LDO regulator 700 OUT can be increased.

[0144] When the resistance value of the first variable resistor R1 decreases or the resistance value of the second variable resistor R2 increases, the feedback voltage V FB can be increased. Therefore, the output voltage V of the LDO regulator 700 OUT can be decreased.

[0145] Referring together to Figure 5B and Figure 7C , when the gate voltage V R2G and / or V R2BG decreases, the drain current of the dummy cell transistor included in the second variable resistor R2 can decrease, so that the resistance value of the second variable resistor R2 can be increased. Referring together to Figure 5B and Figure 7D , when the gate voltage V R1G and / or V R1BG increases, the drain current of the dummy cell transistor included in the first variable resistor R1 can increase, so that the resistance value of the first variable resistor R1 can be decreased. Therefore, when adjusting the gate voltages V Figure 7C and Figure 7D as shown in R1G V R2G V R1BG , and V R2BGWhen the feedback voltage V of the LDO regulator 700 FB can be increased. Therefore, the output voltage V of the LDO regulator 700 OUT can be decreased.

[0146] Hereinafter, examples of using a variable resistor according to an exemplary embodiment will be described with reference to Figure 8A and Figure 8B Description of the example using a variable resistor according to an exemplary embodiment.

[0147] Figure 8A is a diagram showing a part of the configuration of a semiconductor memory device according to an exemplary embodiment. The semiconductor memory device 1000E may be an example of the above-described semiconductor memory devices 1000, 1000A, 1000A', 1000B, 1000C, and 1000D, but the exemplary embodiment is not limited thereto. In the description Figure 8A When, descriptions that are repetitive of those already described above will be omitted. According to an exemplary embodiment, the semiconductor memory device 1000E may include a voltage divider.

[0148] Referring to Figure 8A , the semiconductor memory device 1000E may include a first chip 100E and a second chip 200E having a CoP structure. In this case, the dummy region 120E of the first chip 100E may include a voltage divider 800. The voltage divider 800 may include at least two variable resistors connected in series. As described above, the variable resistor included in the voltage divider 800 may be implemented by serially connecting dummy cell transistors in the dummy region 120E.

[0149] The voltage divider 800 may generate at least one intermediate voltage based on the power supply voltage applied through the power supply pad 45. In this case, at least one intermediate voltage may have a value obtained by dividing the power supply voltage by the ratio of the resistance values of the variable resistors included in the voltage divider 800.

[0150] The resistance value of each variable resistor included in the voltage divider 800 may be adjusted based on the gate voltage applied to the gate line of the corresponding variable resistor. Therefore, the intermediate voltage generated by the voltage divider 800 may be adjusted by the gate voltage applied to the variable resistor of the voltage divider 800. In this case, the gate voltage may be provided from a DC voltage generation circuit (abbreviated as DC for short) 65 included in the peripheral region 220E. The gate voltage generated from the DC voltage generation circuit 65 may be applied to the gate line of each variable resistor of the voltage divider 800 through the first bonding metal 10 and the second bonding metal 20.

[0151] The intermediate voltage generated by the voltage divider 800 can be applied to the peripheral circuits P1, P2, and P3 through the first bonding metal 10 and the second bonding metal 20. In this case, the peripheral circuits P1, P2, and P3 can be circuits among the peripheral circuits included in the peripheral circuit region 220E of the second chip 200E that require a reference voltage during operation. Therefore, according to the exemplary embodiment, the peripheral circuits P1, P2, and P3 can operate using the intermediate voltage generated by the voltage divider 800 as a reference voltage.

[0152] In the exemplary embodiment, the first chip 100E can include vertical-channel transistors, and the second chip 200E can include horizontal-channel transistors. Therefore, the memory cells included in the cell regions 110-1 and 110-2 and the dummy cell transistors included in the dummy region 120E can be implemented using vertical-channel transistors, and the circuits included in the core regions 210-1 and 210-2 and the peripheral circuit region 220E can be implemented using horizontal-channel transistors.

[0153] Figure 8B is Figure 8A an enlarged view of the voltage divider. Referring to Figure 8B , the first variable resistor to the fourth variable resistor R1, R2, R3, and R4 included in the voltage divider 800 can be implemented using the dummy cell transistors included in the dummy region 120E. Each of the first variable resistor to the fourth variable resistor R1, R2, R3, and R4 can include a predetermined number of dummy cell transistors connected in series. The first variable resistor to the fourth variable resistor R1, R2, R3, and R4 can be connected in series. In this case, one end of the first variable resistor R1 can be connected to the power supply voltage VDD, and one end of the fourth variable resistor R4 can be grounded.

[0154] The first gate electrode and the second gate electrode of the dummy cell transistors included in the first variable resistor R1 can form the first gate line and the second gate line, respectively. The first gate voltage V R1G can be applied to the first gate line of the first variable resistor R1, and the second gate voltage V R1BG can be applied to the second gate line. Therefore, the resistance value of the first variable resistor R1 can vary according to at least one of the gate voltages V R1G and V R1BG . In this case, according to the exemplary embodiment, the gate voltages V R1G and V R1BG can be independently controlled.

[0155] The first gate electrode and the second gate electrode of the dummy cell transistors included in the second variable resistor R2 can also form the first gate line and the second gate line, respectively. The first gate voltage VR2G can be applied to the first gate line of the second variable resistor R2, and the second gate voltage V R2BG can be applied to the second gate line of the second variable resistor R2. Accordingly, the resistance value of the second variable resistor R2 can be varied in accordance with at least one of the gate voltages V R2G and V R2BG . In this case, according to an exemplary embodiment, the gate voltages V R2G and V R2BG can be controlled independently.

[0156] This concept can be applied to the third variable resistor R3 and the fourth variable resistor R4. For example, the first gate voltage V R3G and the second gate voltage V R3BG can be respectively applied to the first gate line and the second gate line of the third variable resistor R3. In addition, the resistance value of the third variable resistor R3 can be varied in accordance with at least one of the gate voltages V R3G and V R3BG . According to an exemplary embodiment, the gate voltages V R3G and V R3BG can be controlled independently. The first gate voltage V R4G and the second gate voltage V R4BG can be respectively applied to the first gate line and the second gate line of the fourth variable resistor R4. In addition, the resistance value of the fourth variable resistor R4 can be varied in accordance with at least one of the gate voltages V R4G and V R4BG . According to an exemplary embodiment, the gate voltages V R4G and V R4BG can be controlled independently.

[0157] According to an exemplary embodiment, the resistance values of the first variable resistor to the fourth variable resistor R1, R2, R3, and R4 can be controlled independently. For example, the first gate voltages V R1G , V R2G , V R3G and V R4G can be controlled independently. According to an exemplary embodiment, the second gate voltages V R1BG , V R2BG , V R3BG and V R4BG can be controlled independently or together.

[0158] The voltage divider 800 can generate first to third intermediate voltages V R1 , V R2 and V R3 based on the power supply voltage VDD. In this case, the first intermediate voltage V can be generated at the node where the first variable resistor R1 and the second variable resistor R2 are connectedR1 A second intermediate voltage V can be generated at the node where the second variable resistor R2 and the third variable resistor R3 are connected R2 and a third intermediate voltage V can be generated at the node where the third variable resistor R3 and the fourth variable resistor R4 are connected R3 .

[0159] The intermediate voltages V R1 、V R2 and V R3 for each can vary according to the ratio of the resistance values of the first variable resistor to the fourth variable resistor R1, R2, R3, and R4. As described above, the resistance value of the variable resistor can vary according to the gate voltage applied to the corresponding gate line. Therefore, the intermediate voltages V R1G 、V R2G 、V R3G 、V R4G 、V R1BG 、V R2BG 、V R3BG and V R4BG generated by the voltage divider 800 can be controlled by adjusting the gate voltages V R1 、V R2 and V R3 .

[0160] For example, when the first gate voltages V R1G 、V R2G 、V R3G and V R4G can be the same voltage and the second gate voltages V R1BG 、V R2BG 、V R3BG and V R4BG can be the same voltage, the resistance values of the first variable resistor to the fourth variable resistor R1, R2, R3, and R4 can have the same value. In this case, the first intermediate voltage to the third intermediate voltage V R1 、V R2 and V R3 can have values of (3 / 4) VDD, (2 / 4) VDD, and (1 / 4) VDD, respectively. However, the exemplary embodiments are not limited thereto. The gate voltages V R1G 、V R2G 、V R3G 、V R4G 、V R1BG 、V R2BG 、V R3BG and V R4BG can be applied in a manner different from the above example such that the first intermediate voltage to the third intermediate voltage VR1 , V R2 and V R3 can be adjusted to have different values.

[0161] Figure 8B shows that the voltage divider 800 includes four variable resistors R1, R2, R3, and R4 and generates three intermediate voltages V R1 , V R2 and V R3 as an example, but the exemplary embodiments are not limited thereto. The number of variable resistors included in the voltage divider 800 or the number of intermediate voltages generated by the voltage divider 800 may vary according to the exemplary embodiments.

[0162] Hereinafter, an example of using a variable resistor according to an exemplary embodiment will be described with reference to Figure 9 . According to the exemplary embodiment, the intermediate voltage generated by the voltage divider can be monitored. Figure 9 The semiconductor memory device 1000E' has a structure similar to that of the semiconductor memory device 1000E described in Figure 8A and Figure 8B , so a repeated description will be omitted and the differences will be mainly described.

[0163] Referring to Figure 9 , the semiconductor memory device 1000E' may include a first chip 100E' and a second chip 200E' having a CoP structure.

[0164] The first chip 100E' may further include a monitoring pad 47 in the pad region. The monitoring pad 47 may be a pad for monitoring the intermediate voltage generated by the voltage divider 800. The monitoring pad 47 may be connected to a switch unit (SW) 67 of the second chip 200E' through a first bonding metal 10 and a second bonding metal 20.

[0165] The second chip 200E' may include a switch unit 67 in the peripheral circuit region 220E. The switch unit 67 may select one of the intermediate voltages generated by the voltage divider 800 and apply the selected intermediate voltage to the monitoring pad 47 through the first bonding metal 10 and the second bonding metal 20. For example, the intermediate voltage generated by the voltage divider 800 may be applied to the switch unit 67 through the first bonding metal 10 and the second bonding metal 20. A plurality of switches included in the switch unit 67 may be turned on / off under the control of the control logic to select one of the intermediate voltages.

[0166] Figure 10 is a block diagram showing a part of the structure of a semiconductor memory system according to an exemplary embodiment. Referring to Figure 10, the semiconductor memory system 10000 may include a memory controller 2000 and a semiconductor memory device 1000F. The semiconductor memory device 1000F may be an example of the above-described semiconductor memory devices 1000, 1000A, 1000A', 1000B, 1000C, 1000D, 1000E, and 1000E', but the exemplary embodiments are not limited thereto. In the description Figure 10 descriptions that are repetitive of the above-described content will be omitted.

[0167] The memory controller 2000 may control the semiconductor memory device 1000F. For example, the memory controller 2000 may control the semiconductor memory device 1000F based on a request from a processor that supports various applications such as server applications, personal computer (PC) applications, or mobile applications. For example, the memory controller 2000 may be included in a host including a processor and may control the semiconductor memory device 1000F based on a request from the processor.

[0168] The memory controller 2000 may send a clock signal CK, a command CMD, and / or an address ADDR to the semiconductor memory device 1000F to control the semiconductor memory device 1000F. In addition, the memory controller 2000 may send a data signal DQ to the semiconductor memory device 1000F or receive the data signal DQ from the semiconductor memory device 1000F. When the memory controller 2000 reads the data signal DQ from the semiconductor memory device 1000F, the memory controller 2000 may receive a data strobe signal DQS from the semiconductor memory device 1000F.

[0169] The semiconductor memory device 1000F may receive data from the memory controller 2000 and store the received data. The semiconductor memory device 1000F may read the stored data in response to a request from the memory controller 2000 and send the read data to the memory controller 2000.

[0170] In an example embodiment, the semiconductor memory device 1000F may be a memory device including volatile memory cells. For example, the semiconductor memory device 1000F may be various DRAM devices (such as double data rate synchronous dynamic random access memory (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, low power double data rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR4X SDRAM, LPDDR5 SDRAM, graphics double data rate synchronous graphics random access memory (GDDR SGRAM), GDDR2 SGRAM, GDDR3 SGRAM, GDDR4 SGRAM, GDDR5 SGRAM, or GDDR6 SGRAM).

[0171] In an example embodiment, the semiconductor memory device 1000F may be a memory device in which DRAM dies are stacked (such as high bandwidth memory (HBM), HBM2, and HBM3).

[0172] In an example embodiment, the semiconductor memory device 1000F may be a memory module (such as a dual in-line memory module (DIMM)). For example, the semiconductor memory device 1000F may be a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), or a small outline DIMM (SO-DIMM). However, these are merely examples, and the semiconductor memory device 1000F may be another memory module (such as a single in-line memory module (SIMM)).

[0173] In an example embodiment, the semiconductor memory device 1000F may include a static random access memory (SRAM) device, a NAND flash memory device, a NOR flash memory device, a resistive random access memory (RRAM) device, a ferroelectric random access memory (FRAM) device, a phase change random access memory (PRAM) device, a thyristor random access memory (TRAM) device, a magnetic random access memory (MRAM) device, etc.

[0174] The semiconductor memory device 1000F may include a memory cell array 150 and a core / peripheral circuit 300. In this case, the memory cell array 150 may be implemented in the first chips 100, 100A, 100A', 100B, 100C, 100D, 100E, and 100E' described above, and the core / peripheral circuit 300 may be implemented in the second chips 200, 200A, 200A', 200B, 200C, 200D, 200E, and 200E' described above.

[0175] The memory cell array 150 may include a plurality of banks Bank 1 to Bank n, and each of the banks Bank 1 to Bank n may include a plurality of memory cells for storing data. For ease of description, an example in which each bank includes DRAM cells will be provided. However, this is merely an example, and each of the banks Bank 1 to Bank n may be implemented to include volatile memory cells other than DRAM cells. Additionally, each of the banks Bank 1 to Bank n may be implemented to include the same type of memory cells, or may be implemented to include different types of memory cells.

[0176] In this case, according to an exemplary embodiment, each of the banks Bank 1 to Bank n may include a plurality of cell array pads. The cell array pads may represent regions of memory cells divided based on sub-word line drivers.

[0177] The core / peripheral circuit 300 may include various circuits for driving the memory cell array 150. For example, the core / peripheral circuit 300 may include various core circuits (such as bit line sense amplifiers, sub-word line drivers, row decoders (or X decoders), or column decoders (or Y decoders)). The core circuits may be provided in the core regions 210-1 and 210-2 described above. The core / peripheral circuit 300 may include various peripheral circuits (such as control logic for decoding commands, address buffers, delay locked loops (DLLs), data input / output (I / O) circuits, DC circuits, or power circuits). The peripheral circuits may be provided in the peripheral circuit regions 220, 220A, 220A', 220B, 220D, and 220E described above.

[0178] Figure 11 is a block diagram showing an example of a semiconductor memory device according to an exemplary embodiment. Figure 11 The semiconductor memory device 1000F of Figure 10 is an example of the semiconductor memory device 1000F of , but the exemplary embodiments are not limited thereto.

[0179] Refer to Figure 11, the semiconductor memory device 1000F may include a control logic circuit 410, an address register 420, a bank control logic (or bank control circuit) 430, a refresh control circuit 500, a row address multiplexer (or RAM Mux) 440, a column address latch (or CA latch) 450, a row decoder 460, a column decoder 470, a memory cell array 150, an input / output gating circuit 490, an error correction code (ECC) engine 550, and a data input / output buffer 520. Although not shown in Figure 11 , the semiconductor memory device 1000F may include a sub-word line driver and a bit line sense amplifier corresponding to each cell array pad.

[0180] In this case, according to an exemplary embodiment, the memory cell array 150 may be implemented in the first chips 100, 100A, 100A', 100B, 100C, 100D, 100E, and 100E' described above. Additionally, the remaining circuits 410, 420, 430, 440, 450, 460, 470, 490, 500, 520, 550, the sub-word line driver (not shown), and the bit line sense amplifier (not shown) may be implemented in the second chips 200, 200A, 200A', 200B, 200C, 200D, 200E, and 200E' described above.

[0181] For example, a core circuit including a sub-word line driver (not shown), a bit line sense amplifier (not shown), a row decoder 460, and a column decoder 470 may be disposed in the core regions 210-1 and 210-2 of the second chips 200, 200A, 200A', 200B, 200C, 200D, 200E, and 200E'. A peripheral circuit including a control logic circuit 410, an address register 420, a bank control logic 430, a refresh control circuit 500, a row address multiplexer 440, a column address latch 450, an input / output gating circuit 490, an ECC engine 550, and a data input / output buffer 520 may be disposed in the peripheral circuit regions 220, 220A, 220A', 220B, 220D, and 220E of the second chips 200, 200A, 200A', 200B, 200C, 200D, 200E, and 200E'.

[0182] In an exemplary embodiment, referring to Figure 2B and Figure 11, a sub - word - line driver (not shown) and a bit - line sense amplifier (not shown) may be disposed in a first region 201 of the core regions 210 - 1 and 210 - 2. In addition, a row decoder 460 may be disposed in a second region 26 of the core regions 210 - 1 and 210 - 2, and a column decoder 470 may be disposed in a third region 27 of the core regions 210 - 1 and 210 - 2. The control logic circuit 410, the address register 420, the bank control logic 430, the refresh control circuit 500, the row - address multiplexer 440, the column - address latch 450, the input / output gating circuit 490, the ECC engine 550, and the data input / output buffer 520 may be disposed in the peripheral - circuit region 220A, but the exemplary embodiments are not limited thereto.

[0183] The memory cell array 150 may include a plurality of bank arrays 150_1 to 150_n (e.g., a first bank array to an nth bank array). Each of the plurality of bank arrays 150_1 to 150_n may include a plurality of memory cells. For example, each of the plurality of memory cells may be formed at an intersection of a corresponding word line and a corresponding bit line. In this case, each of the plurality of bank arrays 150_1 to 150_n may include a plurality of cell - array pads.

[0184] The row decoder 460 may include a plurality of sub - row decoders 460_1 to 460_n (e.g., a first sub - row decoder to an nth sub - row decoder). Each of the plurality of sub - row decoders 460_1 to 460_n may be connected to a corresponding bank array among the plurality of bank arrays 150_1 to 150_n.

[0185] The column decoder 470 may include a plurality of sub - column decoders 470_1 to 470_n (e.g., a first sub - column decoder to an nth sub - column decoder). Each of the plurality of sub - column decoders 470_1 to 470_n may be connected to a corresponding bank array among the plurality of bank arrays 150_1 to 150_n.

[0186] For example, the plurality of bank arrays 150_1 to 150_n, the plurality of sub - column decoders 470_1 to 470_n, and the plurality of sub - row decoders 460_1 to 460_n may each constitute a plurality of banks. For example, the first bank array 150_1, the first sub - column decoder 470_1, and the first sub - row decoder 460_1 may be included in the first bank.

[0187] The address register 420 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 2000. The address register 420 may provide the received bank address BANK_ADDR to the bank control logic 430, the received row address ROW_ADDR to the row address multiplexer 440, and the received column address COL_ADDR to the column address latch 450.

[0188] The bank control logic 430 may generate bank control signals in response to the bank address BANK_ADDR. For example, the sub - row decoder corresponding to the bank address BANK_ADDR among the plurality of sub - row decoders 460_1 to 460_n may be activated in response to the above - mentioned bank control signals. The sub - column decoder corresponding to the bank address BANK_ADDR among the plurality of sub - column decoders 470_1 to 470_n may be activated in response to the above bank control signals.

[0189] The row address multiplexer 440 may receive the row address ROW_ADDR from the address register 420 and the refresh row address REF_ADDR from the refresh control circuit 500. The row address multiplexer 440 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 440 may be applied to each of the plurality of sub - row decoders 460_1 to 460_n.

[0190] The refresh control circuit 500 may sequentially increase or decrease the refresh row address REF_ADDR in response to a refresh signal from the control logic circuit 410.

[0191] The sub - row decoder selected by the bank control logic 430 among the plurality of sub - row decoders 460_1 to 460_n may activate the word line corresponding to the row address RA output from the row address multiplexer 440. For example, the selected sub - row decoder may apply a driving signal to the word line corresponding to the row address.

[0192] In this case, according to the exemplary embodiment, the driving signal may be applied to the main word line corresponding to the row address. The driving signal applied to the main word line may be applied to the sub - word line driver that drives the word line corresponding to the row address. Accordingly, the word line corresponding to the row address may be activated by the sub - word line driver.

[0193] The column address latch 450 can receive a column address COL_ADDR from the address register 420 and temporarily store the received column address COL_ADDR. Additionally, for example, the column address latch 450 can incrementally increase the received column address COL_ADDR in burst mode. The column address latch 450 can apply the temporarily stored or incrementally increased column address COL_ADDR' to each of the plurality of sub-column decoders 470_1 to 470_n.

[0194] Among the plurality of sub-column decoders 470_1 to 470_n, the sub-column decoder activated by the bank control logic 430 can activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input / output gating circuit 490.

[0195] The input / output gating circuit 490 can include a circuit for gating input / output data. Additionally, the input / output gating circuit 490 can include a data latch for storing a codeword CW output from the plurality of memory banks 150_1 to 150_n, and a write driver for writing data into the plurality of memory banks 150_1 to 150_n.

[0196] In an exemplary embodiment, during a read operation, a codeword CW read from a selected memory bank among the plurality of memory banks 150_1 to 150_n can be sensed by a sense amplifier corresponding to the selected memory bank and stored in the data latch of the input / output gating circuit 490. Additionally, after ECC decoding is performed by the ECC engine 550, the codeword CW stored in the data latch can be provided to the data input / output buffer 520 as data DTA. The data input / output buffer 520 can generate a data signal DQ based on the data DTA and provide the data signal DQ together with a strobe signal DQS to the memory controller 2000.

[0197] In an exemplary embodiment, during a write operation, data DTA to be written into a selected memory bank among the plurality of memory banks 150_1 to 150_n can be received by the data input / output buffer 520 as a data signal DQ. The data input / output buffer 520 can convert the data signal DQ into data DTA and provide the data DTA to the ECC engine 550. The ECC engine 550 can generate a parity bit (or parity data) based on the data DTA and provide a codeword CW including the data DTA and the parity bit to the input / output gating circuit 490. The input / output gating circuit 490 can write the codeword CW into the selected memory bank.

[0198] In a write operation, the data input / output buffer 520 may convert a data signal DQ into data DTA and provide the data DTA to the ECC engine 550. In a read operation, the data input / output buffer 520 may convert the data DTA provided from the ECC engine 550 into a data signal DQ.

[0199] The ECC engine 550 may perform ECC encoding on the data DTA during a write operation. The ECC engine 550 may perform ECC decoding on a codeword CW during a read operation.

[0200] The control logic circuit 410 may control the operation of the semiconductor memory device 1000F. For example, the control logic circuit 410 may generate control signals such that the semiconductor memory device 1000F performs write, read, and refresh operations. The control logic circuit 410 may include a command decoder (or CMD decoder) 411 that decodes a command CMD received from the memory controller 2000, and a mode register set (MRS) 412 that sets an operation mode of the semiconductor memory device 1000F.

[0201] The command decoder 411 may decode the command CMD to generate internal command signals (such as an internal active signal IACT, an internal precharge signal IPRE, an internal read signal IRD, or an internal write signal IWR). Additionally, the command decoder 411 may decode a chip select signal and a command / address signal to generate a control signal corresponding to the command CMD.

[0202] Figure 12 is a diagram showing a part of the configuration of a memory cell array according to an exemplary embodiment. Referring to Figure 12 , the memory cell array 900 may include a plurality of word lines WL0 to WLm, a plurality of bit lines BL0 to BLn, and a plurality of memory cells MC disposed at intersections of the word lines WL0 to WLm and the bit lines BL0 to BLn.

[0203] According to an exemplary embodiment, each memory cell MC may be a DRAM cell. For example, each memory cell MC may include a cell transistor connected to the word line and the bit line, and a cell capacitor connected to the cell transistor. In this case, according to an exemplary embodiment, the cell transistor may be a vertical channel transistor.

[0204] Since the vertical-channel transistor has a structure different from that of the horizontal-channel transistor, the vertical-channel transistor and the horizontal-channel transistor can be implemented using different wafers. For example, the vertical-channel transistor can be implemented on the first chips 100, 100A, 100A', 100B, 100C, 100D, 100E, and 100E', and the horizontal-channel transistor can be implemented on the second chips 200, 200A, 200A', 200B, 200C, 200D, 200E, and 200E'.

[0205] Therefore, according to the exemplary embodiment, the memory cells included in the memory cell array 900 can be implemented in the first chips 100, 100A, 100A', 100B, 100C, 100D, 100E, or 100E' including vertical-channel transistors, and the core circuit and the peripheral circuit can be implemented in the second chips 200, 200A, 200A', 200B, 200C, 200D, 200E, or 200E' including horizontal-channel transistors. Therefore, the semiconductor memory devices 1000, 1000A, 1000A', 1000B, 1000C, 1000D, 1000E, or 1000E' having the CoP structure can be implemented by bonding the first chips 100, 100A, 100A', 100B, 100C, 100D, 100E, or 100E' and the second chips 200, 200A, 200A', 200B, 200C, 200D, 200E, or 200E'.

[0206] The dummy cell transistors can be implemented in the first chips 100, 100A, 100A', 100B, 100C, 100D, 100E, or 100E' including vertical-channel transistors. For example, the dummy cell transistors can be implemented in the dummy regions 120, 120A, 120A', 120B, 120C, 120D, or 120E of the first chips 100, 100A, 100A', 100B, 100C, 100D, 100E, or 100E'. In this case, since the dummy cell transistors are not used for storing data, unlike the cell transistors included in the cell regions 110-1 and 110-2, the dummy cell transistors may not be connected to the cell capacitors. For example, the dummy regions 120, 120A, 120A', 120B, 120C, 120D, and 120E may not include cell capacitors.

[0207] Hereinafter, Figure 13A 、 Figure 13B and Figure 13C the exemplary embodiments of the memory cell array including vertical-channel transistors will be described in more detail. Figure 13A is a diagram showing the layout of the memory cell array according to the exemplary embodiment,Figure 13B is a perspective view showing Figure 13A a memory cell array of Figure 13C and is a cross-sectional view taken along Figure 13A lines X-X1' and Y-Y1' of

[0208] Referring to Figure 13A and Figure 13B and Figure 13C , the memory cell array 900A may include a substrate 610, a plurality of first conductive lines 620, a channel layer 630, a gate electrode 640, a gate insulating layer 650, and a capacitor structure 680. In this case, the memory cell array 900A may include a vertical channel transistor (VCT). The vertical channel transistor may represent a structure in which the channel length of the channel layer 630 extends in a vertical direction from the substrate 610.

[0209] An insulating layer 612 may be disposed on the substrate 610, and the plurality of first conductive lines 620 may be spaced apart from each other in a first direction (X direction) and extend in a second direction (Y direction) on the insulating layer 612. A plurality of first insulating patterns 622 may be disposed on the insulating layer 612 to partially or completely fill the space between the plurality of first conductive lines 620. The plurality of first insulating patterns 622 may extend in the second direction Y, and the upper surfaces of the plurality of first insulating patterns 622 may be disposed at the same height as the upper surfaces of the plurality of first conductive lines 620. The plurality of first conductive lines 620 may serve as bit lines of the memory cell array 900A.

[0210] In an exemplary embodiment, the plurality of first conductive lines 620 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the plurality of first conductive lines 620 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but the exemplary embodiment is not limited thereto. The plurality of first conductive lines 620 may have a single-layer structure or a multi-layer structure including the above materials. In an exemplary embodiment, the plurality of first conductive lines 620 may include two-dimensional semiconductor materials. For example, the two-dimensional semiconductor materials may include graphene, carbon nanotubes, or a combination thereof.

[0211] The channel layer 630 may be arranged to be spaced apart from each other in a first direction (X direction) and a second direction (Y direction) on a plurality of first conductive lines 620, for example, in a matrix form. The channel layer 630 may have a first width in the first direction (X direction) and a first height in a third direction (Z direction). In this case, the first height may be greater than the first width. For example, the first height may be about 2 to 10 times the first width, but the exemplary embodiments are not limited thereto. The bottom of the channel layer 630 may serve as a first source / drain region (not shown), and the upper portion of the channel layer 630 may serve as a second source / drain region (not shown). A portion of the channel layer 630 between the first source / drain region and the second source / drain region may serve as a channel region (not shown).

[0212] In an exemplary embodiment, the channel layer 630 may include an oxide semiconductor. For example, the oxide semiconductor may include In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O, In x Ga yO or a combination thereof. The channel layer 630 may have a single-layer structure or a multi-layer structure including an oxide semiconductor. In some embodiments, the channel layer 630 may have a bandgap energy greater than that of silicon. For example, the channel layer 630 may have a bandgap energy of about 1.5 eV to 5.6 eV. For example, the channel layer 630 may have optimal or excellent channel performance when having a bandgap energy of about 2.0 eV to 4.0 eV. For example, the channel layer 630 may be polycrystalline or amorphous, but the exemplary embodiments are not limited thereto. In the exemplary embodiments, the channel layer 630 may include a two-dimensional semiconductor material. For example, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0213] The gate electrode 640 may extend along a first direction (X direction) on opposite sidewalls of the channel layer 630. The gate electrode 640 may include a first sub-gate electrode 640P1 opposite to the first sidewall of the channel layer 630 and a second sub-gate electrode 640P2 opposite to the second sidewall of the channel layer 630 relative to the first sidewall. Since a single channel layer 630 is disposed between the first sub-gate electrode 640P1 and the second sub-gate electrode 640P2, the memory cell array 900A may have a double-gate transistor structure. However, the exemplary embodiments are not limited thereto, and the second sub-gate electrode 640P2 may be omitted and only the first sub-gate electrode 640P1 opposite to the first sidewall of the channel layer 630 may be formed to implement a single-gate transistor structure.

[0214] The gate electrode 640 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the gate electrode 640 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but the exemplary embodiments are not limited thereto.

[0215] The gate insulating layer 650 may surround the sidewalls of the channel layer 630 and may be disposed between the channel layer 630 and the gate electrode 640. For example, as Figure 13A shown, the entire sidewalls of the channel layer 630 may be surrounded by the gate insulating layer 650, and a part of the sidewalls of the gate electrode 640 may be in contact with the gate insulating layer 650. In some embodiments, the gate insulating layer 650 may extend in the direction in which the gate electrode 640 extends (e.g., the first direction (X direction)), and only two sidewalls of the channel layer 630 opposite to the gate electrode 640 may be in contact with the gate insulating layer 650.

[0216] In an exemplary embodiment, the gate insulating layer 650 may be formed of silicon oxide, silicon nitride, a high-κ dielectric layer having a dielectric constant higher than that of silicon oxide, or a combination thereof. The high-κ dielectric layer may include a metal oxide or a metal oxynitride. For example, the high-κ dielectric layer may be used as the gate insulating layer 650 and include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 , Al 2 O 3 or a combination thereof, but the exemplary embodiment is not limited thereto.

[0217] A plurality of second insulating patterns 632 may extend in a second direction (Y direction) on the plurality of first insulating patterns 622, and the channel layer 630 may be disposed between two adjacent second insulating patterns 632. In addition, a first filling layer 634 and a second filling layer 636 may be disposed in a space between two adjacent channel layers 630 and in a space between two adjacent second insulating patterns 632. The first filling layer 634 may be disposed at the bottom of the space between two adjacent channel layers 630, and the second filling layer 636 may be formed on the first filling layer 634 to partially or completely fill the remaining portion of the space between two adjacent channel layers 630. The upper surface of the second filling layer 636 may be disposed at the same height as the upper surface of the channel layer 630, and the second filling layer 636 may cover the upper surface of the gate electrode 640 or be stacked with the upper surface of the gate electrode 640. In contrast, the plurality of second insulating patterns 632 may include a material layer continuous or adjacent to the plurality of first insulating patterns 622, or the second filling layer 636 may include a material layer continuous or adjacent to the first filling layer 634.

[0218] The capacitor contact 660 may be disposed on the channel layer 630. The capacitor contacts 660 may be disposed to be vertically stacked with the channel layer 630 and be spaced apart from each other, for example, in a matrix form in a first direction (X direction) and a second direction (Y direction). The capacitor contacts 660 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO X or a combination thereof, but the exemplary embodiment is not limited thereto. The upper insulating layer 662 may surround the sidewalls of the capacitor contacts 660 on the plurality of second insulating patterns 632 and the second filling layer 636.

[0219] The etch stop layer 670 may be disposed on the upper insulating layer 662, and the capacitor structure 680 may be disposed on the etch stop layer 670. The capacitor structure 680 may include a lower electrode 682, a capacitor dielectric layer 684, and an upper electrode 686.

[0220] The lower electrode 682 may be electrically connected to the upper surface of the capacitor contact 660. The lower electrode 682 may be formed as a column extending in the third direction (Z direction), but the exemplary embodiments are not limited thereto. In the exemplary embodiments, the lower electrode 682 may be disposed to be vertically stacked with the capacitor contact 660 and disposed to be spaced apart from each other in a matrix form, for example, in the first direction (X direction) and the second direction (Y direction). In contrast, a landing pad (not shown) may also be disposed between the capacitor contact 660 and the lower electrode 682, and thus the lower electrode 682 may be disposed in a hexagonal shape.

[0221] Although not shown in Figure 13B and Figure 13C According to the exemplary embodiments, a plurality of metal layers may be formed in the lower part of the memory cell array 900A. Additionally, a pad region may be formed on the memory cell array 900A.

[0222] According to the exemplary embodiments, when the memory cell array 900A is formed in the cell regions 110-1 and 110-2, the above-described dummy cell transistors may be formed together in the dummy regions 120, 120A, 120A', 120B, 120C, 120D, or 120E, but the exemplary embodiments are not limited thereto. In this case, the capacitor contact 660 or the capacitor structure 680 may not be formed in the dummy regions 120, 120A, 120A', 120B, 120C, 120D, or 120E. Additionally, the length of the gate electrode 640 of the memory cell array 900A and the length of the gate electrode of the dummy cell transistor may be different from each other.

[0223] According to the exemplary embodiments, the above-described dummy cell transistors may be NMOS transistors, but the exemplary embodiments are not limited thereto.

[0224] Although the above description has been made with reference to the case where the dummy cell transistors are vertical channel transistors, the exemplary embodiments are not limited thereto. According to the exemplary embodiments, horizontal channel transistors may be used to form the dummy cell transistors.

[0225] In addition, the above description has been made with reference to the case where the vertical channel transistors include two gate electrodes, but the exemplary embodiments are not limited thereto. According to the exemplary embodiments, vertical channel transistors including a single gate electrode may be used as the dummy cell transistors.

[0226] In addition, although the above description has been made with reference to examples in which two chips (e.g., the first chip 100, 100A, 100A', 100B, 100C, 100D, 100E or 100E' and the second chip 200, 200A, 200A', 200B, 200C, 200D, 200E or 200E') are included in the CoP structure, the example embodiments are not limited thereto. For example, three or more chips may be stacked to implement a semiconductor memory device having a CoP structure. For example, at least one chip having an implemented memory cell array and at least one chip having an implemented core / peripheral circuit may be stacked to implement a semiconductor memory device having a CoP structure.

[0227] According to the various embodiments described above, a variable resistor may be implemented in a dummy region of a semiconductor memory device having a CoP structure. As a result, a chip size gain may be obtained.

[0228] As described above, according to the example embodiments, a variable resistor may be implemented in a dummy region of a semiconductor memory device. As a result, a chip size gain may be obtained.

[0229] Although the example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept defined by the appended claims.

Claims

1. A semiconductor memory device, comprising: A first chip includes: a cell region including a memory cell; and a dummy region including a set of dummy cell transistors; and a second chip including a core circuit and a peripheral circuit configured to control the operation of the memory unit, the second chip being stacked with at least a portion of the first chip in a vertical direction, The dummy region of the first chip includes at least one variable resistor, and the at least one variable resistor includes a set of dummy cell transistors.

2. The semiconductor memory device according to claim 1, wherein The set of dummy cell transistors includes vertical channel transistors.

3. The semiconductor memory device according to claim 2, wherein: The vertical channel transistor includes a first gate electrode on a first side of a channel layer and a second gate electrode on a second side of the channel layer.

4. The semiconductor memory device according to claim 3, wherein: The at least one variable resistor includes a set of variable resistors, each variable resistor in the set of variable resistors includes a subset formed of dummy cell transistors among the set of dummy cell transistors electrically connected in series with each other, and The first gate electrode and the second gate electrode of the subset of dummy cell transistors included in the set of variable resistors correspond to the first gate line and the second gate line, respectively.

5. The semiconductor memory device according to claim 4, wherein: The set of variable resistors includes a first variable resistor and a second variable resistor, wherein a first resistance value of the first variable resistor is configured based on a first voltage and a second voltage respectively applied to a first gate line and a second gate line of the first variable resistor, and The second resistance value of the second variable resistor is configured based on a third voltage and a fourth voltage respectively applied to the first gate line and the second gate line of the second variable resistor.

6. The semiconductor memory device according to claim 5, wherein: The first voltage may be controlled independently of the third voltage.

7. The semiconductor memory device according to claim 1, wherein: The at least one variable resistor includes a plurality of variable resistors, The dummy area of ​​the first chip includes a voltage divider, the voltage divider includes the plurality of variable resistors electrically connected in series, and The voltage divider is configured to generate at least one intermediate voltage based on a ratio of respective resistance values ​​of the plurality of variable resistors included in the voltage divider.

8. The semiconductor memory device according to claim 7, wherein: At least one peripheral circuit among the peripheral circuits of the second chip operates based on the at least one intermediate voltage as a reference voltage.

9. The semiconductor memory device according to claim 1, wherein: The at least one variable resistor includes a third variable resistor and a fourth variable resistor, and the semiconductor memory device further includes: A low voltage dropout regulator comprising a third variable resistor and a fourth variable resistor connected in series, an amplifier and a pass transistor, The dummy area of ​​the first chip includes a third variable resistor and a fourth variable resistor of the low voltage dropout regulator, and The second chip includes an amplifier and a transmission transistor of a low voltage dropout regulator.

10. The semiconductor memory device according to claim 9, wherein: The amplifier includes: a first input terminal configured to receive a reference voltage; a second input terminal electrically connected to a first end of a third variable resistor and a first end of a fourth variable resistor; and an output terminal electrically connected to a gate terminal of a pass transistor, wherein a gate terminal of the transfer transistor is electrically connected to an output terminal of the amplifier, a source terminal of the transfer transistor is electrically connected to a power supply, and a drain terminal of the transfer transistor is electrically connected to a second end of a third variable resistor, and The second end of the fourth variable resistor is electrically connected to the ground.

11. The semiconductor memory device according to claim 10, wherein: The output voltage of the low dropout regulator is configured to be output from the drain terminal of the pass transistor and depends on a ratio of respective resistance values ​​of the third variable resistor and the fourth variable resistor.

12. The semiconductor memory device according to claim 11, wherein At least one of the peripheral circuits of the second chip operates based on an output voltage of the low dropout regulator.

13. The semiconductor memory device according to claim 1, wherein: The first chip and the second chip are electrically connected to each other through a first bonding metal in a lower portion of the first chip and a second bonding metal in an upper portion of the second chip.

14. The semiconductor memory device according to claim 1, wherein: The core circuit includes sub-word line drivers and bit line sense amplifiers, and Wherein, a first peripheral circuit among the peripheral circuits is configured to decode a command, and a second peripheral circuit among the peripheral circuits is configured to control input and / or output of an address and data.

15. The semiconductor memory device according to claim 14, wherein: The second chip includes a core region corresponding to the cell region and a peripheral circuit region corresponding to the dummy region, and The core area and the peripheral circuit area include core circuits and peripheral circuits respectively.

16. A semiconductor memory device comprising: A first chip includes: a cell region including a memory cell; and a dummy region including a set of dummy cell transistors; and a second chip including a core circuit and a peripheral circuit configured to control the operation of the memory unit, the second chip being stacked with at least a portion of the first chip in a vertical direction, The dummy area of ​​the first chip includes: a first variable resistor including a first subset formed of dummy cell transistors electrically connected in series with each other among the set of dummy cell transistors; and a second variable resistor including a second subset formed of dummy cell transistors electrically connected in series with each other among the set of dummy cell transistors, The second chip includes an amplifier and a transmission transistor, and The first and second variable resistors, the amplifier and the transmission transistor are included in a low voltage dropout regulator.

17. The semiconductor memory device according to claim 16, wherein: A first subset of dummy cell transistors includes vertical channel transistors that share a first gate line, and The second subset of dummy cell transistors includes vertical channel transistors that share a second gate line.

18. The semiconductor memory device according to claim 17, wherein: A first resistance value of the first variable resistor and a second resistance value of the second variable resistor are independently controlled based on a first voltage applied to the first gate line and a second voltage applied to the second gate line, respectively, and The output voltage of the low voltage dropout regulator depends on the ratio of the first resistance value to the second resistance value.

19. The semiconductor memory device according to claim 16, further comprising: a first bonding metal in a lower portion of the first chip; as well as The second bonding metal, in the upper portion of the second chip, The first bonding metal and the second bonding metal are configured to electrically connect the first chip and the second chip, and The first variable resistor and the second variable resistor are electrically connected to the amplifier and the transfer transistor through the first bonding metal and the second bonding metal.

20. A semiconductor memory device comprising: A first chip includes: a cell region including a memory cell; and a dummy region including a dummy cell transistor; and a second chip including a core circuit and a peripheral circuit configured to control the operation of the memory cell, the first chip and the second chip being stacked in a vertical direction, Among them, the dummy cell transistor is a vertical channel transistor, The dummy region of the first chip includes a plurality of variable resistors, each variable resistor includes dummy unit transistors electrically connected in series with each other among the dummy unit transistors, and wherein a corresponding resistance value of each of the plurality of variable resistors is independently controlled based on a voltage applied to a gate line of a dummy cell transistor included in a corresponding one of the plurality of variable resistors.

Images