On-chip termination signal generation circuit and memory system

Abstract

The invention provides an on-chip termination signal generation circuit and a storage system, the on-chip termination signal generation circuit is applied to the storage system, the storage system comprises a memory with an on-chip termination control circuit, and the on-chip termination signal generation circuit comprises a generation circuit, a time delay circuit and an output circuit; the generation circuit is used for receiving the initial signal, responding to a clock signal and outputting a first signal and an indication signal; wherein the indication signal is used for indicating a first burst length; the effective level period of the first signal is a first duration; the time delay circuit is used for carrying out time delay processing on the first signal and outputting a second signal; the output circuit is used for receiving the indication signal and the second signal and outputting an on-chip termination signal; the width of the active level of the on-chip termination signal is generated according to the indication signal. The on-chip termination signal generating circuit is used for generating the on-chip termination signal for controlling the state of the termination circuit so as to ensure the accuracy of data writing.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and particularly to an on-die termination signal generation circuit and a storage system. Background Art

[0002] Currently, an on-die termination (ODT) control circuit is usually provided in a memory. The on-die termination control circuit adjusts the mode of a termination resistance (RTT) based on an on-die termination signal generated by an on-die termination signal generation circuit, so as to reduce signal reflection.

[0003] Therefore, how to design an ODT generation circuit to control the state of the RTT is the problem to be solved by the present disclosure. Summary of the Invention

[0004] The on-die termination signal generation circuit and the storage system provided by the present disclosure are used to provide an on-die termination signal generation circuit to effectively control the RTT.

[0005] In a first aspect, the present disclosure provides an on-die termination signal generation circuit, which is applied to a storage system. The storage system includes a memory having an on-die termination control circuit. The on-die termination signal generation circuit includes: a generation circuit, a delay circuit, and an output circuit. Among them,

[0006] The generation circuit is configured to receive an initial signal, and in response to a clock signal, output a first signal and an indication signal. Among them, the initial signal is used to indicate the state of the termination resistance of an adjustment data terminal; the indication signal is used to indicate a first burst length; the first burst length is the current burst length of the memory; the effective level period of the first signal is a first duration.

[0007] The delay circuit is configured to receive the first signal, perform a delay process on the first signal, and output a second signal.

[0008] The output circuit is configured to receive the indication signal and the second signal, and output an on-die termination signal. The on-die termination control circuit receives the on-die termination signal to adjust the state of the termination resistance of the data terminal. Among them, the width of the effective level of the on-die termination signal is selected and generated according to the indication signal.

[0009] In some embodiments, the first duration is a fixed value of the data writing duration corresponding to a second burst length; the second burst length is the minimum value among the burst lengths supported by the memory.

[0010] Alternatively, the first duration is a fixed value less than the data writing duration corresponding to the second burst length.

[0011] In some embodiments, the generation circuit includes: a first generation module, a first acquisition module, and a first encoding module; the encoding module is connected to the first acquisition module;

[0012] The first generation module is configured to generate a first signal in response to the received initial signal and clock signal;

[0013] The first acquisition module is configured to determine the first burst length in a first register in response to the received initial signal, and output the first burst length;

[0014] The first encoding module is configured to receive the first burst length, and output an indication signal according to the first burst length and a first correspondence; the first correspondence represents the correspondence between the burst length and the indication signal.

[0015] In some embodiments, if the first burst length is greater than the third burst length, the first duration is the data write duration corresponding to the third burst length; the third burst length is a value selected from the remaining values other than the maximum value among the burst lengths supported by the memory.

[0016] In some embodiments, the generation circuit includes: a second acquisition module, a comparison module, a second generation module, and a second encoding module;

[0017] The second acquisition module is configured to determine the first burst length in a first register in response to the received initial signal, and output the first burst length;

[0018] The comparison module is configured to receive the first burst length, and output a comparison result according to the first burst length and the third burst length; the comparison result is used to represent the magnitude relationship between the first burst length and the third burst length;

[0019] The second generation module is configured to output a first signal if it is determined that the comparison result represents that the first burst length is greater than the third burst length;

[0020] The second encoding module is configured to receive the first burst length, and output an indication signal according to the first burst length and a second correspondence; the second correspondence represents the correspondence between the burst length and the indication signal.

[0021] In some embodiments, the generation circuit further includes:

[0022] A third generation module, the third generation module is connected to the comparison module, and the third generation module is configured to generate a third signal with an active level width of a second value if it is determined that the comparison result indicates that the first burst length is less than or equal to the third burst length, determine the third signal as the first signal, and output the first signal to the delay circuit; the second value is the data writing duration corresponding to the first burst length.

[0023] In some embodiments, the output circuit includes a data selector and a plurality of first processing modules; wherein,

[0024] The first processing module is configured to receive the second signal and increase the width of the active level of the second signal to obtain a first candidate signal; wherein, the widths of the active levels of the first candidate signals output by different first processing modules are different;

[0025] The data selector is configured to receive the indication signal output by the generation circuit and the first candidate signal, and determine and output the on-chip termination signal from among the plurality of first candidate signals according to the indication signal.

[0026] In some embodiments, the output circuit includes: a plurality of second processing modules, and switch modules corresponding to the second processing modules;

[0027] The second processing module is configured to receive the second signal and increase the width of the active level of the second signal to obtain a second candidate signal; wherein, the widths of the active levels of the second candidate signals output by different second processing modules are different;

[0028] The switch module is configured to receive the indication signal, and in response to the indication signal, control the switch module to conduct, determine the second candidate signal generated by the second processing module connected to the switch module as the on-chip termination signal, and output the on-chip termination signal.

[0029] In some embodiments, the delay duration between the active edge of the second signal and the active edge of the first signal is the difference between a third value and a first loss time;

[0030] wherein, the third value is the sum of the write delay of the memory and the state switching duration of the termination resistor; the first loss time is the transmission time from the output end of the on-chip termination signal to the receiving end of the on-chip termination signal.

[0031] In some embodiments, the delay circuit includes a sampling module and a third processing module; the sampling module is connected to the third processing module;

[0032] The sampling module is configured to receive the first signal and sample the first signal in response to the clock signal; if it is determined that the level value of the sampled signal is a valid value, a shift signal is output; the width of the active level period of the shift signal is the same as the width of the active level period of the first signal;

[0033] The third processing module is configured to perform a delay process on the received shift signal according to a preset delay duration and output a second signal, where the preset delay duration is the difference between the third value and the second loss time; the second loss time is the difference between the time when the sampling module samples the valid value of the first signal and the time when the sampling module receives the first signal at the valid value.

[0034] In a second aspect, the present disclosure provides a storage system, which includes a memory having an on-chip termination control circuit and an on-chip termination signal generation circuit as described in any one of the first aspects.

[0035] The on-chip termination signal generation circuit and the storage system provided by the present disclosure are applied to a storage system, which includes a memory having an on-chip termination control circuit. The on-chip termination signal generation circuit includes: a generation circuit, a delay circuit, and an output circuit; wherein, the generation circuit is configured to receive an initial signal and output a first signal and an indication signal in response to a clock signal; wherein, the initial signal is used to indicate the state of the termination resistor of the adjustment data terminal; the indication signal is used to indicate a first burst length; the first burst length is the current burst length of the memory; the active level period of the first signal is a first duration; the delay circuit is configured to receive the first signal and perform a delay process on the first signal to output a second signal; the output circuit is configured to receive the indication signal and the second signal and output an on-chip termination signal, and the on-chip termination control circuit receives the on-chip termination signal to adjust the state of the termination resistor of the data terminal; wherein, the width of the active level of the on-chip termination signal is selected and generated according to the indication signal. Further, an on-chip termination signal for controlling the RTT state is generated based on the above on-chip termination signal generation circuit to ensure the accuracy of data writing. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0037] Figure 1A signal timing diagram provided by the present disclosure;

[0038] Figure 2 A structural diagram of an on-chip termination signal generation circuit provided by the present disclosure;

[0039] Figure 3 Another signal timing diagram provided by the present disclosure;

[0040] Figure 4 A structural schematic diagram of an on-chip termination signal generation circuit provided by an embodiment of the present disclosure;

[0041] Figure 5 A structural schematic diagram of a second on-chip termination signal generation circuit provided by an embodiment of the present disclosure;

[0042] Figure 6 A structural schematic diagram of a third on-chip termination signal generation circuit provided by an embodiment of the present disclosure;

[0043] Figure 7 A structural schematic diagram of a fourth on-chip termination signal generation circuit provided by an embodiment of the present disclosure;

[0044] Figure 8 A structural schematic diagram of a fifth on-chip termination signal generation circuit provided by an embodiment of the present disclosure;

[0045] Figure 9 A structural schematic diagram of a sixth on-chip termination signal generation circuit provided by an embodiment of the present disclosure;

[0046] Figure 10 Another signal schematic diagram provided by an embodiment of the present disclosure.

[0047] Explanation of reference numerals:

[0048] 101: Generation circuit; 102: Delay circuit; 103: Output circuit;

[0049] 1011: First generation module; 1012: First acquisition module; 1013: First encoding module;

[0050] 1014: Second acquisition module; 1015: Comparison module; 1016: Second generation module; 1017: Second encoding module; 1018: Third generation module;

[0051] 1021: Sampling module; 1022: Third processing module;

[0052] 1031: First processing module; 1032: Data selector;

[0053] 1033: Second processing module; 1034: Switch module. Detailed Implementation Modes

[0054] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation modes described in the following exemplary embodiments do not represent all implementation modes consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure.

[0055] Currently, in order to ensure the accuracy of signal transmission and avoid the abnormal operation of the memory caused by signal reflection, termination resistors are usually set at the data (abbreviated as dq) terminals of the memory.

[0056] Figure 1 A signal timing diagram provided by the present disclosure. As Figure 1 shown Figure 1 Specifically, it is the timing diagram when the memory receives a write signal. In the related art, when the memory receives a write command, it is necessary to adjust the state of the termination resistor at the data terminal of the memory before the data to be written is received at the data terminal, that is, to adjust from RTT-PARK to RTT-WR. Among them, the time from receiving the write command to the termination resistor being adjusted to RTT-WR is represented by tODTLon_WR, where tODTLon_WR = CWL + ODTLon_WR_offset. In the above formula, CWL (CAS Write Latency) is the duration from when the write command is activated to when the first data is written. ODTLon_WR_offset can be understood as the turn-on offset, which is an adjustment value sent by the controller to indicate the switching time for adjusting from RTT-PARK to RTT-WR. And, when the above state switching occurs in RTT, a certain switching time is also required, which can generally be represented by tADC.

[0057] After the data writing is completed, it is necessary to switch RTT from the RTT-WR state back to the RTT-PARK state. In order to ensure the timing requirements for the above RTT state switching, it is necessary for the ODT signal generation circuit to generate an ODT_CMD signal (referred to as the on-chip termination signal in the present disclosure) and send the generated on-chip termination signal to the ODT control circuit, so that the ODT control circuit can complete the switching of the RTT resistance values before and after data writing, and the duration corresponding to the valid level period of ODT-CMD needs to be set with a certain offset based on the data writing duration. Among them, the offset can be characterized by ODT_offset as follows:

[0058] ODT_offset = ODTLoff_WR_offset - ODTLon_WR_offset

[0059] Among them, ODTLoff_WR_offset can be understood as the offset between the time when the data reception at the data end ends and the switching time when the RTT-WR state is switched back to RTT-PARK, that is, the turn-off offset mentioned in the present disclosure.

[0060] It should be noted that the number of data bits transmitted in one pulse is different under different BL modes. Under different BL modes, the duration corresponding to the active level period of the above ODT_CMD signal needs to be greater than or equal to the data transmission duration corresponding to the BL mode. In addition, the above turn-on offset and turn-off offset are set by the controller corresponding to the memory, and the values of the two need to meet the value range specified in the protocol. The following Table 1 shows the value range set for the DDR5 memory.

[0061]

[0062] Table 1. Specified Offset Value Range

[0063] In the above Table 1, P indicates that the value is valid, and X indicates that the value is invalid. For example, the controller can set the values of the turn-on offset and turn-off offset to -4 and 4 respectively, but it is not allowed to set them to 2 and -2.

[0064] Figure 2 It is a structural diagram of an on-chip termination signal generation circuit provided by the present disclosure. Figure 3 It is another signal timing diagram provided by the present disclosure. Specifically, the Figure 3 signal timing changes are used to illustrate the working principle of the on-chip termination signal generation circuit provided in Figure 2 . Figure 2 and Figure 3 The signals with the same name are the same signal. Such as Figure 2As shown, in the related art, the on-chip termination signal generation circuit includes three sequentially connected circuit modules (i.e., the first circuit module, the second circuit module, and the third circuit module in the figure). When the memory receives a write instruction, a signal for indicating the adjustment of the RTT state will be generated, which is characterized by CMD_IN in the figure; and CKT in the figure is used to characterize the external clock signal received by the memory, and CLK is used to characterize the internal clock signal of the memory. After the first circuit module receives CMD_IN, the first circuit module will generate a Burst_out signal based on the internal clock signal and transmit the Burst_out signal to the second circuit module connected to the first circuit module. Among them, the active level period of the Burst_out signal is the data write duration corresponding to the current burst length of the memory. For example, when the burst length Burst length is 8 and one clock cycle is 2tck, the active level period corresponding to the Burst_out signal generated by the first circuit module is 4tck; when the burst length is 16 and one clock cycle is 2tck, the active level period corresponding to the Burst_out signal generated by the first circuit module is 8tck.

[0065] After the second circuit module receives the Burst_out signal, it will delay the Burst_out signal according to the internal clock signal, the current data write duration, and the turn-on offset, and transmit the ODT_shift signal obtained by the delay processing to the third circuit module connected to the second circuit module. Furthermore, through the delay processing of the second circuit module above, the start time of the active level period of the finally generated ODT_out signal is adjusted, that is, the switching time when the RTT is adjusted from RTT-PARK to RTT-WR.

[0066] After the third circuit module receives the ODT_shift signal, it will further adjust the duration of the active level period of the ODT_shift signal, that is, increase ODT_offset on the basis of the active level period corresponding to the Burst_out signal, and then obtain the final ODT_out signal. It can be understood that the third circuit module is mainly used to adjust the end time of the active level period of the finally generated ODT signal, that is, to adjust the switching time when the RTT switches from RTT-WR to RTT-PARK.

[0067] However, the values of the turn-on offset and the turn-off offset in ODT_offset in the above circuit need to be selected with reference to the valid value range in Table 1.

[0068] Embodiments of the present disclosure provide an on-chip termination signal generation circuit and a memory system. When the on-chip termination signal generation circuit generates the final on-chip termination signal, a first signal with an active level period of a first duration is generated in the generation circuit 101. Moreover, in the subsequent output circuit 103, in order to ensure that the duration of the active level period of the finally generated on-chip termination signal is greater than or equal to the above data write duration, the output circuit 103 further generates an on-chip termination signal corresponding to the first burst length based on the indication signal generated by the generation circuit 101, so as to control the RTT state.

[0069] The following uses specific embodiments to elaborate in detail on the technical solutions of the present disclosure and how the technical solutions of the present disclosure solve the above technical problems. These several specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0070] Figure 4 FIG. is a schematic structural diagram of an on-chip termination signal generation circuit provided by an embodiment of the present disclosure. The on-chip termination signal generation circuit in this embodiment is used for a storage system, where the storage system includes a memory with an on-chip termination control circuit. As Figure 4 shown, the on-chip termination signal generation circuit in this embodiment includes: a generation circuit 101, a delay circuit 102, and an output circuit 103; wherein, the generation circuit 101 is configured to receive an initial signal CMD, and under the trigger of a clock signal, output a first signal (represented by Burst_out in the figure) and an indication signal; wherein, the initial signal is used to indicate the state of the termination resistor at the adjustment data terminal; the active level period of the first signal is a first duration; the first burst length is the current burst length of the memory, and the indication signal is used to indicate the first burst length; the delay circuit 102 is configured to receive the first signal and perform a delay process on the first signal Burst_out, and output a second signal (represented by latency_out in the figure); the output circuit 103 is configured to receive the indication signal and the second signal latency_out, output an on-chip termination signal (CMD_out); and send the on-chip termination signal to the on-chip termination control circuit, so that the on-chip termination control circuit adjusts the state of the termination resistor at the data terminal based on the on-chip termination signal.

[0071] Exemplarily, in this embodiment, a generation circuit 101, a delay circuit 102, and an output circuit 103 are provided in the on-chip termination circuit. Among them, the generation circuit 101, the delay circuit 102, and the output circuit 103 operate under the same clock signal. It should be noted that the clock signal CLK here is the internal clock signal of the memory.

[0072] When the storage system determines that it has received a write command signal that requires writing data into the memory, an initial signal CMD is generated inside the storage system and transmitted to the generation circuit 101, so as to inform the generation circuit 101 that it is necessary to adjust the state of the termination resistor at the data terminal of the memory. Triggered by the above initial signal CMD and the clock signal CLK, the generation circuit 101 will generate a first signal with an active level period of a first duration. It should be noted that the first duration here is a fixed value. That is, the value of the first duration has nothing to do with the burst length corresponding to the current memory.

[0073] In addition, in this embodiment, the generation circuit 101 also generates an indication signal and sends the indication signal to the output circuit 103 connected to the generation circuit 101, so that the output circuit 103 can determine the width of the active level of the final on-chip termination signal CMD_out according to the burst length indicated by the indication signal.

[0074] After the delay circuit 102 receives the first signal Burst_out, it will perform a delay process on the first signal Burst_out, so that the RTT state switching time can be determined according to the active edge of the second signal latency_out obtained by the delay later. For example, when the delay circuit 102 performs a delay process on the first signal Burst_out, the delay duration can be determined according to the write latency (WL for short) and ODTLon_WR_offset to determine the final delay duration, so as to ensure that before the data terminal of the memory receives the data to be written, the finally generated on-chip termination signal has controlled the RTT of the data terminal to complete the state switching. The specific working principle here can refer to the principle description in the related technology and will not be elaborated here. After the delay circuit 102 delays the first signal to generate the second signal, the generated second signal will be transmitted to the output circuit 103.

[0075] After the output circuit 103 receives the second signal latency_out, it will adjust the width of the active level of the second signal latency_out in combination with the first burst length indicated by the indication signal, so as to obtain an on-chip termination signal that conforms to the current first burst length.

[0076] In this embodiment, through the above on-chip termination circuit, after first generating a first signal with an active level period of a first duration, the first signal is delayed, and the width of the active level of the second signal obtained after the delay is adjusted based on the indication signal, so that finally the RTT state can be accurately and effectively switched based on the generated on-chip termination signal.

[0077] In a possible implementation, in a scenario where the first duration is less than the data write duration of the first burst length, in order to ensure that the effective level width of the on-chip termination signal finally output meets the requirements of the data write duration of the current first burst length, the output circuit 103 needs to perform a broadening process on the received second signal latency_out. In addition, the width of the effective level of the second signal latency_out in this embodiment is less than the data write duration of the first burst length, and the broadening amount for broadening the effective level of the second signal latency_out by the output circuit 103 can be the sum of a first value and ODT_offset. The first value is the difference between the width of the effective level of the second signal latency_out and the data write duration corresponding to the first burst length. Compared with Figure 2 in the solution where the finally generated effective level width is WL + ODT_offset, in this embodiment, the duration of the effective level period of the signal generated by the generation circuit 101 is reduced, and thus the broadening amount of the on-chip termination signal finally output by the output circuit 103 compared with the second signal latency_out changes from ODT_offset in the related art to the sum of ODT_offset and the first value in the present disclosure. Since the first value is a value greater than 0, furthermore, ODT_offset can be a value less than 0. Compared with Figure 2 the circuit shown in which only supports the pulse broadening process with ODT_offset greater than or equal to 0 in Table 1, the method in this embodiment increases the value range of ODT_offset, that is, the value range of ODT_offset can also include [-4tck, 0], and thus the value ranges of ODTLoff_WR_offset and ODTLon_WR_offset also increase, so that the ODT signal generation circuit can be adapted to various different values of the start offset and the end offset.

[0078] In some embodiments, the first duration is a fixed value of the data write duration corresponding to the second burst length; the second burst length is the minimum value among the burst lengths supported by the memory; or, the first duration is a fixed value less than the data write duration corresponding to the second burst length.

[0079] Exemplarily, in this embodiment, on the basis of the above embodiment, when the first duration is a fixed value less than the data write duration corresponding to the minimum burst length (i.e., the second burst length) supported by the memory, the effective level period of the first signal Burst_out output by the generation circuit 101 is less than the data write duration corresponding to its current first burst length.

[0080] Moreover, in this embodiment, the width of the active level period of the first signal output by the generation circuit 101 is a fixed value, that is, the duration of the active level period of the first signal Burst_out output in any burst length mode is the same, and the value of this fixed value is less than the data write duration corresponding to the second burst length. For example, assume that the burst lengths supported by the memory include 8 and 16, and the data write duration corresponding to a burst length of 8 is 4tck, and the data write duration corresponding to a burst length of 16 is 8tck. At this time, the above first duration can be 2tck, that is, regardless of whether the memory operates in a mode with a burst length of 8 or 16, the active level period of the first signal Burst_out output by the corresponding generation circuit 101 is 2tck.

[0081] It can be understood that in this embodiment, the active level periods of the first signals finally output by the generation circuit 101 in multiple burst length modes are the same, which can not only increase the value range of ODT_offset corresponding to the memory in multiple burst length modes, but also, since the generation circuit 101 only needs to output one type of first signal, further compared with Figure 2 the method in which the first circuit module in [reference] needs to adjust the active level period of the output Burst_out signal according to the current burst length of the memory, the circuit complexity of the generation circuit 101 can also be reduced.

[0082] Alternatively, the first duration can also be the data write duration corresponding to the second burst length. For example, assume that the burst lengths supported by the memory include 8 and 16, and the data write duration corresponding to a burst length of 8 is 4tck, and the data write duration corresponding to a burst length of 16 is 8tck, and the first duration is 4tck as an example for illustration. When the memory operates in a working mode with a burst length of 16, since the active level period of the Burst_out signal is 4tck, therefore, the effective level width of the final on-chip termination signal can be characterized as 4tck + 4tck + ODT_offset. Among them, for the two 4tck, one represents the original active level period of the Burst_out signal, and the other represents the difference between the active level period of the Burst_out signal and 8tck. Furthermore, the output circuit 103 can adjust the width of the active level of the received Burst_out signal based on 4tck + ODT_offset to enrich the value range of ODT_offset.

[0083] In some embodiments, the active level period of the first signal Burst_out generated by the generation circuit 101 is a fixed value less than or equal to the data write duration corresponding to the second burst length; the second burst length is the minimum value among the burst lengths supported by the memory. Figure 5Schematic diagram of the second in-chip termination signal generation circuit provided by the embodiments of the present disclosure. Based on the circuit structure shown in Figure 4 In the circuit structure shown, the generation circuit 101 provided in this embodiment includes a first generation module 1011, a first acquisition module 1012, and a first encoding module 1013. Among them, the first generation module 1011 is configured to generate a first signal in response to the received initial signal and clock signal; the first acquisition module 1012 is configured to determine a first burst length in the first register in response to the received initial signal, and output the first burst length; the first encoding module 1013 is configured to receive the first burst length, and output an indication signal according to the first burst length and a first correspondence; the first correspondence represents the correspondence between the burst length and the indication signal.

[0084] During specific operation, the first generation module 1011 is configured to receive the clock signal CLK and the initial signal CMD, and generate a first signal Burst_out with a fixed active level period, and transmit the first signal Burst_out to the delay circuit 102 connected to the first generation module 1011.

[0085] In addition, the first acquisition module 1012 is configured to obtain the first burst length corresponding to the current memory by accessing the register under the trigger of the initial signal CMD. In practical applications, the controller can send a CA signal to the memory to control the memory to enter the OTF mode. After the first acquisition module 1012 obtains the above CA signal, it can determine the first burst length corresponding to the memory according to the parameter value stored in the register.

[0086] After that, the first acquisition module 1012 sends the obtained first burst length to the first encoding module 1013, so that the first encoding module 1013 can determine the indication signal corresponding to the first burst length according to the received first burst length and the preset first correspondence. Specifically, the indication signal in this embodiment can be specifically used to indicate the width of the active level of the finally generated in-chip termination signal. Among them, the first correspondence is the correspondence between the burst length supported by the memory and the indication signal.

[0087] It can be understood that in this embodiment, the generation circuit 101 may include a first generation module 1011 that can be used to generate a first signal with a fixed active level period, and a first encoding module 1013 is also provided to generate a corresponding indication signal based on the obtained first burst length. Among them, the indication signal can specifically also indicate the width of the active level of the in-chip termination signal, so that the output circuit 103 can generate the in-chip termination signal based on the indication signal.

[0088] In some embodiments, in Figure 4Based on the embodiments shown, in this embodiment, if the first burst length is greater than the third burst length, the first duration is the data write duration corresponding to the third burst length; the third burst length is a value selected from the remaining values other than the maximum value among the burst lengths supported by the memory.

[0089] Exemplarily, in this embodiment, the third burst length is any burst length selected from the remaining values other than the maximum value among the burst lengths supported by the pre-specified memory. The generating circuit 101 is configured to generate a first signal Burst_out with a fixed effective level period when it is determined that the current first burst length of the memory is greater than the third burst length, and the fixed value here is the data write duration corresponding to the third burst length. That is to say, as long as the first burst length corresponding to the memory is greater than the third burst length, the effective level period of the first signal Burst_out generated by the generating circuit 101 is the above fixed value. And, since the first burst length is greater than the third burst length, the data write duration corresponding to the first burst length is greater than the data write duration corresponding to the third burst length. Compared with the method in the related art of directly using the data write duration corresponding to the first burst length as the effective level period of the generated signal, the generating circuit 101 provided in this embodiment has an effective level period of the generated first signal less than the data write duration corresponding to the first burst length when the first burst length is greater than the third burst length, and compared with Figure 1 the first circuit module in, the effective level period of the first signal generated by the generating circuit 101 provided in this embodiment is reduced. Furthermore, the subsequent output circuit 103 can perform pulse stretching processing on the received second signal latency_out according to the first value and the preset offset ODT_offset.

[0090] It can be understood that the on-chip termination signal generation circuit provided in this embodiment can ensure that when the memory operates in a mode with a burst length greater than the third burst length, the value range of the preset offset ODT_offset is widened, thereby increasing the function of the ODT signal generation circuit, so that the ODT signal generation circuit can be applied to more value ranges of ODT_offset.

[0091] Based on the above embodiments, Figure 6 is a schematic structural diagram of the third on-chip termination signal generation circuit provided by the embodiments of the present disclosure. In Figure 4Based on the circuit structure shown, the generation circuit 101 provided in this embodiment includes: a second acquisition module 1014, a comparison module 1015, a second generation module 1016, and a second encoding module 1017; the second acquisition module 1014 is configured to determine a first burst length in a first register in response to an initial signal received, and output the first burst length; the comparison module 1015 is configured to receive the first burst length, and output a comparison result according to the first burst length and a third burst length; the comparison result is used to represent the magnitude relationship between the first burst length and the third burst length; the second generation module 1016 is configured to output a first signal if it is determined that the comparison result represents that the first burst length is greater than the third burst length; the second encoding module 1017 is configured to receive the first burst length, and output an indication signal according to the first burst length and a second correspondence relationship; the second correspondence relationship represents the correspondence relationship between the burst length and the indication signal.

[0092] Exemplarily, in this embodiment, the technical principle of the second acquisition module 1014 in the generation circuit 101 is similar to that of the first acquisition module 1012 in the above embodiment, and will not be elaborated here. After the second acquisition module 1014 determines the first burst length, it will send the first burst length to the comparison module 1015. When the comparison module 1015 receives the above first burst length, it will compare the obtained first burst length with the third burst length, and output the obtained comparison result to the second generation module 1016. After the second generation module 1016 obtains the comparison result indicating that the first burst length is greater than the third burst length, it will directly generate a first signal with a data writing duration corresponding to the third burst length. When the second generation module 1016 receives the comparison result indicating that the first burst length is less than or equal to the third burst length, the second generation module 1016 does not work.

[0093] The second encoding module 1017 in this embodiment is connected to the second acquisition module 1014, and the working principle of the second encoding module 1017 is similar to that of the first encoding module 1013 in the above embodiment, and can determine the indication signal corresponding to the first burst length according to a preset second correspondence relationship. Among them, the indication signal can be used to represent the value of the first value.

[0094] In addition, in Figure 6 the shown generation circuit 101 further includes: a third generation module 1018, the third generation module 1018 is connected to the comparison module 1015, and the third generation module 1018 is configured to generate a third signal with an effective level width of a second value if it is determined that the comparison result represents that the first burst length is less than or equal to the third burst length, determine the third signal as the first signal, and output the first signal to the delay circuit 102; the second value is the data writing duration corresponding to the first burst length.

[0095] Specifically, the third generation module 1018 can be used to receive the comparison result output by the comparison module 1015. When the comparison result indicates that the first burst length is less than or equal to the third burst length, the third generation module 1018 will generate a third signal with the width of the effective level corresponding to the data write duration of the first burst length according to the first burst length of the current memory, and use the third signal as the first signal Burst_out finally output by the generation circuit 101 and transmit it to the delay circuit connected to the generation circuit 101. In addition, when the third generation module 1018 determines that the first burst length is greater than the third burst length, the third generation module 1018 does not work.

[0096] For example, assume that the burst lengths supported by the memory include 8 and 16, and the data write duration corresponding to a burst length of 8 is 4tck, and the data write duration corresponding to a burst length of 16 is 8tck. At this time, the third burst length can be 8. That is, when the memory operates in the mode with a burst length of 16, the first signal with a first duration of 4tck can be output according to the second generation module 1016 in the generation circuit 101. When the memory operates in the mode with a burst length of 8, the first signal with a first duration of 4tck can be output according to the third generation module 1018 in the generation circuit 101.

[0097] Alternatively, in the scenario where the burst lengths supported by the memory include 8 and 16, and the data write duration corresponding to a burst length of 8 is 4tck, and the data write duration corresponding to a burst length of 16 is 8tck, a module for generating a first duration with a fixed value (4tck) can be set in the corresponding generation circuit 101 to output the first signal.

[0098] It can be understood that the on-chip termination signal generation circuit provided in this embodiment can ensure that the memory operates in a mode with a burst length greater than the third burst length, increasing the value range of the preset offset ODT_offset. Equivalently, the value ranges of ODTLoff_WR_offset and ODTLon_WR_offset also increase, enabling the ODT signal generation circuit to be applied to more value ranges of ODT_offset. Moreover, it can also ensure that when the memory operates in a mode with a burst length less than or equal to the third burst length, the functions of the ODT signal generation circuit in the related art can still be retained.

[0099] It should be noted that, in some embodiments, the generation circuit 101 can also be controlled according to the following logic: for example, when the first burst length is within the first value range, a first signal with a first duration of a first value can be output, where the first value is greater than the data write duration corresponding to the burst length with the largest value within the first value range; when the first burst length is within the second value range, a second signal with a first duration of a second value can be output; the second value is greater than the data write duration corresponding to the burst length with the largest value within the second value range.

[0100] In some embodiments, based on Figure 4 the embodiment shown, Figure 7 This is a schematic structural diagram of the fourth on-chip termination signal generation circuit provided by the embodiments of the present disclosure. As Figure 7 shown, in the output circuit 103 of the on-chip termination signal generation circuit provided in this embodiment, there are multiple first processing modules 1031 and a data selector 1032; among them, the first processing module 1031 is used to receive the second signal and increase the width of the valid level of the second signal to obtain a first candidate signal; among them, the widths of the valid levels of the first candidate signals output by different first processing modules 1031 are different; the data selector 1032 is used to receive the indication signal output by the generation circuit 101 and the first candidate signal, and determine and output the on-chip termination signal according to the indication signal among multiple first candidate signals.

[0101] Exemplarily, in the on-chip termination signal generation circuit provided in this embodiment, the output circuit 103 can be composed of a data selector 1032 and multiple first processing modules 1031. Among them, each first processing module 1031 included in the output circuit 103 is used to receive the second signal latency_out output by the delay circuit 102, and generate a first candidate signal corresponding to each first processing module 1031 according to the received second signal latency_out. It should be noted that in this embodiment, the widths of the valid levels of the first candidate signals respectively output by different first processing modules 1031 under the action of the same second signal are different.

[0102] The data selector 1032 is also used to receive the indication signal output by the generation circuit 101, so that the data selector 1032 can determine the final on-chip termination signal CMD_out among multiple first candidate signals according to the received indication signal.

[0103] It can be understood that in this embodiment, by setting multiple first processing modules 1031 and a data selector 1032 in the output circuit 103, the on-chip termination signal that conforms to the current burst length can be selected from the first candidate signals respectively obtained by multiple first processing modules 1031.

[0104] In some embodiments, based on Figure 4 the embodiment shown, Figure 8 FIG. 5 is a schematic structural diagram of a fifth in-chip termination signal generation circuit provided by an embodiment of the present disclosure. The output circuit 103 includes: a plurality of second processing modules 1033, and a switch module 1034 corresponding to the second processing module 1033; the second processing module 1033 is configured to receive a second signal and increase the width of the active level of the second signal to obtain a second candidate signal; wherein, the widths of the active levels of the second candidate signals output by different second processing modules 1033 are different; the switch module 1034 is configured to receive an indication signal and control the conduction of the switch module 1034 in response to the indication signal, and determine that the second candidate signal generated by the second processing module 1033 connected to the switch module 1034 is the in-chip termination signal.

[0105] Exemplarily, in this embodiment, when setting the output circuit 103 in the in-chip termination signal generation circuit, a plurality of second processing modules 1033 and switch modules 1034 corresponding one-to-one to the second processing modules 1033 may be connected. Among them, the second processing module 1033 is similar to the first processing module 1031 in the above embodiment. The second processing module 1033 is connected to the delay circuit 102 and is configured to increase the width of the active level of the second signal latency_out output by the delay circuit 102, and then output a second candidate signal. In addition, it should be noted that when each second processing module 1033 adjusts the width of the active level, the increased widths are different. In addition, the switch module 1034 is respectively connected to the generation circuit 101 and the second processing module 1033 corresponding to the switch module 1034. The conduction and cutoff of the switch module 1034 are controlled by the indication signal output by the generation circuit 101. Under the control of the indication signal, one of the plurality of switch modules 1034 in the output circuit 103 will be conducted, and then, the second candidate module output by the second processing module 1033 connected thereto is used as the in-chip termination signal finally output by the output circuit 103.

[0106] It can be understood that in this embodiment, by setting a plurality of switch modules 1034 and combining the indication signal generated by the generation circuit 101, the conduction and cutoff of the switch module 1034 are controlled, so as to select an in-chip termination signal whose active level width conforms to the current burst length, ensure the timing accuracy of the finally output in-chip termination signal, improve the accuracy of the state switching of the termination resistance at the data end of the memory, and ensure that the memory can accurately receive the data to be written input externally.

[0107] In some embodiments, the delay duration between the active edge of the second signal and the active edge of the first signal is the difference between a third value and a first loss time; wherein, the third value is the sum of the write delay of the memory and the state transition duration of the termination resistor; the first loss time is the transmission time from the output end of the on-chip termination signal to the receiving end of the on-chip termination signal.

[0108] Exemplarily, when the delay circuit 102 performs delay processing on the received first signal, considering the time loss in the internal signal processing and transmission process of the memory system, since the delay duration of the delay circuit 102 affects the time for the termination resistor to adjust from RTT-PARK to RTT-WR, therefore, the influence of the loss is also considered when the delay circuit 102 performs delay processing. Specifically, in this embodiment, the time difference between the active edge of the finally output second signal latency_out of the delay circuit 102 and the active edge of the first signal Burst_out is the difference obtained by subtracting the first loss time from the above-mentioned third value. Among them, the first loss time can be understood as the transmission time from the output end of the on-chip termination signal to the receiving end of the on-chip termination signal. And, the third value can be understood as the sum of the write delay (WL) and the turn-on offset (ODTLon_offset) corresponding to the adjustment of the termination resistor from RTT-PARK to RTT-WR.

[0109] It can be understood that in this embodiment, by considering the transmission loss on the data transmission path, and then subtracting the time delay of the above-mentioned transmission loss during the delay processing of the delay circuit 102, the problem of inaccurate signal timing at the receiving end of the on-chip termination signal caused by the transmission path loss can be further avoided.

[0110] In some embodiments, based on the above embodiments, Figure 9 FIG. is a schematic structural diagram of a sixth on-chip termination signal generation circuit provided by an embodiment of the present disclosure. As Figure 9 shown, in Figure 4Based on the circuit structure shown, in this embodiment, the delay circuit 102 includes a sampling module 1021 and a third processing module 1022; the sampling module 1021 is connected to the third processing module 1022; the sampling module 1021 is configured to receive the first signal Burst_out and sample the first signal Burst_out in response to a clock signal; if it is determined that the level value of the sampled signal is a valid value, a shift signal Shift_align is output; the width of the active level period of the shift signal Shift_align is the same as the width of the active level period of the first signal; the third processing module 1022 is configured to perform a delay process on the received shift signal Shift_align according to a preset delay duration and output a second signal, where the preset delay duration is the difference between a third value and a second loss time; the second loss time is the difference between the time when the sampling module 1021 samples the valid value of the first signal and the time when the sampling module 1021 receives the first signal at the valid value.

[0111] Exemplarily, in this embodiment, the sampling module 1021 in the delay circuit 102 is configured to receive the first signal Burst_out sent by the generating circuit 101 and sample the level value of the first signal Burst_out at the active edge of the clock signal CLK. When it is determined that the level value of the first signal Burst_out is a valid level value, a shift signal is generated, and the width of the active level period of the shift signal is the same as the width of the active level period of the first signal. Then, the sampling module 1021 transmits the obtained shift signal to the third processing module 1022 so that the third processing module 1022 performs a delay process on the received shift signal. Moreover, the delay duration of the shift signal by the third processing module 1022 in this embodiment is the preset delay duration, and the preset delay duration is the difference between the third value and the second loss time. Among them, the second loss time can be understood as the time difference between the time when the sampling module 1021 receives the first signal with the level at the valid value and the time when the sampling module 1021 actually samples and determines that the first signal is at the level valid value.

[0112] It can be understood that since the delay unit cannot recognize the first signal at the valid value in time, when the delay unit performs the delay process, the second loss time in the above sampling and recognition process is also combined to determine the final preset delay duration, so as to effectively control the time for the termination resistor to adjust from RTT-PARK to RTT-WR, and further ensure that the state of the termination resistor can be switched before data writing and the data can be accurately written into the memory.

[0113] Figure 10Another signal schematic diagram provided by an embodiment of the present disclosure. In this embodiment, for the sake of illustration, the current burst length of the memory is 16, and when the burst length is 16, the corresponding data write duration is 8tck. Among them, the length of one clock cycle of the internal clock signal CLK is 2tck.

[0114] Among them, when the generation circuit 101 receives the initial signal CMD at a low level, the generation circuit 101 will generate a first signal Burst_out with a duration of 4tck during the active level period. When the delay circuit 102 receives the above first signal Burst_out, it will first generate a shift signal Shift_align with an active level width of 4tck at the active edge of the internal clock signal CLK, and perform a delay process on the shift signal Shift_align to obtain a second signal latency_out. Among them, the delay time between the second signal latency_out and the shift signal Shift_align can be characterized by the following formula:

[0115] T = WL - (1 + N) * 2tck + ODTLon_WR_offset

[0116] Among them, T represents the delay time, that is, the preset delay duration in the above embodiment. WL is the write delay. N can be used to represent the number of clock cycles consumed during the transmission process of the on-chip termination signal from the output circuit 103 to the on-chip termination signal receiving end. ODTLon_WR_offset is the turn-on offset. And the 1 in the above formula can be understood as the time delay consumed by the sampling module 1021 to sample the active level value of the first signal Burst_out, that is, the number of clock cycles corresponding to the time difference between the first active edge of the first signal and the first active edge of the shift signal.

[0117] The on-chip termination signal in the figure is obtained by the output circuit 103 based on the received second signal latency_out. It can be seen from the figure that compared with the second signal latency_out, the width of the active level of the on-chip termination signal differs by ODT_offset + 4tck. Among them, the 4tck here can be understood as the difference between the data write duration 8tck corresponding to the burst length of 16 and the width of the active level period of the first signal (that is, the first value in the present disclosure).

[0118] The actual signal ODT_DQ pin in the figure is the signal actually received by the receiving end of the on-chip termination signal CMD_out. As can be seen from the figure, there is a time delay of N*2tck between the first valid edge of the on-chip termination signal CMD_out and the first valid edge of the actual signal ODT_DQ pin, and the difference between the time of the first valid edge of the actual signal ODT_DQ pin (i.e., the time when the termination resistor is adjusted from RTT-PARK to RTT-WR) and the generation time of the initial signal CMD is WL+ODTLon_WR_offset. The difference between the end time of the valid level of the on-chip termination signal CMD_out (i.e., the time when the termination resistor is adjusted from RTT-WR to RTT-PARK) and the generation time of the initial signal CMD is WL+BL / 2+ODTLoff_WR_offset to ensure the accuracy of the timing of the termination resistor state switching. And, based on the embodiments of the present disclosure, when setting ODT_offset, it is also possible to support value settings within the range of [-4tck,0]. Compared with the related art where ODT_offset can only select values greater than or equal to 0, the value range of [-4tck,0] is further added to the value range in the related art, which is equivalent to increasing the value ranges of ODTLon_WR_offset and ODTLoff_WR_offset. Specifically, the respective value ranges of the two can refer to the value settings in Table 2.

[0119] As shown in Table 2, in the embodiments of the present disclosure, compared with the offset value ranges supported in the BL16 mode provided in Table 1, in the BL16 mode of the embodiments of the present disclosure, the value ranges marked as "X" in Table 1 can also be effectively supported, which is beneficial to broadening the usage range of the offset.

[0120]

[0121] Table 2. Offset value ranges supported by the embodiments of the present disclosure

[0122] The embodiments of the present disclosure also provide a storage system, which includes a memory having an on-chip termination control circuit and an on-chip termination signal generation circuit according to any of the above embodiments.

[0123] The terms "first", "second", "third", "fourth", etc. (if any) in the description, claims and above-mentioned drawings of the present disclosure are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that comprises a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0124] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The description and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

[0125] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

Claims

1. An on-chip termination signal generation circuit is applied to a storage system, and the storage system includes a memory with an on-chip termination control circuit. Characterized in that, The on-chip termination signal generation circuit includes: a generation circuit, a delay circuit, and an output circuit; wherein, The generation circuit is configured to receive an initial signal, and in response to a clock signal, output a first signal and an indication signal; wherein, the initial signal is used to indicate the state of the termination resistor of the adjustment data terminal; the indication signal is used to indicate a first burst length; the first burst length is the current burst length of the memory; the active level period of the first signal is a first duration; The delay circuit is configured to receive the first signal and perform a delay process on the first signal to output a second signal; The output circuit is configured to receive the indication signal and the second signal and output an on-chip termination signal, and the on-chip termination control circuit receives the on-chip termination signal to adjust the state of the termination resistor of the data terminal; wherein, the width of the active level of the on-chip termination signal is selected and generated according to the indication signal.

2. The on-chip termination signal generation circuit according to claim 1, Characterized in that, The first duration is a fixed value of the data write duration corresponding to a second burst length; the second burst length is the minimum value among the burst lengths supported by the memory; Or, the first duration is a fixed value less than the data write duration corresponding to the second burst length.

3. The on-chip termination signal generation circuit according to claim 2, Characterized in that, The generation circuit includes: a first generation module, a first acquisition module, and a first encoding module; the encoding module is connected to the first acquisition module; The first generation module is configured to generate a first signal in response to the received initial signal and clock signal; The first acquisition module is configured to determine the first burst length in a first register in response to the received initial signal and output the first burst length; The first encoding module is configured to receive the first burst length and output an indication signal according to the first burst length and a first correspondence relationship; the first correspondence relationship represents the correspondence relationship between the burst length and the indication signal.

4. The on-chip termination signal generation circuit according to claim 1, Characterized in that, If the first burst length is greater than a third burst length, the first duration is the data write duration corresponding to the third burst length; the third burst length is a value selected from the remaining values other than the maximum value among the burst lengths supported by the memory.

5. The on-chip termination signal generation circuit according to claim 4, Characterized in that, The generation circuit includes: a second acquisition module, a comparison module, a second generation module, and a second encoding module; The second acquisition module is configured to determine the first burst length in a first register in response to the received initial signal and output the first burst length; The comparison module is configured to receive the first burst length, and output a comparison result according to the first burst length and the third burst length; the comparison result is used to characterize the magnitude relationship between the first burst length and the third burst length; The second generation module is configured to output a first signal if it is determined that the comparison result indicates that the first burst length is greater than the third burst length; The second encoding module is configured to receive the first burst length, and output an indication signal according to the first burst length and a second correspondence relationship; the second correspondence relationship characterizes the correspondence relationship between the burst length and the indication signal.

6. The on-chip termination signal generation circuit according to claim 5, wherein, The generation circuit further includes: A third generation module, connected to the comparison module, the third generation module is configured to generate a third signal with an active level width of a second value if it is determined that the comparison result indicates that the first burst length is less than or equal to the third burst length, determine the third signal as the first signal, and output the first signal to the delay circuit; the second value is the data writing duration corresponding to the first burst length.

7. The on-chip termination signal generation circuit according to claim 1, wherein, The output circuit includes a data selector and a plurality of first processing modules; wherein, The first processing module is configured to receive the second signal and increase the width of the active level of the second signal to obtain a first candidate signal; wherein, the widths of the active levels of the first candidate signals output by different first processing modules are different; The data selector is configured to receive the indication signal output by the generation circuit and the first candidate signals, and determine and output the on-chip termination signal from among the plurality of first candidate signals according to the indication signal.

8. The on-chip termination signal generation circuit according to claim 1, wherein, The output circuit includes: a plurality of second processing modules, and switch modules corresponding to the second processing modules; The second processing module is configured to receive the second signal and increase the width of the active level of the second signal to obtain a second candidate signal; wherein, the widths of the active levels of the second candidate signals output by different second processing modules are different; The switch module is configured to receive the indication signal, and in response to the indication signal, control the switch module to conduct, determine the second candidate signal generated by the second processing module connected to the switch module as the on-chip termination signal, and output the on-chip termination signal.

9. The on-chip termination signal generation circuit according to any one of claims 1-8, wherein, The delay duration between the active edge of the second signal and the active edge of the first signal is the difference between a third value and a first loss time; wherein, the third value is the sum of the write delay of the memory and the state switching duration of the termination resistor; the first loss time is the transmission time from the output end of the on-chip termination signal to the receiving end of the on-chip termination signal.

10. The on-chip termination signal generation circuit according to claim 9, It is characterized in that the delay circuit includes a sampling module and a third processing module; the sampling module is connected to the third processing module; the sampling module is configured to receive the first signal and sample the first signal in response to the clock signal; if it is determined that the level value of the sampled signal is a valid value, a shift signal is output; the width of the active level period of the shift signal is the same as the width of the active level period of the first signal; the third processing module is configured to perform a delay process on the received shift signal according to a preset delay duration and output a second signal, where the preset delay duration is the difference between the third value and the second loss time; the second loss time is the difference between the time when the sampling module samples the valid value of the first signal and the time when the sampling module receives the first signal at the valid value.

11. A storage system It is characterized in that the storage system includes a memory having an on-chip termination control circuit and an on-chip termination signal generation circuit according to any one of claims 1-10.

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