Read-write circuit based on spin-orbit moment magnetic random access memory

Abstract

The invention discloses a read accompanying and writing circuit based on a spin-orbit moment magnetic random access memory, which belongs to the field of integrated circuits and comprises a read accompanying and writing circuit for generating a voltage difference after a capacitor is pre-charged, a read amplifying circuit for differentially amplifying the voltage difference of the capacitor and a latch circuit for latching and outputting data. The circuit has double working modes: a normal data read-write mode and a read-write working mode. And for a data read-write mode, data reading can be realized under low voltage and high frequency. For a read-write mode, one-time read operation can be simultaneously carried out in one write operation period in any storage unit in the storage array, namely read-write is carried out. For the challenge that a current large model urgently needs a high-bandwidth memory, the provided read-write scheme can serve as a basic unit of a dual-port memory, and compared with a traditional dual-port memory, the bandwidth can be improved by 100%.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a read-with-write circuit based on a spin-orbit torque magnetic random access memory. Background Art

[0002] Since this century, the fields of computers and artificial intelligence have developed vigorously, bringing a large demand for data operation and storage, and the requirements for the reliability and performance of non-volatile memories have been continuously improved. Against this background, the Spin-orbit-torque magnetic random access memory (SOT-MRAM) has emerged as the times require. At the same time, with the wide application of large-scale deep learning models, the demand for high-bandwidth memories has increased rapidly. High-bandwidth memories provide high data throughput through wide data buses, significantly improving the computing power of the system. However, in the face of the growing computing demand, there are still problems such as mutual conflicts between read and write operations. This is because in traditional memory designs, read and write operations are usually separated and cannot be performed simultaneously, thus limiting the further improvement of the data transfer bandwidth.

[0003] As a new generation of non-volatile memory, SOT-MRAM has the advantage of high-speed reading and writing. Generally, read and write operations can reach the nanosecond level, and even the sub-nanosecond level. This high speed makes SOT-MRAM particularly outstanding in application scenarios that require high-speed data processing and high-frequency operations. More importantly, the read and write paths of SOT-MRAM are separated. This characteristic indicates that it can optimize read and write operations separately without interfering with each other. Compared with the Spin-transfer-torque magnetic random access memory (STT-MRAM), SOT-MRAM avoids the read interference problem and realizes true read-write independence. This not only improves the efficiency of the memory but also reduces the conflicts between read and write operations, thus meeting higher performance requirements.

[0004] In recent years, researchers have performed read and write operations on different memory cells in different banks based on dual-port memories, further improving the memory access bandwidth. Compared with STT-MRAM, as a dual-port memory, SOT-MRAM has the potential to have a higher memory access bandwidth and can more flexibly support parallel operations to meet higher performance requirements. However, especially in the fields of high-performance computing (HPC), real-time data processing, artificial intelligence, and machine learning, it still cannot meet the requirements of high-bandwidth memories in the information age. Summary of the Invention

[0005] The present invention provides a read - accompanied - write circuit based on a spin - orbit - torque magnetic random access memory, so as to solve the technical problem that traditional memories perform data writing and information reading separately, resulting in the memory being able to perform only a single operation at the same time, restricting the read - write efficiency of the memory and limiting the further improvement of the bandwidth of high - bandwidth memories.

[0006] An embodiment of the present invention provides a read - accompanied - write circuit based on a spin - orbit - torque magnetic random access memory, including: a read - accompanied - write circuit that generates a voltage difference after pre - charging a capacitor, a read amplifier circuit for differentially amplifying the voltage difference of the capacitor, and a latch circuit for latching and outputting data; the read - accompanied - write circuit that generates a voltage difference after pre - charging a capacitor includes a storage unit and a reference unit.

[0007] The working modes of the read - accompanied - write circuit based on the spin - orbit - torque magnetic random access memory include a normal data read - write mode and a read - accompanied - write mode.

[0008] In the read - accompanied - write mode, the read - accompanied - write circuit uses the voltage division of the write voltage to charge two capacitors connected to the storage unit and the reference unit respectively. Due to the resistance difference between the storage unit and the reference unit, a voltage difference is generated on the two capacitors. Then, the voltage difference is amplified by a differential amplifier circuit, and finally, the data is latched by the latch circuit, realizing that during the write operation, a read operation is simultaneously performed, that is, read - accompanied - write.

[0009] In the normal data read - out mode, a read voltage is applied to the storage unit and the reference unit through a gated transistor, and the operations of capacitor charging, voltage - difference amplification, and latching are also performed to realize high - speed and low - power consumption data read - out.

[0010] In the normal data write mode, data is written by applying a write voltage to the storage unit.

[0011] Optionally, in an embodiment of the present invention, the storage unit is composed of a spin - orbit - torque magnetic tunnel junction and two NMOS transistors respectively serving as a read transistor and a write transistor, which is called a 2T - 1SOT storage unit.

[0012] The spin - orbit - torque magnetic tunnel junction is composed of a magnetic tunnel junction and an orbit layer. The magnetic tunnel junction is composed of a fixed layer, a free layer, and an oxide isolation layer made of magnetic media. The resistance state of the magnetic tunnel junction is determined by the relative magnetization directions of the fixed layer and the free layer.

[0013] The orbit layer is composed of heavy metals. The orbit layer generates a combined magnetic field by applying a write current, and changes the magnetization direction of the free layer in the absence of an external magnetic field, thereby changing the resistance of the magnetic tunnel junction; the direction of the write current determines the written data.

[0014] The memory access operation of the storage unit is controlled by a bit line BL, a source line SL, a read line RL, a write word line WWL, and a read word line RWL.

[0015] Optionally, in an embodiment of the present invention, the reference unit is composed of three resistors and two NMOS transistors; one of the resistors has a resistance value of the reference resistor Rref, and the resistance values of the other two resistors are both half of the track layer resistance, i.e., Rsot / 2; the two NMOS transistors serve as the reference read transistor and the reference write transistor respectively;

[0016] The operation of the reference unit is controlled by the reference bit line BLref, the reference source line SLref, the reference read line RLref, the write word line WWL, and the read word line RWL.

[0017] Optionally, in an embodiment of the present invention, the read-with-write circuit is composed of a 2T-1SOT memory cell, a reference unit, two capacitors, and two NMOS discharge transistors; according to different resistance states of the magnetic tunnel junction, corresponding charging voltage differences are generated on the two capacitors; the NMOS transistors are used to discharge the capacitors after the operation ends;

[0018] The read amplifier circuit is connected by four NMOS transistors and three PMOS transistors, and is used to preliminarily differentially amplify the charging voltage differences of the capacitors of the memory cell and the reference unit;

[0019] The latch circuit includes three PMOS transistors, three NMOS transistors, two transmission gates, and an inverter, and is used to expand the differentially amplified voltage difference to a full swing and latch the data.

[0020] Optionally, in an embodiment of the present invention, at the sub-memory array level, in the normal data readout mode, a memory cell and the reference unit in the same row are simultaneously activated by the same corresponding read word line; read voltages are applied to the corresponding source line and the reference source line, and the read voltages charge the corresponding capacitors of the memory cell and the reference unit respectively through the read path. Due to the resistance difference on the read path, voltage differences are generated on the two capacitors, and then through differential amplification and latching operations, the data stored in the memory cell is read out;

[0021] In the normal data write mode, only one memory cell is activated by the corresponding write word line; the write drive circuit applies write voltages to the corresponding source line and bit line, and the write voltages form a write current on the write transistor and the track layer, so that the magnetic moment of the free layer points to the specified direction, thereby writing data into the memory cell;

[0022] In the read - while - write mode, a storage cell and a reference cell in the same row are simultaneously activated by the same corresponding read word line and the same corresponding write word line; the write driving circuit and the reference write driving circuit respectively apply the same write voltage to the corresponding source line, bit line, corresponding reference source line, and reference bit line to write data into the storage cell. The voltage division of the write voltage between the center of the track layer and the reference resistors of two Rsot / 2 is equal. The voltage division charges the corresponding capacitors of the storage cell and the reference cell respectively through the read path. Due to the resistance difference between the magnetic tunnel junction and the reference resistor, a voltage difference is generated on the two capacitors, and then through differential amplification and latching, the function of simultaneously reading the data stored in the storage cell before the write operation is realized during the write operation.

[0023] Optionally, in an embodiment of the present invention, the sub - storage array is composed of storage cells in X rows and Y columns and reference cells in X rows and one column;

[0024] All the storage cells in each row share the reference cell in the same row;

[0025] All the storage cells in each storage array share one write driving circuit, and all the reference cells in each storage array share one reference write driving circuit;

[0026] In the normal data writing mode, the write driving circuit is enabled to provide a write voltage to the storage cell;

[0027] In the read - while - write mode, the write driving circuit and the reference write driving circuit are simultaneously enabled to respectively provide the same write voltage to the storage cell and the reference cell.

[0028] Optionally, in an embodiment of the present invention, all the storage cells and reference cells in each sub - storage array share a group of charging capacitors and discharge tubes, and the transmission gate controls whether the read line of a storage cell at a specific address is connected to the capacitor.

[0029] Optionally, in an embodiment of the present invention, the storage cells in each column of the sub - storage array share one PMOS gated tube, and the read voltage source is connected to the source lines of each column of storage cells through the gated tube to provide a read voltage to the source lines only in the normal data readout mode.

[0030] The read - while - write circuit of the spin - orbit - torque magnetic random access memory according to the embodiment of the present invention has the following effects:

[0031] (1) The read - while - write circuit of the spin - orbit - torque magnetic random access memory studied in the present invention has the advantage of high bandwidth. For traditional memories, read and write operations need to be carried out alternately, which will lead to data transmission delay and bandwidth waste. While the read - while - write memory allows read and write operations to be carried out simultaneously, which reduces the waiting time between read and write operations and avoids conflicts between read and write operations, greatly improving data transmission efficiency and providing higher data throughput.

[0032] (2) The read-with-write circuit based on the spin-orbit torque magnetic random access memory studied in the present invention can be used as a basic unit of a dual-port memory. In the read-with-write operation mode, compared with the traditional dual-port memory that can only perform simultaneous read and write operations on storage units at different addresses, the read-with-write scheme proposed by the present invention can achieve simultaneous read and write within the same storage unit, which can increase the bandwidth by 100%, reduce the access latency, and improve the response speed of the memory.

[0033] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the following description of the embodiments in conjunction with the drawings, in which:

[0035] Figure 1 FIG. is a schematic structural diagram of a read-with-write circuit based on a spin-orbit torque magnetic random access memory according to an embodiment of the present invention;

[0036] Figure 2 FIG. is a schematic diagram of the working principles of the read-with-write memory and the separate read and write memory of the present invention;

[0037] Figure 3 FIG. (a) is a schematic structural diagram of a 2T-1SOT storage unit of the present invention;

[0038] Figure 3 FIG. (b) is a schematic diagram of the parallel and anti-parallel states of the track layer and the magnetic tunnel junction of the present invention;

[0039] Figure 4 FIG. is a timing waveform diagram for reading "1" and "0" in the normal data read and write mode of the present invention;

[0040] Figure 5 FIG. is a timing waveform diagram for reading "1" and "0" in the read-with-write mode of the present invention;

[0041] Figure 6 FIG. is a schematic diagram of the principle at the read-with-write array level proposed by the present invention;

[0042] Figure 7 FIG. is a comparison diagram of the read power consumption between the present invention in the separate data readout mode and a general memory using a sense amplifier (SA) to read data;

[0043] Figure 8 FIG. (a) is a power consumption-time diagram of the simultaneous read and write operation in the read-with-write mode of the present invention and the alternating read and write operation of a general memory;

[0044] Figure 8 Figure (b) is a schematic diagram of the number of read and write operations completed by the simultaneous read and write operation and the separate read and write operation in the read-with-write mode of the present invention. Detailed implementation manners

[0045] Embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described by referring to the accompanying drawings are exemplary and are intended to explain the present invention, and should not be construed as a limitation to the present invention.

[0046] Figure 1 It is a schematic diagram of a read-with-write circuit structure based on a spin-orbit torque magnetic random access memory according to an embodiment of the present invention.

[0047] As Figure 1 shown, the read-with-write circuit based on the spin-orbit torque magnetic random access memory includes a read-with-write circuit that generates a voltage difference after pre-charging a capacitor, a read amplifier circuit for differentially amplifying the voltage difference of the capacitor, and a latch circuit for latching and outputting data.

[0048] The read amplifier circuit can amplify the voltage difference between the capacitor of the storage unit and the capacitor of the reference unit. The latch circuit further amplifies the amplified voltage difference of the capacitor to a full swing and latches the data. The read-with-write circuit and the logic circuit for controlling the working mode work together to distinguish the gate voltage configurations of the read transistor and the write transistor in the read-with-write circuit under different working modes.

[0049] Traditional memories can only perform read and write operations separately, and the read and write operations need to be alternated, which will cause delays in data transmission and waste of bandwidth, restricting the further improvement of the memory bandwidth. The working principle of the read-with-write circuit proposed by the present invention is as Figure 2 shown. The read operation can be performed simultaneously through the voltage division of the write operation, realizing simultaneous read and write in the same storage unit, which can effectively improve the data transmission efficiency and further improve the bandwidth of the memory.

[0050] In the embodiments of the present invention, the read-with-write circuit that generates a voltage difference after pre-charging a capacitor includes a storage unit and a reference unit. The read amplifier circuit and the charging circuit are connected by the read line RLmtj of the storage unit and the reference read line RLref of the reference unit. The read amplifier circuit and the latch circuit are connected by leads SAmtj and SAref. The position of each connecting lead is as Figure 1 shown.

[0051] In one embodiment of the present invention, the storage unit is composed of a spin-orbit torque magnetic tunnel junction (SOT-MTJ) and two NMOS transistors serving as a read transistor and a write transistor respectively, which is called a 2T-1SOT storage unit. The read transistor and the write transistor jointly control the working mode (separate read / separate write / read with write), and its specific structure is as shown in Figure 3 Figure (a).

[0052] As a new generation of non-volatile memory, the working unit of SOT-MRAM is a magnetic tunnel junction (MTJ) and an orbit layer tightly connected thereto. The orbit layer is composed of heavy metal media, as shown in Figure 3 Figure (b). The magnetic tunnel junction is composed of a magnetic fixed layer and a free layer, as well as a non-magnetic oxide isolation layer; the fixed reference layer is thicker and its magnetic moment direction will not change; the free layer is thinner and its magnetic moment direction is the same as or opposite to that of the fixed layer, which can be used to represent binary information 0 and 1. The relative magnetization direction of the fixed layer and the free layer determines the resistance state of the magnetic tunnel junction. Due to the giant magnetoresistance effect, when the magnetic moment directions of the free layer and the fixed reference layer are the same, the resistance of the MTJ is smaller, while when they are opposite, the resistance of the MTJ is larger. The two states of the magnetic tunnel junction in the storage unit are anti-parallel AP and parallel P respectively; when the direction of the free layer of the magnetic tunnel junction is parallel to the fixed layer, the magnetic resistance of the magnetic tunnel junction is low at RP, representing logic "0"; when the magnetization direction of the free layer is anti-parallel to the fixed layer, the magnetic resistance is high at RAP, representing logic "1". Due to the giant magnetoresistance effect, when the magnetic moment directions of the free layer and the fixed reference layer are the same, the resistance of the MTJ is smaller, while when they are opposite, the resistance of the MTJ is larger

[0053] The orbit layer is composed of heavy metals and is tightly connected to the fixed layer of the magnetic tunnel junction. By adjusting the angle between the easy magnetization axis of the magnetic tunnel junction and the current channel of the orbit layer, and applying currents in different directions at both ends of the orbit layer, the resultant magnetic field generated can change the magnetic moment of the free layer without an external magnetic field, thereby realizing data writing. The direction of the current determines the written binary data. Thus, the orbit layer can change the magnetization direction of the free layer without an external magnetic field by applying a large enough write current to generate a resultant magnetic field, thereby changing the resistance value of the magnetic tunnel junction. The direction of the write current determines the written data.

[0054] The memory access operation of the storage unit is controlled by a bit line BL, a source line SL, a read line RL, a write word line WWL, and a read word line RWL. One end of the write transistor is connected to the orbit layer, and the other end is connected to the bit line; the source line is connected to the other end of the orbit layer; one end of the read transistor is connected to the magnetic tunnel junction, and the other end is connected to the read line; the write word line and the read word line are respectively connected to the gates of the write transistor and the read transistor. The storage unit is used for normal data read / write mode and read with write mode.

[0055] In one embodiment of the present invention, the reference unit is composed of three resistors and two NMOS transistors; one of the resistors has a resistance value of the reference resistor Rref, and the other two resistors have the same resistance value, which is half of the track layer resistance, i.e., Rsot / 2; the two NMOS transistors are used as the reference read transistor and the reference write transistor respectively, and the operation of the reference unit is controlled by the reference bit line BLref, the reference source line SLref, the reference read line RLref, the write word line WWL, and the read word line RWL.

[0056] One ends of the three reference resistors are connected together. One end of the reference write transistor is connected to a reference resistor with a resistance value of Rsot / 2, and the other end is connected to the reference bit line; the reference source line is connected to the other end of a reference resistor with a resistance value of Rsot / 2; one end of the reference read transistor is connected to the reference resistor with a resistance value of Rref, and the other end is connected to the reference read line; the reference write word line and the reference read word line are connected to the gates of the reference write transistor and the reference read transistor respectively. The reference unit is used for the normal data readout mode and the read-with-write mode.

[0057] In one embodiment of the present invention, the read-with-write circuit is composed of a 2T-1SOT memory cell, a reference unit, two capacitors, and two NMOS discharge transistors; according to different resistance states of the magnetic tunnel junction, corresponding charging voltage differences are generated on the two capacitors; the NMOS transistors are used to discharge the capacitors after the operation is completed.

[0058] Specifically, as Figure 1 shown, the read line RLmtj and the reference read line RLref are respectively connected to the capacitors Cmtj, Cref and the transistors M5, M6, and the other ends of the capacitors are grounded. During the read-with-write operation, the capacitors are charged, and due to different branch resistances, a charging voltage difference is formed. The two discharge NMOS transistors M5 and M6 are respectively connected to RLmtj and RLref, and are used to discharge the capacitors after the operation is completed, and are enabled when the read operation is not selected, so that the capacitor voltages are discharged to GND. According to different resistance states of the magnetic tunnel junction, corresponding charging voltage differences are generated on the two capacitors.

[0059] Since the magnetoresistance of the magnetic tunnel junction is different from the reference resistor Rref, even if the same charging voltage is given, the charging speeds of the capacitors on the read line RLmtj and the reference read line RLref will be different. Therefore, the voltage difference between the read line RLmtj and RLref can be amplified by using a read amplifier circuit.

[0060] In one embodiment of the present invention, the read amplifier circuit is composed of four NMOS transistors and three PMOS transistors connected together, and is used to preliminarily differentially amplify the charging voltage difference between the capacitor of the memory cell and the capacitor of the reference unit.

[0061] Specifically, the voltages of the read line RLmtj and the reference read line RLref are connected to the gate nodes of transistors M11 and M12. Transistor M13 is a gated transistor that is only enabled during amplification to reduce power consumption overhead. The gates of transistors M9 and M10 are cross-connected to form positive feedback to initially amplify the charging voltage difference between the storage unit capacitor and the reference unit capacitor. Transistors M7 and M8 are connected in diode configuration between the gate and the drain to form negative feedback to avoid excessive amplification. The entire amplifier is of differential structure, suppressing common-mode interference and having strong stability.

[0062] In an embodiment of the present invention, the latch circuit includes three PMOS transistors, three NMOS transistors, two transmission gates, and an inverter, and is used to expand the differentially amplified voltage difference to a full swing and latch data.

[0063] Specifically, the output signal of the sense amplifier circuit is connected to the input signal of the latch circuit; when latch enabling, the transmission gates are turned off to isolate the input signal of the latch circuit from the output signal of the sense amplifier circuit to avoid mutual interference. Among them, M14 and M15 are used as gated transistors that are only enabled during latching to reduce power consumption overhead. The input signal leads SAmtj and SAref are respectively connected to the two transmission gates, and the other ends of the transmission gates are respectively the output signal leads OUT and OUTB, serving as the input terminals of two cross-coupled inverters. This latch circuit is used to expand the differentially amplified voltage difference to a full swing and latch data.

[0064] In an embodiment of the present invention, the read-with-write operation mode of the spin-orbit torque magnetic random access memory includes a normal data read / write mode and a read-with-write mode, and both of these operation modes are realized by the joint operation of the sense amplifier circuit, the latch circuit, and the read-with-write circuit.

[0065] Furthermore, in the normal data readout mode, a read voltage is applied to the storage unit and the reference unit through a gated transistor, and the operations of capacitor charging, voltage difference amplification, and latching are also performed to achieve high-speed and low-power data readout.

[0066] When performing normal data readout, a storage unit and a reference unit in the same row are simultaneously activated by the same corresponding read word line; a read voltage is applied on the corresponding source line and the reference source line, and the read voltage charges the corresponding capacitors of the storage unit and the reference unit respectively through the read path. Due to the resistance difference on the read path, a voltage difference is generated between the two capacitors, and then through differential amplification and latching operations, the data stored in this storage unit is read out to achieve data readout. The readout stage is divided into: a charging stage, an amplification stage, and a latching stage. The specific operation of the normal data readout mode is as follows:

[0067] During charging, the read word line (RWL) is at a high level, the read transistors M1 and M3 are turned on, and read voltages of the same magnitude are applied to SL and SLref. These read voltages charge the capacitors Cmtj and Cref through the read transistors M1 and M3 respectively. By adjusting the capacitance values and the charging time, the voltage difference between the read lines RLmtj and RLref is made large enough at the end of the charging time. At this time, the read word line RWL drops to a low level, the read transistors M1 and M3 turn off, and there is no closed loop for the charge and discharge of the capacitors. Therefore, the capacitor voltages remain stable subsequently, and the charging period ends, and the amplification stage starts. Only the charging current of the capacitors exists during the charging stage, and the power consumption is low.

[0068] The operation of the amplifier circuit is as follows: During the non-enabled period, the AMP signal is at a low level, the pull-up transistor M13 is not turned on, and there is no closed loop. When the amplifier circuit starts to operate, the AMP is active at a high level, and the voltages on the read line RLmtj and the reference read line RLref are used as the inputs of the amplifier circuit for differential amplification to amplify the voltage difference between these two input voltages. By adjusting the sizes and threshold voltages of the transistors in the amplifier circuit, an appropriate common-mode input voltage and amplification factor are set, and the amplified voltage is the voltage on the leads SAmtj and SAref.

[0069] The operation of the latching stage is as follows: When the latch signal LAT is not enabled, the transmission gate is turned on, SAref and SAmtj are connected to OUT and OUTB respectively, and the gated transistors M14 and M15 are cut off; when the latch signal LAT is active at a high level, the gated transistors M14 and M15 are turned on, and the transmission gate is turned off. At this time, the voltages on the leads OUT and OUTB are the voltage values of SAref and SAmtj before LAT is enabled. Then, the positive feedback is used to adjust SAmtj and SAref to the high and low levels of the full swing, and the output of the latch circuit is the read result.

[0070] In the normal data writing mode, data can be written by applying an appropriate write voltage to the memory cell.

[0071] During normal data writing, only one memory cell is activated by the corresponding write word line; the write driver circuit applies a write voltage large enough and with a long enough pulse width to the corresponding source line and bit line. The write voltage forms a write current on the write transistor and the track layer, making the magnetic moment of the free layer point in the specified direction, thereby writing data into the memory cell. Only the data at one address is written. The specific operation of the write operation is as follows: The enabled write word line WWL is active at a high level, the read word line RWL is not enabled, and the write driver circuit applies high and low voltages to the bit line BL and the source line SL to form currents in different directions. A large enough current (greater than the switching current of the spin-orbit torque MTJ) and a long enough write pulse width can flip the magnetic moment of the free layer, and thus data can be written.

[0072] Further, in the read - while - write mode, the read - while - write circuit uses the voltage division of the write voltage to charge two capacitors connected to the storage unit and the reference unit respectively. Due to the resistance difference between the storage unit and the reference unit, a voltage difference will be generated on the two capacitors. Then, the voltage difference is amplified by a differential amplifier circuit, and finally, the data is latched by a latching circuit, realizing a read operation during the write operation, that is, read - while - write.

[0073] In an embodiment of the present invention, at the sub - memory - array level, in the normal data read - out mode, a storage unit and a reference unit in the same row are simultaneously activated by the same corresponding read word line; a read voltage is applied to the corresponding source line and reference source line, and the read voltage charges the capacitors corresponding to the storage unit and the reference unit respectively through the read path. Due to the resistance difference on the read path, a voltage difference is generated between the two capacitors, and then through differential amplification and latching operations, the data stored in the storage unit is read out;

[0074] In the normal data write mode, only one storage unit is activated by the corresponding write word line; the write driver circuit applies a write voltage to the corresponding source line and bit line, and the write voltage forms a write current on the write tube and the track layer, making the magnetic moment of the free layer point to the specified direction, thereby writing data into the storage unit;

[0075] In the read - while - write mode, a storage unit and a reference unit in the same row are simultaneously activated by the same corresponding read word line and the same corresponding write word line; the write driver circuit and the reference write driver circuit respectively apply the same write voltage to the corresponding source line, bit line and the corresponding reference source line, reference bit line to write data into the storage unit. The voltage division between the center of the track layer and the two Rsot / 2 reference resistors of the write voltage is equal, and the voltage division charges the capacitors corresponding to the storage unit and the reference unit respectively through the read path. Due to the resistance value difference between the magnetic tunnel junction and the reference resistor, a voltage difference is generated on the two capacitors, and then through differential amplification and latching, the function of reading out the data stored in the storage unit before writing is realized during the write operation.

[0076] Specifically, in the read-with-write mode, a storage unit and a reference unit in the same row are simultaneously activated by the same corresponding read word line and the same corresponding write word line; the write drive circuit and the reference write drive circuit respectively apply the same write voltage to the corresponding source line, bit line, corresponding reference source line, and reference bit line to write data into the storage unit. Since the resistance of the track layer is equal to the sum of the resistances of two Rsot / 2 reference resistors, and the charging path current is smaller than the write current, the voltage division of the write voltage between the center of the track layer and the two Rsot / 2 reference resistors is almost equal. This voltage division charges the corresponding capacitors of the storage unit and the reference unit through the read path. Due to the resistance difference between the magnetic tunnel junction and the reference resistor, a voltage difference is generated on the two capacitors, and then through differential amplification and latching, the function of simultaneously reading the data stored in the storage unit before the write operation is realized during the write operation. The specific operation is as follows:

[0077] In the read-with-write mode, the read transistors M1 and M3 and the write transistors M2 and M4 are all turned on. The read-with-write circuit uses the voltage division of the write voltage to charge the two capacitors connected to the storage unit and the reference unit respectively. Due to the resistance difference between the storage unit and the reference unit, a voltage difference will be generated on the two capacitors. Then, the voltage difference is amplified by the differential amplifier circuit, and finally, the data is latched by the latching circuit, realizing a read operation during the write operation, that is, read-with-write. The write operation of read-with-write is almost the same as that in the normal data writing mode, while the read operation is different from the normal data reading mode. Since the read transistors are turned on, the voltage division of the write voltage applied to the bit line BL and the source line SL at the central position of the track layer will charge the capacitor Cmtj of the storage unit through the MTJ and the read transistor M1. Similarly, the voltage division of the write voltage applied to the reference bit line BLref and the reference source line SLref between the two Rsot / 2 resistors will charge the capacitor Cref of the reference unit through the reference resistor Rref and the reference read transistor M3. By selecting appropriate capacitor values, charging times, and reference resistors, a large charging voltage difference can be generated on the read lines RLmtj and RLref. At the end of charging, the read transistors M1 and M3 are turned off, and the read word line RWL is at a low level and not enabled, that is, the capacitor charge and discharge path is disconnected, and the voltage on the capacitor is kept unchanged. Subsequently, the amplification stage and the latching stage are carried out in sequence to read the data before writing. The working principles of the amplification stage and the latching stage are the same as those in the normal data reading mode.

[0078] For the write operation in the read-with-write working mode, during the charging stage, the read operation charges the capacitor using the voltage division of the write voltage. Since the capacitor charging current is smaller than the write current, even if the write current is divided to charge the capacitor, the impact on the write yield is small. During the amplification stage and the latching stage after the charging stage, since the read transistor is turned off, the read operation is isolated from the write operation, so the subsequent amplification and latching operations have no impact on the write operation. With sufficient write voltage and write pulse width, data writing can be achieved normally. At the same time, using the voltage difference generated by charging the capacitor with the voltage division of the write voltage on the track layer, after amplification and latching, the data before writing can also be read out simultaneously.

[0079] In the read-with-write working mode, the data read operation can be achieved by using the data write operation. A read operation can be performed simultaneously during the write operation to achieve simultaneous reading and writing of the same storage unit, that is, read-with-write.

[0080] In an embodiment of the present invention, the sub-storage array consists of storage units arranged in X rows and Y columns and reference units arranged in X rows and one column;

[0081] All the storage units in each row share the reference unit in the same row;

[0082] All the storage units in each storage array share a write driving circuit, and all the reference units in each storage array share a reference write driving circuit;

[0083] In the normal data writing mode, the write driving circuit is enabled to provide the write voltage to the storage unit;

[0084] In the read-with-write mode, the write driving circuit and the reference write driving circuit are enabled simultaneously to provide the same write voltage to the storage unit and the reference unit respectively.

[0085] Furthermore, the read-with-write circuit conducts the array-level design of the read-with-write circuit for SOT-MRAM. The sub-storage array consists of storage units arranged in X rows and Y columns and reference units arranged in X rows and one column. All the storage units in each row share the reference unit in the same row. All the storage units in each sub-storage array share a write driving circuit, which is enabled in both the normal data writing mode and the read-with-write mode and is used to provide the write voltage to the storage unit in the normal data writing mode and the read-with-write mode. All the reference units in each storage array share a reference write driving circuit, which is only enabled in the read-with-write working mode, and the rest of the logic functions are exactly the same as those of the write driving circuit used for normal data writing, and is used to provide the write voltage to the reference unit in the read-with-write mode. In the read-with-write mode, a read-with-write operation can be performed on any storage unit in the array. Using the reference unit in the same row as the read reference for the read operation of the read-with-write, the operation of simultaneously reading and writing any storage unit in the array is realized.

[0086] In one embodiment of the present invention, all the memory cells and reference cells within each sub - memory array share a set of charging capacitors and discharge tubes, and a transmission gate is used to control whether the read line of the memory cell at a specific address is connected to the capacitor.

[0087] In one embodiment of the present invention, the memory cells in each column of the sub - memory array share a PMOS gating tube. The read voltage source is connected to the source lines of each column of memory cells through the gating tube, and provides a read voltage to the source lines only in the normal data readout mode.

[0088] Specifically, the memory cells in each column of the sub - memory array share a PMOS gating tube. The read voltage source is connected to the source lines of each column of memory cells through the gating tube, and provides a read voltage to the source lines only in the normal data readout mode.

[0089] Furthermore, the read - while - write circuit conducts array - level design of the read - while - write circuit of SOT - MRAM; to reduce the area overhead caused by capacitors, all the memory cells and reference cells within each sub - memory array share a set of charging capacitors and discharge tubes, and a transmission gate is used to control whether the read line of the memory cell at a specific address is connected to the capacitor.

[0090] The present invention adopts the SMIC 40nm CMOS process and 40nm - sized MTJ design, evaluates the impact of process fluctuations on circuit performance through the Monte Carlo (MC) method, and considers the statistical distributions of both global and local transistor parameters. According to the simulation results, when the power supply voltage is 1.2V and the TMR is equal to 120%, at 25°C, under the ssg process corner, the read yield measured by 800 Monte Carlo simulations can reach 98.875%.

[0091] To better understand the purpose, structure, and function of the present invention, the following further describes in detail a read - while - write circuit of a spin - orbit - torque magnetic random access memory according to the present invention with reference to the accompanying drawings.

[0092] Embodiment 1:

[0093] In the single read operation mode, the read operation of the memory cell is controlled by the read line RL and the reference read line RLref, the source line SL and the reference source line SLref, and the read word line RWL. When the logic signal RE is valid, a read voltage is applied to the source line SL and the reference source line SLref through the gated transistor. In the memory cell, the read voltage charges the capacitor Cmtj through the track layer, the MTJ, and the read transistor. In the reference cell, the read voltage charges the capacitor Cref through the Rsot / 2 reference resistor, the Rref reference resistor, and the reference read transistor. Due to the resistance difference, a voltage difference is generated across the capacitors. Since the write word line is not activated, no current flows through the bit line BL and the reference bit line BLref. Subsequently, the read word line RWL stops being enabled, and the capacitor voltage remains unchanged. The read amplifier circuit amplifies the capacitor voltage difference for the first time through differential amplification, and the amplified voltage is at the nodes SAmtj and SAref. At the end of the amplification stage, the voltages at SAmtj and SAref are respectively stored on both sides of the latch circuit. When LAT is high, the latching stage begins. The voltages at SAmtj and SAref are sent to the latch circuit for amplification to the full swing. The output of the latch is the result of two-stage amplification. Assume that the resistance of the memory cell MTJ is Rp. The read OUT will represent "0", and OUTB will represent "1". The timing in the single read operation mode is as Figure 4 shown. The read voltage is set to be slightly greater than the write voltage divided by the write associated with the read to ensure an appropriate common-mode input voltage for the read amplifier circuit.

[0094] Embodiment 2:

[0095] In the single write operation mode, the write operation of the memory cell is controlled by the source line SL, the bit line BL, and the write word line WWL. When the logic signal WE is valid, a write voltage is applied to the source line SL or the bit line BL through the write driver circuit, and the other is applied with a low level to form a write current. The direction of the write current determines whether the written data is "0" or "1". With a sufficient write pulse width, the generated combined magnetic field can change the magnetic moment of the free layer without an external magnetic field, thereby achieving data writing.

[0096] Embodiment 3:

[0097] In the read-while-write operating mode, the simultaneous read and write operations of the memory cell are jointly controlled by the read line RL and the reference read line RLref, the source line SL and the reference source line SLref, the bit line BL and the reference bit line BLref, the write word line WWL and the read word line RWL. When the logic signal RWW (Read While Write) is valid, write voltages are applied to the source line SL and the reference source line SLref, and the bit line BL and the reference bit line BLref through the write drive circuit. In the memory cell, the voltage divided in the center of the track layer by the write voltage charges the capacitor Cmtj through the MTJ and the read transistor. In the reference cell, the voltage divided between the two Rsot / 2 resistors by the write voltage charges the capacitor Cref through the resistor Rref and the reference read transistor. Due to the resistance difference, a voltage difference is generated on the capacitor. Subsequently, the read word line RWL is disabled, and the capacitor voltage remains unchanged, isolating the read and write operations. The write operation proceeds as normal. Subsequently, the read amplifier circuit and the latch circuit operate exactly the same as in the normal data readout mode. Assume that the resistance of the memory cell MTJ is Rp, OUT will represent "0", and OUTB will represent "1". The timing in the read-while-write operating mode is as Figure 5 shown.

[0098] Adding a memory array with a structure as shown in Figure 6 can realize the read and write functions of stored data at the array level, with two operating modes: separate data read and write, and read-while-write, which are controlled by the logic signals RE (separate data readout) / WE (separate data write) / RWW (read-while-write).

[0099] Figure 7 shows the comparison of the read power consumption of this read-while-write circuit in the separate data readout operation with the read power consumption of a conventional memory using a sense amplifier (e.g., OCCSA) to read data. It can be seen that the read power consumption of the read-while-write separate data read P is almost reduced by half compared with the conventional read method, and the read power consumption also decreases in the case of read AP; Figure 8 (a) of Figure 8 shows the power-timing schematic diagram of a conventional memory in the separate read and write and read-while-write modes,

[0100] The read - while - write circuit based on the spin - orbit - torque magnetic random access memory according to an embodiment of the present invention includes a read - while - write circuit that generates a voltage difference after pre - charging a capacitor, a sense amplifier circuit for differentially amplifying the voltage difference of the capacitor, and a latch circuit for latching and outputting data. This circuit has two operating modes: the normal data read - write mode and the read - while - write operating mode. For the data read - write mode, data can be read out at low voltage and high frequency. For the read - while - write mode, in any one of the memory cells in the memory array, a read operation can be simultaneously performed within one write operation cycle, that is, read - while - write. For the challenge that today's large models urgently need high - bandwidth memories, the proposed read - while - write scheme can be used as the basic unit of a dual - port memory, and compared with traditional dual - port memories, it can increase the bandwidth by 100%.

[0101] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above - mentioned terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or N embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0102] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "N" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

Claims

1. A read-with-write circuit based on spin-orbit moment magnetic random access memory, characterized in that: include: A read-accompanying write circuit for generating a voltage difference after precharging the capacitor, a read amplifier circuit for differentially amplifying the capacitor voltage difference, and a latch circuit for latching data and outputting it; The read-with-write circuit that generates a voltage difference after pre-charging the capacitor includes a storage unit and a reference unit; The operation modes of the read-and-write circuit based on the spin-orbit moment magnetic random access memory include a normal data read-and-write mode and a read-and-write mode; In the read-with-write mode, the read-with-write circuit uses the voltage division of the write voltage to charge the two capacitors connected to the storage unit and the reference unit respectively. Due to the resistance difference between the storage unit and the reference unit, a voltage difference is generated on the two capacitors, and then the voltage difference is amplified by the differential amplifier circuit. Finally, the data is latched by the latch circuit, so that a read operation is performed simultaneously during the write operation, that is, read-with-write; In the normal data readout mode, the read voltage is applied to the storage unit and the reference unit through the gate control tube, and the capacitor is charged, the voltage difference is amplified, and the latch operation is performed to achieve high-speed and low-power data readout; In the normal data writing mode, data writing is achieved by applying a write voltage to the storage cell.

2. The circuit according to claim 1, characterized in that The storage unit is composed of a spin-orbit moment magnetic tunnel junction and two NMOS transistors serving as a read transistor and a write transistor respectively, and is called a 2T-1SOT storage unit; The spin-orbit moment magnetic tunnel junction is composed of a magnetic tunnel junction and an orbital layer. The magnetic tunnel junction is composed of a fixed layer, a free layer, and an oxide isolation layer formed of a magnetic medium. The resistance state of the magnetic tunnel junction is determined by the relative magnetization direction of the fixed layer and the free layer. The track layer is made of heavy metal. The track layer generates a combined magnetic field by applying a write current, which changes the magnetization direction of the free layer in the absence of an external magnetic field, thereby changing the resistance of the magnetic tunnel junction. The direction of the write current determines the data written. The memory access operation of the memory cell is controlled by the bit line BL, the source line SL, the read line RL, the write word line WWL, and the read word line RWL.

3. The circuit according to claim 1, characterized in that The reference unit is composed of three resistors and two NMOS tubes; one of the resistors has a resistance value of the reference resistor Rref, and the other two resistors have a resistance value of half the track layer resistance, that is, Rsot / 2; the two NMOS tubes are used as a reference reading tube and a reference writing tube respectively; The operation of the reference cell is controlled by a reference bit line BLref, a reference source line SLref, a reference read line RLref, a write word line WWL, and a read word line RWL.

4. The circuit according to claim 1, 2 or 3, characterized in that: The read-with-write circuit is composed of a 2T-1SOT storage unit, a reference unit, two capacitors and two NMOS discharge tubes; according to the different resistance states of the magnetic tunnel junction, a corresponding charging voltage difference is generated on the two capacitors; the NMOS tube is used to discharge the capacitor after the operation is completed; The read amplifier circuit is composed of four NMOS tubes and three PMOS tubes connected together, and is used for preliminary differential amplification of the charging voltage difference between the storage unit capacitor and the reference unit capacitor; The latch circuit includes three PMOS tubes, three NMOS tubes, two transmission gates, and an inverter, and is used to expand the voltage difference after differential amplification to the full swing and latch data.

5. The circuit according to claim 1, characterized in that At the sub-memory array level, in the normal data read mode, a memory cell and a reference cell in the same row are activated simultaneously by the same corresponding read word line; a read voltage is applied to the corresponding source line and the reference source line, and the read voltage charges the capacitors corresponding to the memory cell and the reference cell respectively through the read path. Due to the resistance difference on the read path, a voltage difference is generated between the two capacitors, and then the data stored in the memory cell is read out through differential amplification and latching operations; In the normal data writing mode, only one storage cell is activated by the corresponding write word line; the write drive circuit applies a write voltage to the corresponding source line and bit line, and the write voltage forms a write current on the write tube and the track layer, so that the magnetic moment of the free layer points to the specified direction, thereby writing data into the storage cell; In the read-with-write mode, a memory cell and a reference cell in the same row are activated simultaneously by the same corresponding read word line and the same corresponding write word line; The write drive circuit and the reference write drive circuit apply the same write voltage to the corresponding source line, bit line and the corresponding reference source line, reference bit line respectively to write data into the storage cell. The write voltage is equal in the divided voltage between the center of the track layer and the two reference resistors of Rsot / 2. ​​The divided voltage charges the capacitors corresponding to the storage cell and the reference cell respectively through the read path. Due to the difference in resistance value between the magnetic tunnel junction and the reference resistor, a voltage difference is generated on the two capacitors. Then, through differential amplification and latching, the function of reading the data stored before writing into the storage cell is realized during the write operation.

6. The circuit according to claim 5, characterized in that The sub-memory array consists of X rows and Y columns of memory cells and X rows and one column of reference cells; All memory cells in each row share the same reference cell in the same row; All storage cells in each storage array share a write driver circuit, and all reference cells in each storage array share a reference write driver circuit; In the normal data writing mode, the write driving circuit is enabled to provide a write voltage to the memory cell; In the read-with-write mode, the write driver circuit and the reference write driver circuit are enabled at the same time, and provide the same write voltage to the storage cell and the reference cell respectively.

7. The circuit according to claim 5, characterized in that All storage cells and reference cells in each sub-storage array share a set of charging capacitors and discharge tubes, and a transmission gate is used to control whether the read line of the storage cell with a specific address is connected to the capacitor.

8. The circuit according to claim 5, characterized in that The memory cells of each column in the sub-memory array share a PMOS gate control tube, and the read voltage source is connected to the source line of each column of memory cells through the gate control tube, and the read voltage is provided to the source line only in the normal data read mode.

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