Memory device including power gating switch

Abstract

A memory device includes: a core peripheral circuit structure including a first bonding metal pad connected to an internal power supply voltage line; and a cell array structure disposed on the core peripheral circuit structure and including a second bonding metal pad in contact with the first bonding metal pad. The cell array structure includes: a memory cell array; and a power gate switch connected between the external power supply voltage line and the first bonding metal pad, and the power gate switch is located in a different region from the memory cell array of the cell array structure and selectively supplies an external power supply voltage to the internal power supply voltage line.

Description

[0001] CROSS - REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2023 - 0171840, filed with the Korean Intellectual Property Office on November 30, 2023, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present inventive concept relates to a semiconductor memory device, and more particularly, to a memory device in which a power gating switch is located in a region different from a memory cell region in a cell array structure. BACKGROUND ART

[0004] As the power consumption of electronic devices becomes increasingly important, the demand for energy - saving electronic devices is also increasing. Memory system power, as part of the power budget of an electronic device, can account for a large portion of the overall system power usage. A memory system may include, for example, dynamic random - access memory (DRAM) implemented on multiple separate DRAM chips.

[0005] A variety of power - saving methods have been implemented in DRAM. For example, DRAM can operate in a power - off mode, in which the internal circuit can be disabled when internal circuit elements are not in use. In the power - off mode, some elements in DRAM may continue to consume power due to the standby current or leakage current of transistors. A power gating switch can be used to reduce standby power consumption. The power gating switch can be located between a power supply and one or more downstream logic elements and can supply power to the downstream logic elements when turned on and cut off the power supply when turned off. SUMMARY OF THE INVENTION

[0006] The present inventive concept provides a memory device in which a power gating switch can be located in a cell array structure in which a plurality of memory cells including vertical - channel transistors are implemented.

[0007] According to an aspect of the present inventive concept, a memory device includes: a core - peripheral circuit structure including an internal power - supply voltage line and a first bonding metal pad connected to the internal power - supply voltage line; and a cell array structure disposed on the core - peripheral circuit structure and including an external power - supply voltage line for conducting an external power - supply voltage applied from the outside of the memory device and a second bonding metal pad in contact with the first bonding metal pad, wherein the cell array structure includes a memory cell array and a power gating switch connected between the external power - supply voltage line and the first bonding metal pad, wherein the power gating switch is located in a region different from the memory cell array in the cell array structure, and the power gating switch is configured to selectively supply the external power - supply voltage to the internal power - supply voltage line.

[0008] According to another aspect of the inventive concept, a memory device includes: a core peripheral circuit structure including an internal ground voltage line and a first bonding metal pad connected to the internal ground voltage line; and a cell array structure disposed on the core peripheral circuit structure and including an external ground voltage line for conducting an external ground voltage applied from the outside of the memory device and a second bonding metal pad in contact with the first bonding metal pad, wherein the cell array structure includes a memory cell array and a power gating switch connected between the external ground voltage line and the first bonding metal pad, wherein the power gating switch is located in a region of the cell array structure different from the memory cell array, and the power gating switch is configured to selectively supply the external ground voltage to the internal ground voltage line.

[0009] According to another aspect of the inventive concept, a memory device includes: a core peripheral circuit structure including an internal power supply voltage line, an internal ground voltage line, a first bonding metal pad connected to the internal power supply voltage line, and a second bonding metal pad connected to the internal ground voltage line; and a cell array structure overlapping the core peripheral circuit structure in a vertical direction and including an external power supply voltage line for conducting an external power supply voltage applied from the outside of the memory device, an external ground voltage line for conducting an external ground voltage applied from the outside of the memory device, a third bonding metal pad in contact with the first bonding metal pad, and a fourth bonding metal pad in contact with the second bonding metal pad, wherein the cell array structure includes: a memory cell array including a plurality of memory cells; and a power gating switch located in a region of the cell array structure different from the memory cell array, the power gating switch including: a first power gating circuit connected between the external power supply voltage line and the third bonding metal pad; and a second power gating circuit connected between the external ground voltage line and the fourth bonding metal pad, and the first power gating circuit is configured to selectively supply the external power supply voltage to the internal power supply voltage line, and the second power gating circuit is configured to selectively supply the external ground voltage to the internal ground voltage line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a diagram conceptually showing a memory device according to an embodiment;

[0012] Figure 2 shows Figure 1 the configuration of the memory device;

[0013] Figure 3 , Figure 4 , Figure 5 and Figure 6is a diagram showing the structure of a storage device according to an embodiment;

[0014] Figure 7 , Figure 8 , Figure 9A and Figure 9B is a diagram showing a power gating switch according to an embodiment; and

[0015] Figure 10 is a system block diagram for explaining an electronic device including a storage device according to an embodiment. Detailed Description of the Embodiments

[0016] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Like components in the drawings are denoted by like reference numerals, and repeated descriptions may be omitted.

[0017] The present disclosure allows for various variations and numerous embodiments, and specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the embodiments to a specific practice mode, and it should be understood that all changes, equivalents, and alternatives that do not depart from the spirit and technical scope of the inventive concept are included in the present disclosure. In the present disclosure, when certain detailed descriptions would obscure the essence of the inventive concept, those detailed descriptions may be omitted.

[0018] Figure 1 is a diagram conceptually showing a storage device 10 according to some embodiments. Figure 2 Shows Figure 1 an example configuration of a storage device.

[0019] Referring to Figure 1 and Figure 2 , the storage device 10 may include a core peripheral circuit 21 and a memory cell array 22. The core peripheral circuit 21 may include a control logic circuit 24, a row decoder 25, a column decoder 26, a power gating switch 27, and a sense amplifier 28. The core peripheral circuit 21 may further include an address buffer 23, an input / output (I / O) gating circuit 2090, a data I / O circuit 2095, etc. In some embodiments, the storage device 10 may be a dynamic random access memory (DRAM), and the DRAM includes a plurality of memory cells having vertical channel transistors and capacitors. Hereinafter, the "storage device" may be referred to as a DRAM.

[0020] The memory cell array 22 can be connected to the row decoder 25. The memory cell array 22 can be connected to the row decoder 25 via the word line WL. The memory cell array 22 can be connected to the sense amplifier 28 via the bit line BL. The memory cell array 22 can include a first bank memory array 2080a, a second bank memory array 2080b, a third bank memory array 2080c, and a fourth bank memory array 2080d. Each of the first to fourth bank memory arrays 2080a, 2080b, 2080c, and 2080d can include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells. The plurality of memory cells can be formed at the intersections of the word lines WL and the bit lines BL.

[0021] The row decoder 25 can include a first bank row decoder 2060a, a second bank row decoder 2060b, a third bank row decoder 2060c, and a fourth bank row decoder 2060d, which are respectively connected to the first to fourth bank memory arrays 2080a, 2080b, 2080c, and 2080d. The column decoder 26 can include a first bank column decoder 2070a, a second bank column decoder 2070b, a third bank column decoder 2070c, and a fourth bank column decoder 2070d, which are respectively connected to the first to fourth bank memory arrays 2080a, 2080b, 2080c, and 2080d. The sense amplifier 28 can include a first sense amplifier 2082a, a second sense amplifier 2082b, a third sense amplifier 2082c, and a fourth sense amplifier 2082d, which are respectively connected to the first to fourth bank memory arrays 2080a, 2080b, 2080c, and 2080d.

[0022] The first to fourth memory bank storage arrays 2080a, 2080b, 2080c, and 2080d, the first to fourth memory bank row decoders 2060a, 2060b, 2060c, and 2060d, the first to fourth memory bank column decoders 2070a, 2070b, 2070c, and 2070d, and the first to fourth sense amplifiers 2082a, 2082b, 2082c, and 2082d may respectively constitute the first memory bank BANK1, the second memory bank BANK2, the third memory bank BANK3, and the fourth memory bank BANK4. The first to fourth memory bank row decoders 2060a, 2060b, 2060c, 2060d, the first to fourth memory bank column decoders 2070a, 2070b, 2070c, 2070d, and the first to fourth sense amplifiers 2082a, 2082b, 2082c, 2082d may be referred to as the core circuits of the first to fourth memory banks BANK1 to BANK4. In an embodiment, although an example in which the memory device 10 includes four memory banks is shown, the present disclosure is not limited thereto, and according to some embodiments, the memory device 10 may include other numbers of memory banks.

[0023] The address buffer 23 may receive an address ADDR including a row address and a column address. The address buffer 23 may receive the address ADDR from a memory controller connected to the memory device 10. In addition, the address ADDR may include a memory bank address. The address buffer 23 may provide the received memory bank address to the memory bank control logic, provide the received row address to the row decoder 25, and provide the received column address to the column decoder 26. The memory bank control logic may generate a memory bank control signal in response to the memory bank address. In response to the memory bank control signal, the memory bank row decoder corresponding to the memory bank address among the first to fourth memory bank row decoders 2060a, 2060b, 2060c, and 2060d may be activated, and the memory bank column decoder corresponding to the memory bank address among the first to fourth memory bank column decoders 2070a, 2070b, 2070c, and 2070d may be activated.

[0024] The control logic circuit 24 may control one or more operations of the memory device 10. The control logic circuit 24 may generate control signals to perform a write operation and / or a read operation of the memory device 10. The control logic circuit 24 may include: a mode register that may set multiple operation options of the memory device 10; and a command decoder that may decode a command CMD received from the memory controller.

[0025] The sense amplifier 28 can sense the data stored in the memory cells. The sense amplifier 28 can send the sensed data to the data I / O circuit 2095 to output the sensed data to the memory controller through the data pads. The data I / O circuit 2095 can receive the data to be written into the memory cells from the memory controller through the data pads. The data I / O circuit 2095 can send the received data to the memory cell array 22. The I / O strobe circuit 2090 can output the read data by using a data line amplifier that receives and amplifies the data sensed by the sense amplifier 28. The read data can be output to the memory controller through the data pads. The I / O strobe circuit 2090 can include a circuit for strobing the I / O data DQ, a column selection circuit, an input data mask logic, a read data latch for storing the read data output from the first to fourth bank memory arrays 2080a, 2080b, 2080c, and 2080d, and a write driver for writing data into the first to fourth bank memory arrays 2080a, 2080b, 2080c, and 2080d.

[0026] The read data output from the bank memory array among the first to fourth bank memory arrays 2080a, 2080b, 2080c, and 2080d can be sensed by the sense amplifiers 2082a, 2082b, 2082c, and 2082d corresponding to the bank memory array and stored in the read data latch. The write data to be written into the memory cell array of the bank memory array among the first to fourth bank memory arrays 2080a, 2080b, 2080c, and 2080d can be provided from the memory controller to the data I / O circuit 2095. The data provided to the data I / O circuit 2095 can be written into the bank memory array through the write driver.

[0027] The memory device 10 can include one or more power gating switches 27. The power gating switches 27 can selectively supply power to the core peripheral circuit 21. The power gating switches 27 can selectively supply power to each of the control logic circuit 24, row decoder 25, column decoder 26, sense amplifier 28, address buffer 23, I / O strobe circuit 2090, and data I / O circuit 2095 included in the core peripheral circuit 21.

[0028] The power gating switch 27 can include a power delivery network PDN configured to supply power to the core peripheral circuit 21. When the power gating switch 27 is included in the same plane as the core peripheral circuit 21 (e.g., in the core peripheral circuit structure CPS ( Figure 3)) Due to the area of the power gating switch 27 in the core-periphery circuit structure CPS, the chip size of the memory device 10 may increase. At this time, due to the limitation of the memory chip size, the number of power gating switches 27 in the core-periphery circuit structure CPS may decrease. The decrease in the number of power gating switches 27 may limit the power delivery network PDN of the core-periphery circuit 21. In addition, due to the area of the power gating switch 27 in the core-periphery circuit structure CPS, the chip size of the memory device 10 may increase. By placing the power gating switch 27 in the blank area of the cell array structure CAS( Figure 3 ), the area occupied by the power gating switch 27 in the core-periphery circuit structure CPS can be reduced, and the chip size of the memory device 10 can be decreased. In addition, when the power gating switch 27 is located in the blank space of the cell array structure CAS, the power delivery network PDN related to the core-periphery circuit 21 can be improved, thereby improving the operating performance of the memory device 10.

[0029] Figure 3 、 Figure 4 、 Figure 5 and Figure 6 are diagrams showing the structure of the memory device 10 according to some embodiments. In the figures, a first direction D1 intersects a second direction D2 to form a horizontal plane, and a third direction D3 intersects the horizontal plane in the vertical direction. Figure 4 is a perspective view showing the cell array structure CAS of the memory device 10 of Figure 3 . Figure 5 is Figure 4 a cross-sectional view of the memory device 10 taken along a position corresponding to the second direction D2 in a perspective view. Figure 6 is Figure 4 a cross-sectional view of the memory device 10 showing a cross-section taken along a position corresponding to the first direction D1. For ease of understanding, expressions such as upper surface / lower surface, top / bottom, up / down, etc. can be understood based on the directions shown in the drawings. Therefore, according to the directions shown in the figures, the same surface can be referred to as the upper surface and the lower surface, respectively.

[0030] Refer to Figure 2 and Figure 3, the memory device 10 may include a cell array structure CAS and a core peripheral circuit structure CPS that overlap each other in the third direction D3. That is, the cell array structure CAS may be disposed on the core peripheral circuit structure CPS. The cell array structure CAS may include a memory cell array 22 and a power gating switch 27. The power gating switch 27 may include a first power gating circuit 27a and a second power gating circuit 27b. The core peripheral circuit structure CPS may include a core peripheral circuit 21, and the core peripheral circuit 21 includes an address buffer 23, a control logic circuit 24, a row decoder 25, a column decoder 26, a sense amplifier 28, an I / O gating circuit 2090, and a data I / O circuit 2095. For the sake of simplicity of the drawings, the circuits forming the control logic circuit 24, the row decoder 25, and the column decoder 26 are shown as being arranged in the core peripheral circuit structure CPS. The memory device 10 may have a structure in which the memory cell array 22 is disposed above the core peripheral circuit (i.e., a cell-on-periphery (COP) structure).

[0031] In the memory cell array 22 of the cell array structure CAS, word lines WL may extend in the first direction D1, and bit lines BL may extend in the second direction D2. Shield bit lines SBL may be disposed adjacent to the bit lines BL. Memory cells including vertical channel transistors may be disposed at points where the word lines WL and the bit lines BL intersect each other.

[0032] The power gating switch 27 of the cell array structure CAS may include a first power gating circuit 27a and a second power gating circuit 27b. In an embodiment, the power gating switch 27 region is shown as being separated from the memory cell array 22 region. The power gating switch 27 may be placed in a blank region in the cell array structure CAS where the memory cell array 22 does not exist. Since the power gating switch 27 is placed in the cell array structure CAS and separated from the memory cell array 22, it may not be necessary to provide a separate region in the cell array structure CAS to accommodate the power gating switch 27.

[0033] In some embodiments, the first power gating circuit 27a may include at least one first transistor connected between an external power supply voltage VDD line and an internal power supply voltage VPWR line ( Figure 8)。The external power supply voltage VDD applied from the outside of the storage device 10 can be supplied to the external power supply voltage VDD line. The first transistor of the first power gating circuit 27a can be configured as a P-type metal oxide semiconductor (PMOS) transistor. When the first transistor is turned on, the external power supply voltage VDD can be supplied to the internal power supply voltage VPWR line, and when the first transistor is turned off, the power supply voltage can be cut off. Therefore, by turning on or off the first transistor, the external power supply voltage VDD can be selectively supplied to the internal power supply voltage VPWR line, and the first transistor can be referred to as a switching transistor.

[0034] In some embodiments, the second power gating circuit 27b may include at least one second transistor connected between the external ground voltage VSS line and the internal ground voltage VGND line ( Figure 8 )。The external ground voltage VSS applied from the outside of the storage device 10 can be supplied to the external ground voltage VSS line. The second transistor can be configured as an N-type metal oxide semiconductor (NMOS) transistor. When the second transistor is turned on, the external ground voltage VSS can be supplied to the internal ground voltage VGND line, and when the second transistor is turned off, the ground voltage supply can be cut off. Therefore, by turning on or off the second transistor, the external ground voltage VSS can be selectively supplied to the internal ground voltage VGND line, and the second transistor can be referred to as a switching transistor.

[0035] In some embodiments, the external power supply voltage VDD and the external ground voltage VSS may be the power supplies provided to the storage device 10 from the outside of the storage device 10, and the internal power supply voltage VPWR and the internal ground voltage VGND may be the power supplies of the core peripheral circuit 21 of the storage device 10 (for example Figure 8 )。In this case, the core peripheral circuit 21 may refer to downstream logic elements.

[0036] The core peripheral circuit structure CPS may include a semiconductor substrate, and the core peripheral circuit 21 may be formed by forming semiconductor elements (such as transistors) and patterns for connecting these elements on the semiconductor substrate. After the core peripheral circuit 21 is formed in the core peripheral circuit structure CPS, a cell array structure CAS including a memory cell array 22 may be formed, and patterns may be formed (for example, Figure 5The bonding metal pads 301 and 302) to electrically connect the word lines WL, bit lines BL, and shield bit lines SBL of the memory cell array 22 to the core peripheral circuit 21 formed in the core peripheral circuit structure CPS. However, the present disclosure is not limited thereto. The cell array structure CAS may be formed before the core peripheral circuit structure CPS, or the core peripheral circuit structure CPS and the cell array structure CA may be formed simultaneously and bonded together. In addition, a pattern may be formed for electrically connecting the power gating switch 27, the internal power supply voltage line VPWR, and the internal ground voltage VGND line to each other (e.g., Figure 5 the bonding metal pads 301 and 302) in

[0037] Referring together to Figure 4 、 Figure 5 、 Figure 6 , the core peripheral circuit structure CPS may include a lower substrate 310, an interlayer insulating film 315, a plurality of circuit elements 312a and 312b (or a first circuit element 312a and a second circuit element 312b), first metal layers 314a and 314b respectively connected to the circuit elements 312a and 312b, second metal layers 316a and 316b formed on the first metal layers 314a and 314b, and a bonding metal pad 301 formed on the uppermost metal layer of the core peripheral circuit structure CPS. In an embodiment, the first metal layers 314a and 314b may include tungsten having a relatively high resistance, the second metal layers 316a and 316b may include copper having a relatively low resistance, and the bonding metal pad 301 may include copper. In another embodiment, the bonding metal pad 301 may include aluminum (Al) or tungsten (W).

[0038] Although the first metal layers 314a and 314b and the second metal layers 316a and 316b are shown and described in this specification, the present specification is not limited thereto, and at least one metal layer may be formed on the second metal layers 316a and 316b. At least some of one or more metal layers on the top of the second metal layers 316a and 316b may include aluminum or the like, which has a lower resistance than the copper forming the second metal layers 316a and 316b. The interlayer insulating film 315 may be disposed on the lower substrate 310 to cover the circuit elements 312a and 312b, the first metal layers 314a and 314b, and the second metal layers 316a and 316b. For example, the interlayer insulating film 315 may seal the circuit elements 312a and 312b, the first metal layers 314a and 314b, and the second metal layers 316a and 316b. The interlayer insulating film 315 may include an insulating material such as silicon oxide, silicon nitride, etc.

[0039] The circuit elements 312a and 312b can be connected to at least one circuit element forming the core peripheral circuit 21. For convenience of description, the first circuit element 312a represents a transistor forming the row decoder 25, and the second circuit element 312b represents a transistor forming the control logic circuit 24.

[0040] In the memory device 10, the bit lines BL can be disposed on the upper substrate 320 and can be spaced apart from each other in the first direction D1. The upper substrate 320 is expressed to indicate that the upper substrate 320 is an element corresponding to the lower substrate 310. According to some embodiments, the upper substrate 320 may be referred to as a plate or a conductive plate. The bit lines BL can be spaced apart from each other in the first direction D1 and extend in a second direction D2 intersecting the first direction D1. The active patterns AP can be alternately disposed on each bit line BL in the second direction D2. The active patterns AP can be spaced apart from each other at regular intervals in the first direction D1. That is, the active patterns AP can be two-dimensionally arranged in the first direction D1 and the second direction D2 intersecting each other. In some embodiments, the word lines WL, the bit lines BL, and the plurality of active patterns AP can form a plurality of vertical channel transistors.

[0041] Each active pattern AP can have a length in the first direction D1, a width in the second direction D2, and a height in a third direction D3 perpendicular to the upper substrate 320. Each active pattern AP can have a substantially uniform width. Each active pattern AP can have an upper surface and a lower surface facing each other in the third direction D3. For example, the lower surface of the active pattern AP can contact the bit line BL. Each active pattern AP can include a source region adjacent to the bit line BL, a drain region adjacent to the contact pattern BC, and a channel region disposed between the source region and the drain region. During the operation of the memory device 10, the channel region of the active pattern AP can be controlled by the word line WL and the back gate electrode BG. The active pattern AP can include, for example, single-crystalline silicon (Si), which can improve the leakage current characteristics during the operation of the memory device 10.

[0042] The back gate electrodes BG may be disposed to be separated from each other at a predetermined interval along a second direction D2 on the bit lines BL. The back gate electrodes BG may extend across the bit lines BL along a first direction D1. Each back gate electrode BG may be located between adjacent active patterns AP in the second direction D2. For example, the back gate electrode BG may be located between a pair of active patterns AP in the second direction D2. The first active pattern 191 may be located on a first side of each back gate electrode BG, and the second active pattern 192 may be located on a second side of each back gate electrode BG. The height of the back gate electrode BG in the vertical direction may be less than the height of the active pattern AP in the vertical direction. During the operation of the memory device 10, a negative voltage may be applied to the back gate electrodes BG, and the threshold voltage of the vertical channel transistor may be increased. As the vertical channel transistor becomes smaller, the threshold voltage decreases and the deterioration of the leakage current characteristics may be reduced or prevented.

[0043] The first insulating pattern 111 may be located between adjacent active patterns AP in the second direction D2. The first insulating pattern 111 may extend parallel to the back gate electrodes BG along the first direction D1. The back gate insulating layer 113 may be located between each back gate electrode BG and each active pattern AP and between the back gate electrode BG and the first insulating pattern 111. The back gate insulating layer 113 may include a vertical portion covering the side surfaces of the back gate electrodes BG and a horizontal portion connecting the vertical portions to each other. The horizontal portion of the back gate insulating layer 113 may be closer to the contact pattern BC than the bit line BL and may cover the upper surface of the back gate electrode BG. The back gate capping pattern 115 may be located between the bit line BL and the back gate electrode BG. The back gate capping pattern 115 may include an insulating material, and the lower surface of the back gate capping pattern 115 may be in contact with the bit line BL. The back gate capping pattern 115 may be located between the vertical portions of the back gate insulating layer 113.

[0044] The word lines WL may extend along the first direction D1 on the bit lines BL and may be alternately arranged along the second direction D2. The first word line 181 among the word lines WL may be disposed on a first side of the first active pattern 191, and the second word line 182 among the word lines WL may be disposed on a second side of the second active pattern 192. For example, a pair of word lines WL may be disposed outside a pair of active patterns including the first active pattern 191 and the second active pattern 192. A part of the first word line 181 may be located between the first active patterns 191 adjacent in the first direction D1, and a part of the second word line 182 may be located between the second active patterns 192 adjacent in the first direction D1.

[0045] The word line WL can be vertically disposed and separated from the bit line BL and the contact pattern BC. From a vertical perspective, the word line WL can be located between the bit line BL and the contact pattern BC. Adjacent word lines WL can have sidewalls facing each other. The height of the word line WL in the vertical direction can be less than the height of the active pattern AP in the vertical direction. The height of the word line WL in the third direction D3 can be equal to or greater than the height of the back gate electrode BG in the third direction D3.

[0046] The gate insulating film 160 can be located between the word line WL and the active pattern AP. The gate insulating film 160 can extend along the first direction D1 and can be substantially parallel to the word line WL. The gate insulating film 160 can cover one surface of the first active pattern 191 and the other surface of the second active pattern 192. The gate insulating film 160 can have a substantially uniform thickness. The second insulating pattern 141 can be located between the gate insulating film 160 and the contact pattern BC. For example, the second insulating pattern 141 can include silicon oxide. The first etch stop layer 131 and the second etch stop layer 133 can be located between the active pattern AP and the second insulating pattern 141.

[0047] On the gate insulating film 160, the word lines WL can be separated from each other by the third insulating pattern 151. The third insulating pattern 151 can extend along the first direction D1 between the word lines WL. The first capping film 153 can be located between the third insulating pattern 151 and the word lines WL. The first capping film 153 can have a substantially uniform thickness. The third insulating pattern 151 can include a third vertical pattern 151A and a third horizontal pattern 151B.

[0048] The contact pattern BC can pass through the third etch stop layer 210 and the interlayer insulating film 220 and be respectively connected to the active pattern AP. In other words, the contact pattern BC can be respectively connected to the drain regions of the active pattern AP. The lower width of the contact pattern BC can be greater than the upper width of the contact pattern BC. Adjacent contact patterns BC can be separated from each other by the separation insulating pattern 230. Each contact pattern BC can have various shapes in a plan view, such as circular, oval, rectangular, square, rhombic or hexagonal. The landing pad LP can be respectively disposed on the contact pattern BC.

[0049] The separation insulating pattern 230 can be located between the landing pads LP. In a plan view, the landing pads LP can be arranged in a matrix form along the first direction D1 and the second direction D2. The upper surface of the landing pad LP can be substantially coplanar with the upper surface of the separation insulating pattern 230. The fourth etch stop layer 240 can be formed on the separation insulating pattern 230.

[0050] The data storage pattern DSP can be disposed on the landing pad LP. The data storage pattern DSP can be electrically connected to the active pattern AP respectively. The data storage pattern DSP can be arranged in a matrix form along the first direction D1 and the second direction D2. The data storage pattern DSP can completely or partially overlap with the landing pad LP. The data storage pattern DSP can contact all or part of the upper surface of the landing pad LP. The upper insulating layer 260 can be disposed on the data storage pattern DSP, and the cell contact plug PLG can pass through the upper insulating layer 260 and be connected to the plate electrode 255.

[0051] In some embodiments, the data storage pattern DSP can be a capacitor and can include a capacitor dielectric film 253 located between the storage electrode 251 and the plate electrode 255. In this case, the storage electrode 251 can be in direct contact with the landing pad LP and can have various shapes in a plan view, such as circular, oval, rectangular, square, diamond, or hexagonal.

[0052] In some embodiments, the data storage pattern DSP can be a variable resistance pattern, which can be switched between two resistance states by an electrical pulse applied to the storage element. For example, the data storage pattern DSP can include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, an antiferromagnetic material, etc., whose crystal state changes according to the magnitude of the current, but is not limited thereto. According to the material film of the data storage pattern DSP, the storage device 10 can be implemented as a resistive memory, such as a phase change random access memory (PRAM), a magnetic RAM (MRAM), or a resistive RAM (RRAM).

[0053] The shield bit line SBL can be located between and below the bit lines BL. The shield bit line SBL can reduce the coupling noise between adjacent bit lines BL. For example, the shield bit line SBL can be a shield structure including a conductive material. The first line insulating layer 173 can be disposed separately from each other along the first direction D1 and extend along the second direction D2. The first line insulating layer 173 can be formed to contact the opposite sidewalls of adjacent bit lines BL and be separated from each other in the first direction D1. The second line insulating layer 325 can be formed to surround the bottom surface and side surfaces of the shield bit line SBL and fill the space between the shield bit lines SBL.

[0054] The through electrode 322 may pass through the upper substrate 320 to contact the metal layer 318b and extend in the third direction (D3 direction) to reach the bonding metal pad 302 formed on the uppermost metal layer of the core peripheral circuit structure CPS. In the embodiment, only one of the metal layers 318a and 318b is shown and described, but it is not limited thereto, and at least one metal layer may be formed on the metal layers 318a and 318b. The shielding bit line SBL may be electrically connected to the second circuit element 312b of the control logic circuit 24 through the bonding metal pad 302 of the cell array structure CAS and the bonding metal pad 301 of the core peripheral circuit structure CPS. The shielding bit line SBL may be controlled by the control logic circuit 24. When the control logic circuit 24 detects and amplifies the data of the memory cell selected from the memory cell array 22, the control logic circuit 24 may selectively provide a specific voltage (e.g., a bit line precharge voltage, a power supply voltage, or a ground voltage) to the shielding bit line SBL so that the shielding bit line SBL is in a floating state.

[0055] In some embodiments, the bonding metal pad 302 of the cell array structure CAS and the bonding metal pad 301 of the core peripheral circuit structure CPS can be electrically and / or physically connected to each other by a bonding method. When the bonding metal pads 301 and 302 include copper (Cu), the bonding method can be a Cu-Cu bonding method. As another example, the bonding metal pads 301 and 302 may include aluminum (Al) or tungsten (W).

[0056] The metal layer 318a of the cell array structure CAS may be electrically and / or physically connected to each word line WL, and may be in contact with the bonding metal pad 302. Each word line WL may be electrically connected to the first circuit element 312a of the row decoder 25 through the bonding metal pad 302 of the cell array structure CAS and the bonding metal pad 301 of the core peripheral circuit structure CPS. The components and operations of the power gating switch 27 located in the cell array structure CAS are described in detail below through various embodiments.

[0057] Figure 7 , Figure 8 , Figure 9A and Figure 9B is a diagram illustrating a power gating switch 27 according to some embodiments. Figure 7 and Figure 8 is a diagram showing the architecture of the power gating switch 27 located in the memory device 10 . Figure 9A and Figure 9B FIG. 2 shows a power gating switch 27 implemented in a cell array structure CAS. For the sake of clarity, Figure 7 Shows Figure 2 The first memory bank BANK1 and the second memory bank BANK2.

[0058] Combined with Figure 2 and Figure 3 with reference to Figure 7 ,the memory device 10 may include a cell array structure CAS and a core peripheral circuit structure CPS that overlap each other in a third direction (D3 direction). The cell array structure CAS may include a first bank memory array 2080a region, a second bank memory array 2080b region, and a power gating switch 27 region. The power gating switch 27 region may be located between the first bank memory array 2080a region and the second bank memory array 2080b region.

[0059] In some embodiments, the memory cell array 22 in the cell array structure CAS may be divided into first to fourth bank memory arrays 2080a, 2080b, 2080c, 2080d, and the first to fourth bank memory arrays 2080a, 2080b, 2080c, 2080d may be arranged to be separated from each other at a predetermined interval. The separation region R1 of the first to fourth bank memory arrays 2080a, 2080b, 2080c, and 2080d may be different from the memory cell region. For example, the separation region R1 may be adjacent to the memory cell region, separated from the memory cell region, etc. The separation region R1 may omit the vertical channel transistor structure and the capacitor structure connected to the vertical channel transistor structure respectively. This means that the separation region R1 may be a blank region of the cell array structure CAS. The power gating switch 27 may be provided in a blank region of the cell array structure CAS that is different from the memory cell region.

[0060] In an embodiment, an example in which the power gating switch 27 region is located between the first bank memory array 2080a region and the second bank memory array 2080b region is described, but this is only an example for helping understanding and is not intended to limit the inventive concept. In other embodiments, the power gating switch 27 region may be provided in any blank region of the cell array structure CAS. For example, the power gating switch 27 region may be provided in a region of the cell array structure CAS that is different from the region of the memory cell array.

[0061] In the core peripheral circuit structure CPS, the regions of the first bank row decoder 2060a and the second bank row decoder 2060b corresponding to the first bank memory array 2080a and the second bank memory array 2080b, respectively, may be separated from each other. From a vertical perspective, the areas of the regions of the first bank row decoder 2060a and the second bank row decoder 2060b may partially overlap with the regions of the first bank memory array 2080a and the second bank memory array 2080b. A plurality of bonding metal pads 301 connected to the power gating switch 27 of the cell array structure CAS may be included between the regions of the first bank row decoder 2060a and the second bank row decoder 2060b.

[0062] In an embodiment, the row decoder 25 including the first bank row decoder 2060a and the second bank row decoder 2060b may be described as being located in the core peripheral circuit structure CPS, but is not limited thereto, and specific circuits of the core peripheral circuit 21 may be included. For example, the control logic circuit 24, the column decoder 26, the sense amplifier 28, the address buffer 23, the I / O gating circuit 2090, or the data I / O circuit 2095 may be located in the core peripheral circuit structure CPS to replace the row decoder 25.

[0063] Referring to Figure 7 and Figure 8 , the power gating switch 27 of the cell array structure CAS may include a first power gating circuit 27a and a second power gating circuit 27b. The first power gating circuit 27a may include a plurality of PMOS transistors 811 and 812, which are electrically connected between the external power supply voltage VDD line of the cell array structure CAS and the internal power supply voltage VPWR line of the core peripheral circuit structure CPS. The plurality of PMOS transistors 811 and 812 may be connected in parallel between the external power supply voltage VDD line of the cell array structure CAS and the internal power supply voltage VPWR line. Each of the PMOS transistors 811 and 812 may be connected between the external power supply voltage VDD line and the bonding metal pad 302 of the cell array structure CAS, and the bonding metal pad 302 of the cell array structure CAS may be in contact with the bonding metal pad 301 connected to the internal power supply voltage VPWR line of the core peripheral circuit structure CPS.

[0064] The second power gating circuit 27b may include a plurality of NMOS transistors 821 and 822, which are electrically connected between the external ground voltage VSS line of the cell array structure CAS and the internal ground voltage VGND line of the core peripheral circuit structure CPS. The plurality of NMOS transistors 821 and 822 may be connected in parallel between the external ground voltage VSS line and the internal ground voltage VGND line. The NMOS transistors 821 and 822 may be connected between the external ground voltage VSS line and the bonding metal pad 302 of the cell array structure CAS, and the bonding metal pad 302 of the cell array structure CAS may be in contact with the bonding metal pad 301 connected to the internal ground voltage VGND line of the peripheral circuit structure CPS.

[0065] In some embodiments, the PMOS transistors 811 and 812 of the first power gating circuit 27a and the NMOS transistors 821 and 822 of the second power gating circuit 27b may be controlled by the control logic circuit 24. The control logic circuit 24 may be configured to control the PMOS transistors 811 and 812 to conduct, so as to supply the external power voltage VDD to the internal power voltage VPWR line. The control logic circuit 24 may be configured to control the PMOS transistors 811 and 812 to cut off, so as to cut off the supply of the external power voltage VDD to the internal power voltage VPWR line. The control logic circuit 24 may be configured to supply the external ground voltage VSS to the internal ground voltage VGND line when the NMOS transistors 821 and 822 conduct, and be configured to cut off the supply of the external ground voltage VSS to the internal ground voltage VGND line when the NMOS transistors 821 and 822 cut off. The PMOS transistors 811 and 812 of the first power gating circuit 27a and the NMOS transistors 821 and 822 of the second power gating circuit 27b may be used as switching transistors.

[0066] In combination Figure 5 、 Figure 7 and Figure 8 with reference to Figure 9A , memory cells including a data storage pattern DSP, a word line WL, a back gate electrode BG, an active pattern AP, a bit line BL, and a shield bit line SBL may be arranged in each of the first bank memory array 2080a and the second bank memory array 2080b regions of the cell array structure CAS. The word line WL, the active pattern AP, and the bit line BL may form a vertical channel transistor VCT. The active pattern AP of the vertical channel transistors VCT in the first bank memory array 2080a and the second bank memory array 2080b may include a first type of conductive material, such as an N-type conductive material.

[0067] In the power gating switch 27 region of the cell array structure CAS, the first power gating circuit 27a and the second power gating circuit 27b can be connected to an external power supply voltage VDD line and an external ground voltage VSS line through I / O contact plugs 901 and 902. The respective PMOS transistors 811 and 812 and NMOS transistors 821 and 822 of the first power gating circuit 27a and the second power gating circuit 27b can be formed in the process of forming the vertical channel transistors VCT of the first bank memory array 2080a and the second bank memory array 2080b. That is to say, the PMOS transistors 811 and 812 and the NMOS transistors 821 and 822 of the first power gating circuit 27a and the second power gating circuit 27b can be formed to have the same structure as the vertical channel transistors VCT. Therefore, the PMOS transistors 811 and 812 and the NMOS transistors 821 and 822 can be implemented to have the same pattern as the vertical channel transistors VCT. The PMOS transistors 811 and 812 and the NMOS transistors 821 and 822 of the first power gating circuit 27a and the second power gating circuit 27b can be implemented in a configuration where multiple vertical channel transistors VCT are connected in parallel. That is to say, the PMOS transistors 811 and 812 can be connected in parallel between the external power supply voltage VDD line and the internal power supply voltage VPWR line, and the NMOS transistors 821 and 822 can be connected in parallel between the external ground voltage VSS line and the internal ground voltage VGND line.

[0068] In some embodiments, the transistors 811 and 812 of the first power gating circuit 27a can include a second type of conductive material, such as a P-type conductive material, in the active pattern AP of the vertical channel transistor VCT. The transistors 821 and 822 of the second power gating circuit 27b can include a first type of conductive material, such as an N-type conductive material, in the active pattern AP of the vertical channel transistor VCT. That is to say, the transistors 811 and 812 of the first power gating circuit 27a and the transistors 821 and 822 of the second power gating circuit 27b can have opposite conductive types. In addition, the transistors 821 and 822 of the second power gating circuit 27b can have the same conductive type as the active pattern AP of the vertical channel transistors VCT in the first bank memory array 2080a and the second bank memory array 2080b.

[0069] In the first power gating circuit 27a, a first I / O contact plug 901 connected to an external power supply voltage VDD line may be connected in parallel to the active patterns AP of transistors 811 and 812 and a bit line BL. A third I / O contact plug 903 connected to the bit line BL to which transistors 811 and 812 are connected in parallel may be connected to an internal power supply voltage VPWR line 905 of the core peripheral circuit structure CPS. The word lines WL of transistors 811 and 812 may also be connected in parallel, and transistors 811 and 812 may be controlled by the control logic circuit 24 to be turned on or off.

[0070] In the second power gating circuit 27b, a second I / O contact plug 902 connected to an external ground voltage VSS line may be connected in parallel to the active patterns AP of transistors 821 and 822 and a bit line BL, and a fourth I / O contact plug 904 connected to the bit line BL to which transistors 821 and 822 are connected in parallel may be connected to an internal ground voltage VGND line 906 of the core peripheral circuit structure CPS. The word lines WL of transistors 821 and 822 may also be connected in parallel, and transistors 821 and 822 may be controlled by the control logic circuit 24 to be turned on or off.

[0071] Combined Figure 5 、 Figure 7 、 Figure 8 Referring Figure 9B , in the cell array structure CAS, the first bank memory array 2080a and the second bank memory array 2080b regions and the power gating switch 27 region may be disposed above the internal power supply voltage VPWR line 905 and the internal ground voltage VGND line 906. A first I / O contact plug 911 connected to an external power supply voltage VDD line 915 may be connected in parallel to the active patterns AP of transistors 811 and 812 and a bit line BL. A third I / O contact plug 913 connected to the bit line BL to which transistors 811 and 812 are connected in parallel may be connected to an internal power supply voltage VPWR line 905 of the core peripheral circuit structure CPS. A second I / O contact plug 912 connected to an external ground voltage VSS line 916 may be connected in parallel to the active patterns AP of transistors 821 and 822 and a bit line BL, and a fourth I / O contact plug 914 connected to the bit line BL to which transistors 821 and 822 are connected in parallel may be connected to an internal ground voltage VGND line 906 of the core peripheral circuit structure CPS.

[0072] In some embodiments, the PMOS transistors 811 and 812 and the NMOS transistors 821 and 822 of the first power gating circuit 27a and the second power gating circuit 27b may be implemented as fin field-effect transistors (finFETs). The finFET may include: a gate structure extending along a second direction perpendicular to the first direction on the upper substrate 320 of the cell array structure CAS while covering a portion of the fin-shaped active region extending in the first direction; and source and drain regions disposed on both sides of the gate structure along the first direction.

[0073] In some embodiments, the PMOS transistors 811 and 812 and the NMOS transistors 821 and 822 of the first power gating circuit 27a and the second power gating circuit 27b may be implemented as planar field-effect transistors. The planar field-effect transistor may include: a gate structure extending along the second direction on the upper substrate 320 of the cell array structure CAS; and source and drain regions disposed on both sides of the gate structure along a first direction perpendicular to the second direction.

[0074] As described herein, the chip size of the memory device 10 can be reduced by placing the power gating switches in the blank spaces of the cell array structure. For example, the power gating switches may be disposed in a region of the cell array structure different from the memory cell array. In addition, by improving the power delivery network PDN by utilizing the power gating switches located in the cell array structure, the operating performance of the memory device 10 can be enhanced.

[0075] Figure 10 is a block diagram of the system 1000, showing an electronic device including a memory device according to some embodiments.

[0076] Referring to Figure 10 , the system 1000 may include a camera 1100, a display 1200, an audio processor 1300, a modem 1400, DRAMs 1500a and 1500b, flash memories 1600a and 1600b, I / O devices 1700a and 1700b, and an application processor (AP) 1800. The system 1000 may be implemented as a laptop computer, a mobile phone, a smartphone, a tablet personal computer, a wearable device, a healthcare device, or an Internet of Things (IoT) device. In addition, the system 1000 may be implemented as a server or a personal computer.

[0077] The camera 1100 can capture still images or moving images under user control and store or send the captured image / video data to the display 1200. The audio processor 1300 can process audio data or network content included in the flash memories 1600a and 1600b. The modem 1400 can modulate and send signals for wired / wireless data transmission and reception, and the receiving end can demodulate the sent signals to restore the original signals. The I / O devices 1700a and 1700b can include devices providing digital input and / or output functions, such as universal serial bus (USB) or memory, digital camera, secure digital (SD) card, digital versatile disc (DVD), network adapter, touch screen, etc.

[0078] The AP 1800 can control the overall operation of the system 1000. The AP 1800 can include a controller block 1810, an accelerator block or accelerator chip 1820, and an interface block 1830. The AP 1800 can control the display 1200 such that some content stored in the flash memories 1600a and 1600b can be displayed on the display 1200. When user input is received through the I / O devices 1700a and 1700b, the AP 1800 can perform control operations corresponding to the user input. The AP 1800 can include an accelerator block which can be a dedicated circuit for artificial intelligence (AI) data calculation or can include an accelerator chip 1820 separated from the AP 1800. The DRAM 1500b can be additionally installed on the accelerator block or accelerator chip 1820. The accelerator can be a functional block that specifically executes a particular function of the AP 1800 and can include: a graphics processing unit (GPU), which can be a functional block dedicated to graphics data processing; a neural processing unit (NPU), which can be a block dedicated to AI calculation and inference; or a data processing unit (DPU), which can be a block dedicated to data transfer.

[0079] The system 1000 can include multiple DRAMs 1500a and 1500b. The AP 1800 can control the DRAMs 1500a and 1500b through commands and mode register (MRS) settings compliant with the Joint Electron Device Engineering Council (JEDEC) standards, or can set an interface protocol to perform communication to use entity-specific functions (such as low voltage / high speed / reliability) and cyclic redundancy check (CRC) / error correction code (ECC) functions. For example, the AP 1800 can communicate with the DRAM 1500a through a JEDEC-standard compliant interface such as LPDDR4 and LPDDR5. To control the DRAM 1500b for the accelerator with a higher bandwidth than the DRAM 1500a, the accelerator block or accelerator chip 1820 can communicate by setting a new DRAM interface protocol.

[0080] In Figure 10 only DRAMs 1500a and 1500b are shown, but the inventive concept is not limited thereto, and any memory such as PRAM, SRAM, MRAM, RRAM, FRAM, or hybrid RAM may be used as long as the bandwidth, response speed, and voltage conditions of the AP1800 or the accelerator chip 1820 are satisfied. DRAMs 1500a and 1500b have relatively smaller latency and bandwidth than I / O devices 1700a and 1700b or flash memories 1600a and 1600b. DRAMs 1500a and 1500b may be initialized when the system 1000 is powered on, and an operating system and application data may be loaded into DRAMs 1500a and 1500b such that DRAMs 1500a and 1500b may be used as a temporary storage location or may be used as an execution space for various software codes.

[0081] In DRAMs 1500a and 1500b, arithmetic operations such as addition / subtraction / multiplication / division, vector operations, address operations, or fast Fourier transform (FFT) operations may be performed. In addition, functions for inference may be performed within DRAMs 1500a and 1500b. Here, an artificial neural network may be used to perform inference with a deep learning algorithm. The deep learning algorithm may include a training operation of training a model through various data and an inference operation of identifying data using the trained model. For example, an image captured by the user through the camera 1100 may be subjected to signal processing and stored in DRAM 1500b, and the accelerator block or the accelerator chip 1820 may perform AI data operations using the data stored in DRAM 1500b and a function for inference to identify the data.

[0082] The system 1000 may include a plurality of storage devices or a plurality of flash memories 1600a and 1600b. The plurality of flash memories 1600a and 1600b may have a relatively larger capacity than DRAMs 1500a and 1500b. The accelerator block or the accelerator chip 1820 may use the flash memories 1600a and 1600b to perform training operations and AI data operations. In an embodiment, the flash memories 1600a and 1600b may include a storage controller 1610 and flash memory devices 1620, and may effectively perform training operations and inference AI data operations performed by the AP 1800 and / or the accelerator chip 1820 by using a computing device provided in the storage controller 1610. The flash memories 1600a and 1600b may store photos taken through the camera 1100 or data transmitted through a data network. For example, the flash memories 1600a and 1600b may store augmented reality / virtual reality, high definition (HD), or ultra high definition (UHD) content.

[0083] In system 1000, DRAMs 1500a and 1500b may be the memory devices referred to herein Figures 1 to 9B and described. The memory device may include: a core peripheral circuit structure disposed on a semiconductor substrate; and a cell array structure overlapping the core peripheral circuit structure in a vertical direction on the core peripheral circuit structure. The core peripheral circuit structure may include: a core peripheral circuit; an internal power supply voltage line and an internal ground voltage line connected to the core peripheral circuit; a first bonding metal pad connected to the internal power supply voltage line; and a second bonding metal pad connected to the internal ground voltage line. The core peripheral circuit structure may not include a memory cell array among the components of the memory device. The cell array structure may include: a memory cell array including a third bonding metal pad in contact with the first bonding metal pad, a fourth bonding metal pad in contact with the second bonding metal pad, a plurality of vertical channel transistor structures, and a plurality of capacitor structures respectively connected to the vertical channel transistor structures; an external power supply voltage line provided with an external power supply voltage applied from outside the memory device; an external ground voltage line provided with an external ground voltage applied from outside the memory device; and a power gating switch located in a blank area of the cell array structure. The power gating switch may selectively supply the external power supply voltage to the internal power supply voltage line using a first power gating circuit connected between the external power supply voltage line and the first bonding metal pad, and selectively supply the external ground voltage to the internal ground voltage line using a second power gating circuit connected between the external ground voltage line and the second bonding metal pad. By placing the power gating switch in the blank area (e.g., an area other than the memory cell array) of the cell array structure, the chip size of the memory device can be reduced, and the power delivery network (PDN) of the core peripheral circuit can be improved, thereby improving the operating performance of the memory device.

[0084] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: a core peripheral circuit structure including an internal power supply voltage line and a first bonding metal pad connected to the internal power supply voltage line; as well as a cell array structure disposed on the core peripheral circuit structure and comprising an external power supply voltage line for conducting an external power supply voltage applied from outside the memory device and a second bonding metal pad in contact with the first bonding metal pad, wherein the cell array structure comprises a memory cell array and a power gating switch connected between the external power supply voltage line and the first bonding metal pad, wherein the power gating switch is located in a region of the cell array structure different from the memory cell array, and The power gating switch is configured to selectively provide the external power supply voltage to the internal power supply voltage line.

2. The memory device according to claim 1, wherein: The power gating switch includes: a plurality of switch transistors electrically connected between the external power supply voltage line and the internal power supply voltage line.

3. The memory device according to claim 2, wherein: The plurality of switching transistors are connected in parallel between the external power supply voltage line and the internal power supply voltage line.

4. The memory device according to claim 1, further comprising a plurality of vertical channel transistors, Each of the plurality of vertical channel transistors comprises: a portion of an upper substrate; A bit line is disposed on the upper substrate and extends along a second direction intersecting the first direction; a pair of active patterns disposed on the bit lines; a back gate electrode, located between the pair of active patterns and extending along the first direction; as well as A pair of word lines is disposed outside the pair of active patterns and extends along the first direction.

5. The memory device according to claim 4, wherein: The power gating switch includes: a plurality of switch transistors electrically connected between the external power supply voltage line and the internal power supply voltage line, and Each of the plurality of switch transistors has the same structure as the plurality of vertical channel transistors, and the pair of active patterns of the plurality of switch transistors has an opposite conductivity type to the pair of active patterns of the plurality of vertical channel transistors.

6. The memory device according to claim 4, wherein: The memory cell array includes a shielding bit line located between a plurality of bit lines including the bit line and below the plurality of bit lines.

7. A storage device comprising: a core peripheral circuit structure including an internal ground voltage line and a first bonding metal pad connected to the internal ground voltage line; as well as a cell array structure disposed on the core peripheral circuit structure and comprising an external ground voltage line for conducting an external ground voltage applied from outside the memory device and a second bonding metal pad in contact with the first bonding metal pad, The cell array structure includes a memory cell array and a power gating switch connected between the external ground voltage line and the first bonding metal pad, wherein the power gating switch is located in a region of the cell array structure different from the memory cell array, and The power gating switch is configured to selectively provide the external ground voltage to the internal ground voltage line.

8. The memory device according to claim 7, wherein: The power gating switch includes a plurality of switch transistors electrically connected between the external ground voltage line and the internal ground voltage line.

9. The memory device according to claim 8, wherein: The plurality of switching transistors are connected in parallel between the external ground voltage line and the internal ground voltage line.

10. The memory device according to claim 7, further comprising a plurality of vertical channel transistors, Each of the plurality of vertical channel transistors comprises: a portion of an upper substrate; A bit line is disposed on the upper substrate and extends along a second direction intersecting the first direction; a pair of active patterns disposed on the bit lines; a back gate electrode, located between the pair of active patterns and extending along the first direction; as well as A pair of word lines is disposed outside the pair of active patterns and extends along the first direction.

11. The memory device according to claim 10, wherein: The power gating switch includes: a plurality of switch transistors electrically connected between the external ground voltage line and the internal ground voltage line, and Each of the plurality of switch transistors has the same structure as the plurality of vertical channel transistors, and the pair of active patterns of the plurality of switch transistors has the same conductivity type as the pair of active patterns of the plurality of vertical channel transistors.

12. The memory device according to claim 10, wherein: The memory cell array includes a shielding bit line located between a plurality of bit lines including the bit line and below the plurality of bit lines.

13. A storage device comprising: A core peripheral circuit structure including an internal power supply voltage line, an internal ground voltage line, a first bonding metal pad connected to the internal power supply voltage line, and a second bonding metal pad connected to the internal ground voltage line; as well as a cell array structure that overlaps the core peripheral circuit structure in a vertical direction and includes an external power supply voltage line for conducting an external power supply voltage applied from outside the memory device, an external ground voltage line for conducting an external ground voltage applied from outside the memory device, a third bonding metal pad in contact with the first bonding metal pad, and a fourth bonding metal pad in contact with the second bonding metal pad, The cell array structure includes: a memory cell array including a plurality of memory cells; and a power gating switch located in a region of the cell array structure different from the memory cell array. The power gating switch includes: a first power gating circuit connected between the external power supply voltage line and the third bonding metal pad; and a second power gating circuit connected between the external ground voltage line and the fourth bonding metal pad, and The first power gating circuit is configured to selectively provide the external power supply voltage to the internal power supply voltage line, and the second power gating circuit is configured to selectively provide the external ground voltage to the internal ground voltage line.

14. The memory device according to claim 13, wherein: The first power gating circuit includes: a plurality of first switch transistors electrically connected between the external power supply voltage line and the internal power supply voltage line, and The second power gating circuit includes: a plurality of second switch transistors electrically connected between the external ground voltage line and the internal ground voltage line.

15. The memory device according to claim 14, wherein: The first switch transistor comprises a PMOS transistor.

16. The memory device according to claim 14, wherein: The second switch transistor comprises an NMOS transistor.

17. The memory device according to claim 14, wherein: The plurality of first switching transistors are connected in parallel between the external power supply voltage line and the internal power supply voltage line, and the plurality of second switching transistors are connected in parallel between the external ground voltage line and the internal ground voltage line.

18. The memory device according to claim 14, further comprising a plurality of vertical channel transistors, Each of the plurality of vertical channel transistors comprises: a portion of an upper substrate; A bit line is disposed on the upper substrate and extends along a second direction intersecting the first direction; a pair of active patterns disposed on the bit lines; a back gate electrode, located between the pair of active patterns and extending along the first direction; as well as A pair of word lines is disposed outside the pair of active patterns and extends along the first direction.

19. The memory device according to claim 18, wherein: The memory cell array includes a shielding bit line located between a plurality of bit lines including the bit line and below the plurality of bit lines.

20. The memory device according to claim 13, wherein: The core peripheral circuit structure includes a core peripheral circuit different from the memory cell array, and The core peripheral circuit is connected to the internal power supply voltage line and the internal ground voltage line.

Images