Memory, operating method thereof, and memory system

Abstract

The invention provides a memory, an operation method of the memory and a memory system, relates to the technical field of memories, and aims to reduce programming interference. The memory comprises a memory cell array, a plurality of word lines, a first selection line and a peripheral circuit. Wherein the peripheral circuit is configured to apply a first voltage to the first word line and a second voltage to the second word line at a first stage of a recovery stage of the verification operation, the second voltage being greater than the first voltage. In a second stage of the recovery stage of the verification operation, a third voltage is applied to the first selection line. In a third stage of the recovery stage of the verify operation, a fourth voltage is applied to the first word line and a fifth voltage is applied to the second word line, the fifth voltage being greater than the fourth voltage. The memory is applied to a programming process.

Description

Technical Field

[0001] The present disclosure relates to the technical field of memories, and in particular, to a memory, an operation method of the memory, and a memory system. Background Art

[0002] A NAND flash memory is a memory that can retain the stored data for a long time without power supply, and has advantages such as low storage cost and high storage capacity. When performing a program operation, the NAND flash memory programs the storage units in units of pages to store data in the storage units. However, during the program operation of the NAND flash memory, program interference is likely to occur. Summary of the Invention

[0003] Embodiments of the present disclosure provide a memory, an operation method of the memory, and a memory system, aiming to reduce program interference.

[0004] To achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In a first aspect, an embodiment of the present disclosure provides a memory, which includes: a memory cell array including a plurality of memory strings, each memory string including a first select transistor, a plurality of memory cells, and a second select transistor connected in series in sequence; a plurality of word lines coupled to the plurality of memory cells; and a peripheral circuit coupled to the plurality of word lines and a first select line, and configured to: in a first stage of a recovery phase of a verify operation, apply a first voltage to a first word line and a second voltage to a second word line, where the second voltage is greater than the first voltage. In a second stage of the recovery phase of the verify operation, apply a third voltage to the first select line.

[0006] In the memory provided in the above embodiment of the present disclosure, in the first stage of the recovery phase of the verify operation, a first voltage is applied to the first word line and a second voltage is applied to the second word line. The memory cells coupled to the first word line have completed programming, and the memory cells coupled to the second word line are currently being programmed. It can be considered that the second word line is the selected word line. In the second stage of the recovery phase of the verify operation, a third voltage is applied to the first select line to turn on the first select transistor. When the voltage on the first word line drops, the residual electrons in the channel are drawn away through the turned-on first select transistor, thereby reducing the residual electrons in the channel and reducing program interference.

[0007] In some embodiments, the peripheral circuit is further configured to: in a third stage of the recovery phase of the verify operation, apply a fourth voltage to the first word line and a fifth voltage to the second word line, where the fifth voltage is greater than the fourth voltage.

[0008] In these embodiments, since a fourth voltage is applied to the first word line and a fifth voltage greater than the fourth voltage is applied to the second word line, the potential difference between adjacent memory cells during the programming process can be reduced, thereby reducing the coupling effect.

[0009] In some embodiments, the memory further includes a second selection line, and the second selection line is coupled to a second selection transistor. The peripheral circuit is further configured to: apply a fourth voltage to the second selection line in the second stage of the recovery phase of the verification operation.

[0010] In these embodiments, a fourth voltage is applied to the second selection line, and the fourth voltage can be a low potential, that is, the second selection transistor is in an off state.

[0011] In some embodiments, the peripheral circuit is further configured to: apply a sixth voltage to the first selection line after the second stage of the recovery phase of the verification operation, and the sixth voltage is less than the third voltage.

[0012] In these embodiments, after the second stage of the recovery phase of the verification operation, appropriately reducing the voltage on the first selection line can reduce the interference of the first selection transistor on programming.

[0013] In some embodiments, the peripheral circuit is further configured to: apply a fourth voltage to the first selection line in the fourth stage of the recovery phase of the verification operation.

[0014] In these embodiments, after the electrons remaining in the channel are drawn away, a fourth voltage can be applied to the first selection line, that is, the first selection transistor is turned off.

[0015] In some embodiments, the peripheral circuit is further configured to: apply a programming voltage to the second word line and a conduction voltage to the first word line in the fifth stage of the recovery phase of the verification operation.

[0016] In some embodiments, the peripheral circuit is further configured to: apply a fourth voltage to the third word line in the first stage of the recovery phase of the verification operation, where the third word line is located between the second word line and the first selection line. That is, a fourth voltage can be applied to the unprogrammed memory cell, and the unprogrammed memory cell can be made conductive.

[0017] In some embodiments, the memory cell coupled to the first word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell.

[0018] In some embodiments, the peripheral circuit is further configured to: apply a seventh voltage to the source line in the second stage of the recovery phase of the verification operation, where the first selection line is located between the third word line and the source line.

[0019] In these embodiments, if the top-down programming method is adopted, a seventh voltage can be applied to the source line to attract the residual electrons in the channel to the source line, so as to reduce the residual electrons in the channel and reduce programming interference.

[0020] In some embodiments, the peripheral circuit is further configured to: apply an eighth voltage to the bit line in the second stage of the recovery phase of the verification operation, wherein the first selection line is located between the third word line and the bit line.

[0021] In these embodiments, if the bottom-up programming method is adopted, an eighth voltage can be applied to the bit line to attract the residual electrons in the channel to the bit line, so as to reduce the residual electrons in the channel and reduce programming interference.

[0022] In some embodiments, the peripheral circuit is further configured to: apply a second voltage to the fourth word line in the first stage of the recovery phase of the verification operation, wherein the fourth word line is located between the second word line and the first word line.

[0023] In these embodiments, applying a second voltage to the fourth word line adjacent to the selected second word line can reduce the potential difference of the channel.

[0024] In some embodiments, the peripheral circuit is further configured to: apply a fourth voltage to the fifth word line in the first stage of the recovery phase of the verification operation, wherein the fifth word line is located between the first word line and the second selection line.

[0025] In some embodiments, the peripheral circuit is further configured to: apply a ninth voltage to the first word line and the second word line in the first stage of the recovery phase of the last verification operation of the memory string.

[0026] In some embodiments, the second voltage is less than the turn-on voltage.

[0027] In a second aspect, an embodiment of the present disclosure provides an operation method of a memory, the method includes: applying a first voltage to the first word line and applying a second voltage to the second word line in the first stage of the recovery phase of the verification operation, the second voltage being greater than the first voltage. Applying a third voltage to the first selection line in the second stage of the recovery phase of the verification operation.

[0028] In some embodiments, the method further includes: applying a fourth voltage to the first word line and applying a fifth voltage to the second word line in the third stage of the recovery phase of the verification operation, the fifth voltage being greater than the fourth voltage.

[0029] In some embodiments, the method further includes: applying a fourth voltage to the second selection line in the second stage of the recovery phase of the verification operation.

[0030] In some embodiments, the method further includes: after the second stage of the recovery phase of the verification operation, applying a sixth voltage to the first selection line, where the sixth voltage is less than the third voltage.

[0031] In some embodiments, the method further includes: in the fourth stage of the recovery phase of the verification operation, applying a fourth voltage to the first selection line.

[0032] In some embodiments, the method further includes: in the fifth stage of the recovery phase of the verification operation, applying a programming voltage to the second word line and applying a conduction voltage to the first word line.

[0033] In some embodiments, the method further includes: in the first stage of the recovery phase of the verification operation, applying a fourth voltage to the third word line, where the third word line is located between the second word line and the first selection line.

[0034] In some embodiments, the memory cell coupled to the first word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell.

[0035] In some embodiments, the method further includes: in the second stage of the recovery phase of the verification operation, applying a seventh voltage to the source line, where the first selection line is located between the third word line and the source line.

[0036] In some embodiments, the method further includes: in the second stage of the recovery phase of the verification operation, applying an eighth voltage to the bit line, where the first selection line is located between the third word line and the bit line.

[0037] In some embodiments, the method further includes: in the first stage of the recovery phase of the verification operation, applying a second voltage to the fourth word line, where the fourth word line is located between the second word line and the first word line.

[0038] In some embodiments, the method further includes: in the first stage of the recovery phase of the verification operation, applying a fourth voltage to the fifth word line, where the fifth word line is located between the first word line and the second selection line.

[0039] In some embodiments, the method further includes: during the last verification operation of the memory string, in the first stage of the recovery phase of the last verification operation, applying a ninth voltage to the first word line and the second word line.

[0040] In some embodiments, the second voltage is less than the conduction voltage.

[0041] The beneficial effects of the second aspect can be referred to the description of the first aspect.

[0042] In a third aspect, a memory system is provided. The memory system includes the memory of the first aspect, and a memory controller coupled to the memory and configured to control the memory.

[0043] In a fourth aspect, an electronic device is provided. The electronic device includes the memory system as described above.

[0044] It can be understood that for the memory, the operation method of the memory, the memory system, and the electronic device provided by the above embodiments of the present disclosure, the beneficial effects that can be achieved can refer to the beneficial effects of the memory in the foregoing text, and will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] To more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual sizes of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present disclosure.

[0046] Figure 1 FIG. 101 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure;

[0047] Figure 2 FIG. is a schematic diagram of a hot carrier injection effect provided by an embodiment of the present disclosure;

[0048] Figure 3 FIG. is a timing diagram of an application of an unselected memory string boosting balance method provided by an embodiment of the present disclosure;

[0049] Figure 4 FIG. is a timing diagram of a verification operation and a programming operation provided by an embodiment of the present disclosure;

[0050] Figure 5 FIG. is another timing diagram of a verification operation and a programming operation provided by an embodiment of the present disclosure;

[0051] Figure 6 FIG. is yet another timing diagram of a verification operation and a programming operation provided by an embodiment of the present disclosure;

[0052] Figure 7 FIG. is a flowchart of an operation method of a memory provided by an embodiment of the present disclosure;

[0053] Figure 8 FIG. is a schematic structural diagram of an exemplary system S1 having a memory system 10 provided by an embodiment of the present disclosure;

[0054] Figure 9Schematic diagram of a memory card provided by an embodiment of the present disclosure;

[0055] Figure 10 Schematic diagram of another memory card provided by an embodiment of the present disclosure. Detailed implementation manners

[0056] Next, in combination with the accompanying drawings, the technical solutions in some embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0057] In the description of the present disclosure, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present disclosure.

[0058] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0059] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more. "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C. "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0060] The use of "configured to" or "adapted to" in this document means open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0061] The term "three-dimensional memory" refers to a semiconductor device formed by a string of memory cell transistors (referred to herein as a "memory cell string" or a "memory string", such as a NAND memory cell string) that are arranged in an array on a main surface of a substrate or a source layer and extend in a direction perpendicular to the substrate or the source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface (i.e., the lateral surface) of the substrate or the source layer.

[0062] As Figure 1 shown, Figure 1 FIG. 101 is a schematic structural diagram of a memory 101 provided by an embodiment of the present disclosure. The memory 101 includes one or more memory blocks 1011. Each memory block 1011 includes a plurality of memory strings 20. Each memory string 20 includes a top select gate (TSG) 31, a plurality of memory cells 201, and a bottom select gate (BSG) 32 that are connected in series. The drain terminal of the top select gate 31 can be connected to a bit line 41, and the source terminal of the bottom select gate 32 can be connected to an array common source (ACS). The array common source can be shared by the memory strings 20 in the entire memory block 1011 and is also referred to as a source line (SL) 42. Each memory cell 201 can be connected to a corresponding word line (WL) 43, the top select gate 31 can be connected to an upper select line 44, and the bottom select gate 32 can be connected to a lower select line 45.

[0063] In some embodiments, the memory 101 further includes a peripheral circuit 1012, which can be connected to the word line 43, bit line 41, source line 42, upper selection line 44, lower selection line 45, etc. The peripheral circuit 1012 can include a page buffer / sense amplifier 10121, a row decoder / word line driver 10122, a column decoder / bit line driver 10123, and a peripheral control circuit 10124. The memory block 1011 can be coupled to the row decoder / word line driver 10122 via the word line 43, top selection transistor 31, and bottom selection transistor 32. The memory block 1011 can be coupled to the page buffer / sense amplifier 10121 via the bit line 41. The row decoder / word line driver 10122 can select one memory block among the memory blocks 1011 on the memory 101 in response to an X-path control signal provided by the peripheral control circuit 10124. The row decoder / word line driver 10122 can transfer the voltage provided by the voltage generator 90 to the word line 43 according to the X-path control signal. During read and program operations, the row decoder / word line driver 10122 can transfer the read voltage Vread and program voltage Vpgm to the selected word line 43 according to the X-path control signal received from the peripheral control circuit 10124, and transfer the pass voltage Vpass to the non-selected word lines.

[0064] The column decoder / bit line driver 10123 can transfer the inhibit voltage Vinhibit provided by the voltage generator 90 to the non-selected bit lines according to the Y-path control signal received from the peripheral control circuit 10124, and connect the selected bit line 41 to ground. That is, the column decoder / bit line driver 10123 can be configured to select or deselect one or more memory strings 20 according to the Y-path control signal from the peripheral control circuit 10124. The page buffer / sense amplifier 10121 can be configured to read data from and program (write) data to the memory block 1011 according to the Y-path control signal from the peripheral control circuit 10124. For example, the page buffer / sense amplifier 10121 can store a page of data to be programmed into a memory page. In another example, the page buffer / sense amplifier 10121 can perform a verification operation to ensure that the data has been correctly programmed into each memory cell 201. In yet another example, during a read operation, the page buffer / sense amplifier 10121 can sense the current flowing through the bit line 41 that reflects the logical state (i.e., data) of the memory cell 201, and the amplification factor for amplifying the small signal to a measurable signal.

[0065] The input / output buffer 91 can transfer I / O data from / to the page buffer / sense amplifier 10121, and transfer the address ADDR signal or the command CMD signal to the peripheral control circuit 10124. In some embodiments, the input / output buffer 91 can be used as an interface between the memory controller and the memory 101.

[0066] The peripheral control circuit 10124 can control the page buffer / sense amplifier 10121 and the row decoder / word line driver 10122 in response to the command CMD transferred by the input / output buffer 91. During a programming operation, the peripheral control circuit 10124 can control the row decoder / word line driver 10122 and the page buffer / sense amplifier 10121 to program the selected memory cell 201. During a read operation, the peripheral control circuit 10124 can control the row decoder / word line driver 10122 and the page buffer / sense amplifier 10121 to read the selected memory cell 201. The X-path control signal includes the row address X-ADDR, and the Y-path control signal includes the column address Y-ADDR, which can be used to locate the selected memory cell 201 in the memory block 1011. The row address X-ADDR can include a page index, a block index, and a plane index to respectively identify the memory page and the memory block 1011. The column address Y-ADDR can identify a byte or a word in the data of the memory page.

[0067] In some embodiments, the peripheral control circuit 10124 can include one or more control logic units. Each control logic unit described herein can be a software module and / or a firmware module running on a processor, such as a microcontroller unit (MCU) as part of the peripheral control circuit 10124, or a hardware module of a finite-state machine (FSM), such as an integrated circuit (IC), such as an application-specific IC (ASIC), a field-programmable gate array (FPGA), etc., or a combination of a software module, a firmware module, and a hardware module.

[0068] The voltage generator 90 can generate voltages provided to the word line 43 and the bit line 41 under the control of the peripheral control circuit 10124. The voltages generated by the voltage generator 90 include a read voltage Vread, a programming voltage Vpgm, a pass voltage Vpass, an inhibit voltage Vinhibit, etc.

[0069] In some embodiments, the memory 101 can be formed based on floating gate technology. In some embodiments, the memory 101 can be formed based on charge trapping technology. The charge trapping-based memory 101 can provide high storage density and high intrinsic reliability. Storing data or a logic state (e.g., the threshold voltage Vth of the memory cell 201) depends on the amount of charge trapped in the storage layer. In some embodiments, the memory 101 can be a three-dimensional (3D) memory device, where the memory cells 201 can be vertically stacked on top of each other.

[0070] Currently, after each program pulse and verify pulse in the programming operation ends, the voltages on all word lines recover to VDD, and the voltages on the top select transistor and the bottom select transistor recover to VSS.

[0071] As Figure 2 shown, Figure 2 FIG. is a schematic diagram of the hot carrier injection effect provided by an embodiment of the present disclosure. Among them, a voltage of 2V is applied to the upper select line coupled to the top select transistor, a voltage of -2V is applied to the word line coupled to the redundant layer (dummy, DMY), a voltage of -2V is applied to the unselected word lines far from the selected word line, a voltage of 3V is applied to the unselected word lines close to the selected word line, a voltage of 3V is applied to the selected word line (select word line, sel wl), and a voltage of 2.5V is applied to the lower select line coupled to the bottom select transistor. When the verify operation ends and the word line is recovering to VDD, due to the relatively high threshold voltage of the programmed memory cells in the selected memory string, this part of the programmed memory cells will turn off in advance. At this time, the potential of the channel will be down-coupled from 0V to a negative voltage, such as -3V. At this time, if the potential of the down-coupled channel is not reset, the subsequent programming operation will generate a hot carrier injection (HCI) effect when the potential of the channel rises, and residual electrons will appear in the channel, resulting in program disturb.

[0072] Currently, in order to reduce the impact of the recovery stage of the verify operation on the programming operation, an unselect string boosting enhancement (USBE) method has been proposed. As Figure 3 shown, Figure 3 FIG. is a timing diagram of applying the unselect string boosting enhancement method provided by an embodiment of the present application. Among them, Figure 3One of the verification operations and programming operations is shown, where Figure 3 The dashed part in [it] is the timing diagram of the application without selecting the storage string boosting balance method. Specifically, in the pre-programming stage of the programming operation, the voltage of the unselected word line (unsel wl) rises from VDD to the first voltage ( Figure 3 denoted as V11 in [it]), then drops to VDD, and the voltage of the selected word line also rises from VDD to V11 and then drops to VDD. In addition, the voltage of the selection gate line of the top selection transistor is VSS, that is, the top selection transistor is in the off state, and the voltage of the selection gate line of the bottom selection transistor rises from VSS to the second voltage ( Figure 3 denoted as V21 in [it]), that is, the bottom selection transistor is in the on state. In addition, the voltage of the source line is the third voltage ( Figure 3 denoted as V31 in [it]), that is, the source line is at a high potential, and at this time all the memory cells are turned on, and the electrons remaining in the channel are attracted to the source line, which can eliminate the electrons remaining in the channel and reduce programming interference. However, the method of not selecting the storage string boosting balance requires a relatively long time in the programming operation, such as more than 10 us, which has a greater impact on programming.

[0073] An embodiment of the present application provides a memory. In the first stage after the end of the application of the last verification voltage (applied to the selected word line) in the verification operation (for example, in the first stage of the recovery stage of the verification operation), a first voltage and a second voltage are respectively applied to the word line coupled to the memory cell that has been programmed in the storage string and the selected word line, and the second voltage is greater than the first voltage. The voltage on the word line coupled to the memory cell that has been programmed in the storage string starts to drop from the conduction voltage to the first voltage, and the voltage on the selected word line starts to drop from the last verification voltage of the verification operation to the second voltage. The voltages on the word line coupled to the memory cell that has been programmed in the storage string and the selected word line do not directly return to VDD.

[0074] In addition, for the memory provided in the embodiments of the present application, in the second stage after the application of the last verification voltage (applied to the selected word line) in the verification operation ends (for example, in the second stage of the recovery stage of the verification operation), a third voltage is applied to the first selection line coupled to the first selection transistor. The third voltage is greater than the threshold voltage of the first selection transistor, so that the first selection transistor is in the on state, and VSS is applied to the second selection line coupled to the second selection transistor, so that the second selection transistor is in the off state. Since the second selection transistor starts to turn off in the second stage, which is later than the turn-off time of the memory cells coupled to the first word line and the second word line, the electric potential in the channel can be better reset. In addition, in the second stage, the voltage on the first selection line starts to decrease, which can reduce the programming interference caused by the first selection transistor. Among them, if the top-down programming method is adopted, the first selection transistor is the bottom selection transistor, and the second selection transistor is the top selection transistor. If the bottom-up programming method is adopted, the first selection transistor is the top selection transistor, and the second selection transistor is the bottom selection transistor.

[0075] In some embodiments, the memory includes a memory cell array, a plurality of word lines, a first selection line, and a peripheral circuit. Among them, in the first stage of the recovery stage of the verification operation, a first voltage is applied to the first word line and a second voltage is applied to the second word line. The memory cells coupled to the first word line have completed programming, and the memory cells coupled to the second word line are currently being programmed. It can be considered that the second word line is the selected word line. In the second stage of the recovery stage of the verification operation, a third voltage is applied to the first selection line to turn on the first selection transistor. When the voltage on the first word line drops, the remaining electrons in the channel can be drawn away through the turned-on first selection transistor, thereby reducing the remaining electrons in the channel and reducing programming interference.

[0076] Applied to the above-mentioned memory 101, the timing diagrams of the verification operation and the programming operation performed on the memory 101 provided in the embodiments of the present disclosure will be introduced below. Corresponding to the top-down programming method, as Figure 4 shown, Figure 4 is a timing diagram of a verification operation and a programming operation provided by an embodiment of the present disclosure. Figure 4 The timing diagrams of the bit line, the second selection line, the fifth word line, the first word line, the fourth word line, the second word line, the third word line, the first selection line, and the source line are shown.

[0077] Among them, in the first stage of the recovery stage of the verification operation, a first voltage is applied to the first word line and a second voltage is applied to the second word line, and the second voltage is greater than the first voltage.

[0078] Exemplarily, the verification operation may include a pre-conduction stage before verification, a verification stage, and a recovery stage. Additionally, the programming operation may include a pre-conduction stage before programming and a programming stage. Among them, after the recovery stage of the verification operation is the pre-conduction stage before programming of the programming operation. Embodiments of the present disclosure adjust the timing of the peripheral circuits in the recovery stage of the verification operation and the pre-conduction stage before programming of the programming operation to improve the programming interference caused by the HCI effect.

[0079] Exemplarily, the first stage of the recovery stage of the verification operation, i.e., Figure 4 the stage starting from the moment t1 in, the first word line may be an unselected word line, that is, the memory cell coupled to the first word line may be a programmed memory cell. The second word line may be a selected word line, that is, the memory performs a programming operation and a verification operation on the memory cell coupled to the second word line. Among them, the memory cell coupled to the first word line can be understood as the memory cell in the adjacent area of the memory cell coupled to the second word line. When the voltage on the first word line drops, due to the relatively high threshold voltage of the memory cell coupled to the first word line, the memory cell coupled to the first word line may exhibit the HCI effect, and residual electrons will appear in the channel, which will cause programming interference.

[0080] Exemplarily, starting from the moment t1, a first voltage ( Figure 4 denoted as V1 in ) is applied to the first word line, and the voltage on the first word line drops from the conduction voltage in the verification stage to the first voltage. Starting from the moment t1, a second voltage ( Figure 4 denoted as V2 in ) is also applied to the second word line, and the voltage on the second word line drops from the verification voltage in the verification stage to the second voltage. In a possible example, the value range of the first voltage may be 2V to 4V, and the value range of the second voltage may be 2V to 5V. Among them, when determining the values of the first voltage and the second voltage, the condition that the second voltage is greater than the first voltage should be satisfied.

[0081] Among them, the second voltage is less than the conduction voltage. That is, starting from the moment t1, the voltage on the first word line drops from the conduction voltage to the second voltage.

[0082] Among them, in the second stage of the recovery stage of the verification operation, a third voltage is applied to the first selection line.

[0083] Exemplarily, the second stage of the recovery stage of the verification operation, i.e., Figure 4 the stage starting from the moment t2 in, starting from the moment t2, a third voltage ( Figure 4 denoted as V3 in ) is applied to the first selection line, and the voltage on the first selection line rises from VSS to the third voltage. The third voltage may be greater than the threshold voltage of the first selection transistor, that is, the first selection transistor is in the on state.

[0084] In addition, in the second stage, the voltage on the first word line stabilizes at the first voltage, and the voltage on the second word line stabilizes at the second voltage.

[0085] Thus, since the first selection transistor is in the conducting state during the first and second stages of the recovery phase of the verification operation, the electrons remaining in the channel can be attracted to the source line, thereby reducing the interference of the remaining electrons on programming.

[0086] Optionally, referring to Figure 4 continuously, in the third stage of the recovery phase of the verification operation, a fourth voltage is applied to the first word line, and a fifth voltage is applied to the second word line, and the fifth voltage is greater than the fourth voltage.

[0087] Exemplarily, the third stage of the recovery phase of the verification operation is the stage starting from the moment t3 in Figure 4 . Starting from the moment t3, a fourth voltage ( Figure 4 denoted as V4 in Figure 4 ) is applied to the first word line, and the voltage on the first word line drops from the first voltage to the fourth voltage, where the fourth voltage can be VSS. And a fifth voltage ( Figure 4 denoted as V5 in

[0088] ) is applied to the second word line, and the voltage on the second word line drops from the second voltage to the fifth voltage. Since the fifth voltage is greater than the fourth voltage, the potential difference of the memory cell coupled to the second word line can be reduced when a programming voltage is applied to the second word line, so as to reduce the potential difference between adjacent memory cells and reduce the coupling effect.

[0088] Optionally, referring to Figure 4 continuously, the memory 101 further includes a second selection line, and the second selection line is coupled to the second selection transistor. The peripheral circuit is further configured to: apply a fourth voltage to the second selection line during the second stage of the recovery phase of the verification operation.

[0089] Exemplarily, if the memory 101 is programmed from top to bottom, the second selection transistor is the top selection transistor. If the memory 101 is programmed from bottom to top, the second selection transistor is the bottom selection transistor.

[0090] Exemplarily, starting from the moment t2, a fourth voltage is applied to the second selection line, that is, VSS is applied to the second selection line, and the voltage on the second selection line drops to VSS. At this time, the second selection transistor is in the off state. Since the second selection transistor starts to turn off at the moment t2, which is Δt = t2 - t1 later than the turn-off time of the memory cell coupled to the first word line or the second word line, the potential of the channel can be better reset.

[0091] Optionally, referring to Figure 4 continuously, the peripheral circuit is further configured to: apply a sixth voltage to the first selection line after the second stage of the recovery phase of the verification operation, and the sixth voltage is less than the third voltage.

[0092] Exemplarily, after time t2 and before time t3, a sixth voltage ( Figure 4 denoted as V6 in is applied to the first selection line, that is, the voltage on the first selection line drops from the third voltage to the sixth voltage. Since the sixth voltage is less than the third voltage and the sixth voltage is greater than the turn-on voltage of the first selection transistor, the first selection transistor remains in the on state after time t2 and before time t3. In a possible example, the sixth voltage may be 4V.

[0093] Thus, after time t2 and before time t3, reducing the voltage on the first selection line can reduce the interference of the first selection transistor to programming.

[0094] Optionally, continuing to refer to Figure 4 , the peripheral circuit is further configured to apply a fourth voltage to the first selection line in the fourth stage of the recovery phase of the verification operation.

[0095] Exemplarily, the fourth stage of the recovery phase of the verification operation is the stage starting from time t4 in Figure 4 . Starting from time t4, a fourth voltage is applied to the first selection line, and the voltage on the first selection line drops from the sixth voltage to the fourth voltage, that is, VSS is applied to the first selection line, and at this time the first selection transistor is in the off state.

[0096] In addition, in the fourth stage, the voltage on the first word line is stabilized at the fourth voltage, the voltage on the second word line is stabilized at the fifth voltage, and the voltage on the second selection line is stabilized at the fourth voltage.

[0097] Optionally, continuing to refer to Figure 4 , the peripheral circuit is further configured to apply a programming voltage (Vprog) to the second word line and a pass voltage (Vpass) to the first word line in the fifth stage of the recovery phase of the verification operation.

[0098] Exemplarily, the fifth stage of the recovery phase of the verification operation is Figure 4In the stage starting from time t5, starting from time t5, a programming voltage is applied to the second word line, and the voltage on the second word line rises from the fifth voltage to the programming voltage, so that a large potential difference is formed between the selected memory cell and the channel potential, enabling electrons to tunnel and inject into the charge trapping layer. Among them, the second word line can be programmed by an increment step programming pulse (ISPP), that is, the next programming voltage applied to the second word line has a certain increment based on the previous programming voltage. At time t5, a conduction voltage is applied to the first word line, and the voltage on the first word line rises from the fourth voltage to the conduction voltage to turn on the unselected memory cells.

[0099] Thus, after time t5, the memory 101 is in the programming stage of the programming operation, that is, the first stage to the fifth stage of the recovery stage of the verification operation, which may include the recovery stage of the verification operation and the pre-conduction stage before programming of the programming operation.

[0100] Optionally, continue to refer to Figure 4 , in the first stage of the recovery stage of the verification operation, a fourth voltage is applied to the third word line, where the third word line is located between the second word line and the first selection line. Among them, the memory cells coupled to the first word line are the memory cells with programming completed, and the memory cells coupled to the third word line are the unprogrammed memory cells.

[0101] Exemplarily, for the top-down programming method, at this time, the memory cells coupled to the third word line are unprogrammed memory cells. At time t1, a fourth voltage, that is, VSS, is applied to the third word line, and the voltage on the third word line drops from the conduction voltage to the fourth voltage. At this time, the memory cells coupled to the third word line are in the conduction state, and the remaining electrons in the channel can flow through the memory cells coupled to the third word line and the first selection transistor to the source line, which can reduce the remaining electrons in the channel and reduce programming interference.

[0102] In addition, in the second stage to the fourth stage, the voltage on the third word line is stabilized at the fourth voltage.

[0103] Optionally, continue to refer to Figure 4 , in the second stage of the recovery stage of the verification operation, a seventh voltage is applied to the source line, where the first selection is located between the third word line and the source line.

[0104] Exemplarily, if the top-down programming method is adopted, starting from time t2, a seventh voltage ( Figure 4In the figure (represented by V7), the voltage on the source line rises from VSS to the seventh voltage. In the second to fourth stages, the voltage on the source line stabilizes at the seventh voltage. In a possible example, the value range of the seventh voltage can be from 0.4V to 1V. Thus, starting from time t2, the source line is at a high potential, and the electrons remaining in the channel will flow to the source line, which can reduce the electrons remaining in the channel and reduce programming interference.

[0105] Optionally, continuing to refer to Figure 4 , in the first stage of the recovery phase of the verification operation, a second voltage is applied to the fourth word line, where the fourth word line is located between the second word line and the first word line.

[0106] Exemplarily, the memory cell coupled to the fourth word line is the closest to the memory cell coupled to the second word line. Thus, in the first stage, a second voltage can be applied to the fourth word line, and the voltage on the fourth word line drops from the conduction voltage to the second voltage, which can reduce the potential difference in the channel. Additionally, in the second stage, the voltage on the fourth word line stabilizes at the second voltage, in the third stage, the voltage on the fourth word line drops from the second voltage to the fourth voltage, and in the fourth stage, the voltage on the fourth word line stabilizes at the fourth voltage.

[0107] Optionally, continuing to refer to Figure 4 , in the first stage of the recovery phase of the verification operation, a fourth voltage is applied to the fifth word line, where the fifth word line is located between the first word line and the second selection line.

[0108] Exemplarily, the memory cell coupled to the fifth word line is relatively far from the memory cell coupled to the second word line. It can be understood that the memory cell coupled to the fifth word line has less influence on the memory cell being programmed. Thus, a fourth voltage can be applied to the fifth word line, and the voltage on the fifth word line drops from the conduction voltage to the fourth voltage. In the second, third, and fourth stages, the voltage on the fifth word line stabilizes at the fourth voltage.

[0109] Exemplarily, if the top-down programming method is adopted, from the first stage to the fifth stage of the recovery phase of the verification operation, a fourth voltage can be applied to the bit line to make the bit line at a low potential and the source line at a high potential. Then, the electrons remaining in the channel will flow to the source line, which can reduce the electrons remaining in the channel and reduce programming interference.

[0110] If the bottom-up programming method is adopted, as Figure 5 shown, Figure 5 is another timing diagram of the verification operation and the programming operation provided by the embodiments of the present disclosure. Among them, Figure 5 the timing diagrams of the bit line, the first selection line, the third word line, the second word line, the fourth word line, the first word line, the fifth word line, the second selection line, and the source line are respectively shown.

[0111] Optionally, in the second stage of the recovery phase of the verification operation, an eighth voltage is applied to the bit line, where the first selection line is located between the third word line and the bit line.

[0112] Exemplarily, if the bottom-up programming method is adopted, starting from time t2, an eighth voltage ( Figure 5 denoted as V8 in ) is applied to the bit line. In a possible example, the value range of the eighth voltage can be from 0.4V to 1V. Thus, starting from time t2, the bit line is at a high potential, and the remaining electrons in the channel will flow to the bit line, which can reduce the remaining electrons in the channel and reduce programming interference.

[0113] Exemplarily, if the bottom-up programming method is adopted, a fourth voltage can be applied to the source line from the first stage to the fifth stage of the recovery phase of the verification operation.

[0114] In some embodiments, along the programming direction, all word lines can be numbered starting from 0. For example, WL0 to WLx, where x is an integer greater than 0. Among them, the word line WLn is the selected word line, and the storage units coupled to the word lines WL0 to WLn - 1 have been programmed, and the storage units coupled to the word lines WLn + 1 to WLx have not been programmed yet. In the recovery phase of the verification operation, the word lines can be grouped, and different voltages can be applied to different groups of word lines. For example, when grouping the word lines, it can include the first group of word lines WL0 - WLm, the second group of word lines WLm + 1 - WLn - y, the third group of word lines WLn - y + 1 - WLn - 1, the selected word line WLn, and the fourth group of word lines WLn + 1 - WLx. In the recovery phase of the verification operation, the voltage applied to each word line in the first group of word lines WL0 - WLm can be the same as that of the fifth word line in Figure 4 or the same voltage as the fifth word line in Figure 5 The voltage applied to each word line in the second group of word lines WLm + 1 - WLn - y can be the same as that of the first word line in Figure 4 or the same voltage as the first word line in Figure 5 The voltage applied to each word line in the third group of word lines WLn - y + 1 - WLn - 1 can be the same as that of the fourth word line in Figure 4 or the same voltage as the fourth word line in Figure 5 The voltage applied to each word line in the fourth group of word lines WLn + 1 - WLx can be the same as that of the third word line in Figure 4 or the same voltage as the third word line in Figure 5 In some embodiments, y can be 5, and m can be set according to actual needs.

[0115] In some embodiments, please refer to Figure 4 or Figure 5, all word lines can be numbered in the direction from top (top selection transistor) to bottom (bottom selection transistor). For example, WL0 to WLx, where WL0 is the top WL, WLx is the bottom WL, and WLn is the selected word line. Please refer to Figure 4 , when programming the word lines in a top-down manner and grouping the word lines, it can include the first group of word lines WL0 - WLm, the second group of word lines WLm+1 - WLn-y, the third group of word lines WLn-y+1 - WLn-1, the selected word line WLn, and the fourth group of word lines WLn+1 - WLx. During the recovery stage of the verification operation, the voltage applied to each word line in the first group of word lines WL0 - WLm can be the same as the voltage of the fifth word line, the voltage applied to each word line in the second group of word lines WLm+1 - WLn-y can be the same as the voltage of the first word line, the voltage applied to each word line in the third group of word lines WLn-y+1 - WLn-1 can be the same as the voltage of the fourth word line, and the voltage applied to each word line in the fourth group of word lines WLn+1 - WLx can be the same as the voltage of the third word line. In some embodiments, y can be 5, and m can be set according to actual needs.

[0116] Please refer to Figure 5 , when programming the word lines in a bottom-up manner and grouping the word lines, it can include the first group of word lines WL0 - WLn-1, the selected word line WLn, the second group of word lines WLn+1 - WLn+y-1, the third group of word lines WLn+y - WLm-1, and the fourth group of word lines WLm - WLx. During the recovery stage of the verification operation, the voltage applied to each word line in the first group of word lines WL0 - WLn-1 can be the same as the voltage of the third word line, the voltage applied to each word line in the second group of word lines WLn+1 - WLn+y-1 can be the same as the voltage of the fourth word line, the voltage applied to each word line in the third group of word lines WLn+y - WLm-1 can be the same as the voltage of the first word line, and the voltage applied to each word line in the fourth group of word lines WLm - WLx can be the same as the voltage of the fifth word line. In some embodiments, y can be 5, and m can be set according to actual needs.

[0117] Optionally, as Figure 6 shown, Figure 6 is another timing diagram of the verification operation and the programming operation provided by the embodiments of the present disclosure. Figure 6 shows the timing diagrams of the bit line, the second selection line, the second word line, the first word line, the first selection line, and the source line during the verification operation, the programming operation, and the last verification operation. Among them, during the last verification operation of the memory string, in the first stage of the recovery stage of the last verification operation, a ninth voltage is applied to the first word line and the second word line.

[0118] Exemplarily, the ninth voltage ( Figure 6It may be VDD (represented by V9 in the figure). That is, during the last verification operation, the voltages on the first word line and the second word line are restored to VDD. During consecutive programming and verification operations, during the restoration phase of non-last verification operations, the voltage on the first word line drops from the verification voltage to the first voltage ( Figure 6 represented by V1 in the figure), and then drops to the fourth voltage ( Figure 6 represented by V4). The voltage on the second word line drops from the conduction voltage to the second voltage ( Figure 6 represented by V2 in the figure), and then drops to the fifth voltage ( Figure 6 represented by V5). During the restoration phase of the last verification operation, the voltages on the first word line and the second word line drop to the ninth voltage.

[0119] Applied to the above-mentioned memory, a method for operating a memory provided by an embodiment of the present disclosure will be introduced below. As Figure 7 shown, Figure 7 is a flowchart of a method for operating a memory provided by an embodiment of the present disclosure. The method includes the following processes:

[0120] S701. In the first stage of the restoration phase of the verification operation, apply a first voltage to the first word line and a second voltage to the second word line, where the second voltage is greater than the first voltage.

[0121] Exemplarily, the first word line may be an unselected word line, the second word line may be a selected word line, and the memory cell coupled to the first word line may have completed programming.

[0122] S702. In the second stage of the restoration phase of the verification operation, apply a third voltage to the first selection line.

[0123] Exemplarily, the third voltage may be greater than the threshold voltage of the first selection transistor, that is, the first selection transistor is in a conducting state. Thus, since the first selection transistor is in a conducting state during the first and second stages of the restoration phase of the verification operation, the electrons remaining in the channel can be attracted to the source line, thereby reducing the interference of the remaining electrons on programming.

[0124] Optionally, the method may further include: in the third stage of the restoration phase of the verification operation, apply a fourth voltage to the first word line and a fifth voltage to the second word line, where the fifth voltage is greater than the fourth voltage.

[0125] Optionally, the method may further include: in the second stage of the restoration phase of the verification operation, apply a fourth voltage to the second selection line.

[0126] Optionally, the method may further include: after the second stage of the restoration phase of the verification operation, apply a sixth voltage to the first selection line, where the sixth voltage is less than the third voltage.

[0127] Optionally, the method may further include: applying a fourth voltage to a first selection line in a fourth stage of a recovery phase of a verification operation.

[0128] Optionally, the method may further include: applying a programming voltage to a second word line and applying a conducting voltage to a first word line in a fifth stage of a recovery phase of a verification operation.

[0129] Optionally, the method may further include: applying a fourth voltage to a third word line in a first stage of a recovery phase of a verification operation, where the third word line is located between the second word line and the first selection line.

[0130] Optionally, the method may further include: applying a seventh voltage to a source line in a second stage of a recovery phase of a verification operation, where the first selection line is located between the third word line and the source line.

[0131] Optionally, the method may further include: applying an eighth voltage to a bit line in a second stage of a recovery phase of a verification operation, where the first selection line is located between the third word line and the bit line.

[0132] Optionally, the method may further include: applying a second voltage to a fourth word line in a first stage of a recovery phase of a verification operation, where the fourth word line is located between the second word line and the first word line.

[0133] Optionally, the method may further include: applying a fourth voltage to a fifth word line in a first stage of a recovery phase of a verification operation, where the fifth word line is located between the first word line and the second selection line.

[0134] Optionally, the method may further include: applying a ninth voltage to the first word line and the second word line in a first stage of a recovery phase of a last verification operation of a memory string during the last verification operation.

[0135] Embodiments of the present disclosure further provide a memory system 10, as Figure 8 shown Figure 8Schematic diagram of an exemplary system S1 having a memory system 10 provided by an embodiment of the present disclosure. The system S1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. The memory system 10 (which may also be referred to as a NAND memory system) includes a memory 101 and a memory controller 102. The memory system 10 may communicate with a host 50 through the memory controller 102, wherein the memory controller 102 may be coupled to the memory 101 via a memory channel 60. In some embodiments, the memory 101 in the present disclosure may be a three-dimensional non-volatile memory, for example, it may be a NAND flash memory, and the NAND flash memory may also be simply referred to as a flash memory or NAND. Of course, the memory 101 in the present disclosure may also be other memories. The memory system 10 may have more than one memory 101, and each memory 101 may be managed by the memory controller 102.

[0136] In some embodiments, the host 50 may be a processor of an electronic device, for example, a central processing unit (CPU), a system-on-chip (SoC), or an application processor (AP). The host 50 may send data to be stored at the memory system 10, or read data stored at the memory system 10.

[0137] The memory controller 102 may process input / output (I / O) requests received from the host 50, ensure data integrity and effective storage, and may also manage the memory 101. The memory channel 60 may provide data via a data bus and control the communication between the memory controller 102 and the memory 101.

[0138] Continuing to refer to Figure 8 , the memory 101 may be a memory chip (package), a memory die, or any part of a memory die, and may include a plurality of memory blocks 1011. The size of the memory block 1011 may be megabytes (MB), and the memory block 1011 may be the smallest unit for performing an erase operation. Each memory block 1011 may include a plurality of memory cells, and each memory cell may be addressed by, for example, bit lines 41 and word lines 43. The bit lines 41 and the word lines 43 may be arranged vertically (e.g., in rows and columns respectively), thereby forming an array of metal lines. The directions of the bit lines and the word lines are in Figure 8Are respectively labeled as "BL" and "WL" in the figure. In the present disclosure, one or more memory blocks 1011 may also be referred to as a "memory array" or an "array". A memory array is a core area in a memory device that performs a storage function.

[0139] The memory 101 further includes a peripheral circuit area 1012. The peripheral circuit area 1012 (also referred to as peripheral circuits) includes many digital, analog, and / or mixed-signal circuits (e.g., page buffer / sense amplifier 10121, row decoder / word line driver 10122, column decoder / bit line driver 10123, and peripheral control circuit 10124) to support the functions of the memory 101. Among them, the peripheral control circuit 10124 may include registers, active and / or passive semiconductor devices, such as transistors, diodes, capacitors, or resistors, etc., which is obvious to those of ordinary skill in the art. The peripheral control circuit 10124 of the peripheral circuit area 1012 may be configured to initiate a programming operation on a selected memory cell of a NAND memory string in the memory block 1011. In some embodiments, the peripheral control circuit 10124 receives a programming command from the memory controller 102 through an interface, and in response, sends control signals to the row decoder / word line driver 10122, column decoder / bit line driver 10123, and voltage generator ( Figure 8 not shown in the figure) provided in the peripheral circuit area 1012 to initiate a programming operation on the selected memory cell.

[0140] Figure 8 The layout of the memory system 10 and the electronic devices in the memory 101 in the figure is shown as an example. The memory system 10 and the memory 101 may have other layouts and may include additional devices. For example, the memory 101 may further include a high-voltage charge pump, input / output circuits, etc. The memory system 10 may further include firmware and data scramblers, etc. In some embodiments, the peripheral circuit area 1012 and the memory array may be independently formed on separate wafers and connected to each other through wafer bonding.

[0141] Among them, the memory controller 102 and one or more memories 101 may be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an embedded multi media card (eMMC) package. That is, the memory system 10 may be implemented and packaged into different types of terminal electronic products. In Figure 9In one example shown, the memory controller 102 and a single memory 101 may be integrated into a memory card 200. The memory card 200 may include a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD card), or a Universal Flash Storage (UFS), etc. The memory card 200 may also include a memory card connector 210 that couples the memory card 200 to a host 50. In Figure 10 In another example shown, the memory controller 102 and multiple memories 101 may be integrated into a Solid-State Drive (SSD) 300. The SSD 300 may also include an SSD connector 310 that couples the SSD 80 to the host 50.

[0142] Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0143] The electronic device may include the above memory system, and may also include at least one of a Central Processing Unit (CPU) and a cache, etc.

[0144] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A memory, characterized in that, it includes: a memory cell array, the memory cell array including a plurality of memory strings, each of the memory strings including a first selection transistor, a plurality of memory cells, and a second selection transistor connected in series in sequence; a plurality of word lines, the plurality of word lines being coupled to the plurality of memory cells; a first selection line, the first selection line being coupled to the first selection transistor; and a peripheral circuit, the peripheral circuit being coupled to the plurality of word lines and the first selection line, and being configured to: in a first stage of a recovery phase of a verification operation, apply a first voltage to a first word line and apply a second voltage to a second word line, the second voltage being greater than the first voltage; in a second stage of the recovery phase of the verification operation, apply a third voltage to the first selection line.

2. The memory according to claim 1, characterized in that, the peripheral circuit is further configured to: in a third stage of the recovery phase of the verification operation, apply a fourth voltage to the first word line and apply a fifth voltage to the second word line, the fifth voltage being greater than the fourth voltage.

3. The memory according to claim 1, characterized in that, the memory further includes a second selection line, the second selection line being coupled to the second selection transistor; the peripheral circuit is further configured to: in a second stage of the recovery phase of the verification operation, apply a fourth voltage to the second selection line.

4. The memory according to claim 3, characterized in that, the peripheral circuit is further configured to: after the second stage of the recovery phase of the verification operation, apply a sixth voltage to the first selection line, the sixth voltage being less than the third voltage.

5. The memory according to claim 4, characterized in that, the peripheral circuit is further configured to: in a fourth stage of the recovery phase of the verification operation, apply the fourth voltage to the first selection line.

6. The memory according to claim 5, characterized in that, the peripheral circuit is further configured to: in a fifth stage of the recovery phase of the verification operation, apply a programming voltage to the second word line and apply a conduction voltage to the first word line.

7. The memory according to claim 1, characterized in that, the peripheral circuit is further configured to: in a first stage of the recovery phase of the verification operation, apply a fourth voltage to a third word line, wherein the third word line is located between the second word line and the first selection line.

8. The memory according to claim 7, characterized in that, the memory cells coupled to the first word line are programmed memory cells, and the memory cells coupled to the third word line are unprogrammed memory cells.

9. The memory according to claim 8, characterized in that, the peripheral circuit is further configured to: in a second stage of the recovery phase of the verification operation, apply a seventh voltage to a source line, wherein the first selection line is located between the third word line and the source line.

10. The memory according to claim 8, characterized in that, the peripheral circuit is further configured to: In the second stage of the recovery phase of the verification operation, an eighth voltage is applied to the bit line, wherein the first selection line is located between the third word line and the bit line.

11. The memory according to claim 1, wherein, the peripheral circuit is further configured to: In the first stage of the recovery phase of the verification operation, apply the second voltage to the fourth word line, wherein the fourth word line is located between the second word line and the first word line.

12. The memory according to claim 1, wherein, the peripheral circuit is further configured to: In the first stage of the recovery phase of the verification operation, apply a fourth voltage to the fifth word line, wherein the fifth word line is located between the first word line and the second selection line.

13. The memory according to claim 1, wherein, the peripheral circuit is further configured to: During the last verification operation of the memory string, in the first stage of the recovery phase of the last verification operation, apply a ninth voltage to the first word line and the second word line.

14. The memory according to claim 1, wherein, the second voltage is less than the conduction voltage.

15. A method for operating a memory, wherein, the method includes: In the first stage of the recovery phase of the verification operation, apply a first voltage to the first word line and a second voltage to the second word line, the second voltage being greater than the first voltage; In the second stage of the recovery phase of the verification operation, apply a third voltage to the first selection line.

16. The method according to claim 15, wherein, the method further includes: In the third stage of the recovery phase of the verification operation, apply a fourth voltage to the first word line and a fifth voltage to the second word line, the fifth voltage being greater than the fourth voltage.

17. The method according to claim 15, wherein, the method further includes: In the second stage of the recovery phase of the verification operation, apply a fourth voltage to the second selection line.

18. The method according to claim 17, wherein, the method further includes: After the second stage of the recovery phase of the verification operation, apply a sixth voltage to the first selection line, the sixth voltage being less than the third voltage.

19. The method according to claim 18, wherein, the method further includes: In the fourth stage of the recovery phase of the verification operation, apply the fourth voltage to the first selection line.

20. The method according to claim 19, wherein, the method further includes: In the fifth stage of the recovery phase of the verification operation, apply a programming voltage to the second word line and a conduction voltage to the first word line.

21. The method according to claim 15, wherein, the method further includes: In the first stage of the recovery phase of the verification operation, apply a fourth voltage to the third word line, wherein the third word line is located between the second word line and the first selection line.

22. The method according to claim 21, wherein, The memory cells coupled to the first word line are programmed memory cells, and the memory cells coupled to the third word line are unprogrammed memory cells.

23. The method according to claim 22, wherein, the method further comprises: applying a seventh voltage to the source line in a second stage of a recovery phase of the verify operation, wherein the first select line is between the third word line and the source line.

24. The method according to claim 22, wherein, the method further comprises: applying an eighth voltage to the bit line in a second stage of a recovery phase of the verify operation, wherein the first select line is between the third word line and the bit line.

25. The method according to claim 15, wherein, the method further comprises: applying a second voltage to a fourth word line in a first stage of a recovery phase of the verify operation, wherein the fourth word line is between the second word line and the first word line.

26. The method according to claim 15, wherein, the method further comprises: applying a fourth voltage to a fifth word line in a first stage of a recovery phase of the verify operation, wherein the fifth word line is between the first word line and the second select line.

27. The method according to claim 15, wherein, the method further comprises: applying a ninth voltage to the first word line and the second word line in a first stage of a recovery phase of a last verify operation on the memory string during the last verify operation.

28. The method according to claim 15, wherein, the second voltage is less than the turn-on voltage.

29. A memory system, wherein, the memory system comprises: one or more memories according to any one of claims 1 to 14; a memory controller coupled to the memory and configured to control the memory.

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