A multi-dimensional testing method and system for memory particles

Abstract

The application discloses a kind of memory grain multidimensional test method and system, it is related to memory grain test technical field, including, install multiple memory grains to be tested to form multiple Rank combination, and through setting staggered mapping mode simulates high load environment in actual use;Non-contact light wave signal integrity test is carried out using photonic crystal sensor, and light wave signal integrity data is output;Based on the mechanical property data and light wave signal integrity data of multiple Rank combination, potential failure is predicted using fault prediction model;Based on the fault prediction result of fault prediction model, in combination with the conversion of linear address and physical address, locate fault memory grain unit;The application is combined with mechanical property data and light wave signal integrity data, and potential failure is intelligently analyzed and early warned using fault prediction model, and the stability and reliability of memory grain are improved.

Description

Technical Field

[0001] This invention relates to the field of memory chip testing technology, and in particular to a multi-dimensional testing method and system for memory chips. Background Technology

[0002] With the rapid development of computer technology, memory, as a key storage component in computer systems, plays a crucial role in the operating efficiency and stability of the entire system in terms of its performance and reliability. In recent years, DDR (Double Data Rate) memory technology has evolved from DDR3 to DDR4 and DDR5. These new generation memory chips have not only achieved significant improvements in storage density and access speed, but also realized more efficient data transmission and parallel processing capabilities through multi-rank combination architecture design.

[0003] However, this complex architecture also presents challenges for memory chip reliability testing and fault diagnosis. Traditional memory testing methods mostly rely on electrical signal integrity testing and simple logical address read / write verification, making it difficult to comprehensively evaluate the dynamic performance of memory chips under high load and complex environments. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a multi-dimensional testing method for memory chips to solve the problem of comprehensively evaluating the dynamic performance of memory chips under high load and complex environments.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a multi-dimensional testing method for memory chips, comprising,

[0008] Multiple memory chips to be tested are installed to form a multi-rank combination, and a high-load environment in actual use is simulated by setting an interleaved mapping mode.

[0009] High-frequency vibration and stress testing is performed using SAW sensors to monitor the vibration and strain of multi-rank combinations in real time and output mechanical performance data.

[0010] Non-contact optical signal integrity testing is performed using a photonic crystal sensor, and optical signal integrity data is output.

[0011] Based on multi-rank combined mechanical performance data and optical signal integrity data, a fault prediction model is used to predict potential faults.

[0012] Based on the fault prediction results from the fault prediction model, and combined with the conversion between linear address and physical address, the faulty memory cell can be located.

[0013] As a preferred embodiment of the multi-dimensional testing method for memory chips described in this invention, the steps involve installing multiple memory chips to be tested to form a multi-rank combination, and simulating a high-load environment in actual use by setting an interleaved mapping mode. The specific steps are as follows.

[0014] Based on the size and pin distribution of the memory chip under test, a multi-rank layout of the test board is constructed, with each rank corresponding to a group of memory chips, and different ranks are arranged on the two sides of the test board.

[0015] The test board integrates an interface for connecting to the test equipment.

[0016] The memory chips were installed onto the pads of the test board using an automated pick-and-place machine.

[0017] Connect the test board to the automated testing equipment;

[0018] Start the self-test program of the automated test equipment to check whether the hardware on the test board is working properly;

[0019] Set up an interleaved mapping mode to simulate a high-load environment in real-world use;

[0020] Configure the timing, voltage, and frequency parameters of the memory controller according to the specifications of the memory chip under test.

[0021] As a preferred embodiment of the multi-dimensional testing method for memory chips described in this invention, the step of using a SAW sensor for high-frequency vibration and stress testing, real-time monitoring of vibration and strain of multi-rank combinations, and outputting mechanical performance data includes the following specific steps.

[0022] Multiple SAW sensors based on piezoelectric materials are evenly arranged on the test board pads and signal channels.

[0023] Use conductive adhesive to fix the SAW sensor;

[0024] Under no-load conditions, the initial response characteristics of the SAW sensor were recorded as a reference benchmark for subsequent tests.

[0025] Mechanical stress and vibration are applied, and the response changes of the SAW sensor are recorded. By comparing the actual values ​​of strain and vibration frequency with the measured values ​​of the SAW sensor, the sensitivity and linearity of the sensor are adjusted.

[0026] Set the vibration frequency range according to the application scenario of the memory chips;

[0027] The stress intensity is set according to the specifications of the memory chips and the application scenario;

[0028] Vibration and stress are applied to the test plate according to the set vibration frequency and stress intensity.

[0029] While applying vibration and stress to the test board, the SAW sensor is used to output the propagation speed and phase change of the sound wave by reflecting the sound waves on the surface of each memory chip.

[0030] The vibration frequency of the memory chip is calculated by measuring the time difference of sound wave propagation on the surface of the memory chip.

[0031] By analyzing the phase change of the sound wave and combining it with the formula of elasticity, the strain of the memory chip is calculated.

[0032] The vibration frequency and strain of the memory chips are output as mechanical performance data.

[0033] As a preferred embodiment of the multi-dimensional testing method for memory chips described in this invention, the specific steps for using a photonic crystal sensor to perform non-contact optical signal integrity testing and outputting optical signal integrity data are as follows.

[0034] Photonic crystal sensors are mounted on the signal pins of each memory chip and formed in a surround array;

[0035] The photonic crystal sensor was calibrated under both no-load and applied optical signal conditions.

[0036] The frequency range for optical signal transmission is set according to the operating frequency of the memory chips and the application scenario.

[0037] The signal transmission strength range is set according to the voltage parameters of the memory chips and the application scenario;

[0038] Based on the pin distribution and signal routing design of the memory chips, differential signal transmission is used;

[0039] The automated testing equipment controls the signal generator to send light wave signals with a set frequency and intensity range to the memory chip.

[0040] Real-time monitoring of the propagation speed, amplitude, and phase changes of light waves using photonic crystal sensors;

[0041] The attenuation value of the optical signal is calculated based on the amplitude change of the real-time monitored optical signal.

[0042] Calculate the reflection coefficient of the light wave signal based on the propagation speed of the light wave signal;

[0043] The phase difference between the input and output optical signals is calculated by monitoring the phase change of the optical signals.

[0044] The attenuation value, reflection coefficient, and phase difference of the optical wave signal are output as optical wave signal integrity data.

[0045] As a preferred embodiment of the multi-dimensional testing method for memory chips described in this invention, the mechanical performance data and optical signal integrity data based on multi-rank combinations are used to predict potential faults using a fault prediction model. The specific steps are as follows:

[0046] Collect and process historical data on the mechanical performance and optical signal integrity of memory chips in multi-rank combinations under normal and fault conditions.

[0047] The processed training samples are shuffled and divided into training set, validation set and test set;

[0048] A fault prediction model is constructed based on a convolutional neural network. The training set is input into the fault prediction model. Based on the fault risk score output by the fault prediction model, it is determined whether a fault has occurred and the predicted binary label is output.

[0049] Based on the predicted binary labels and the actual binary labels, the loss value of the fault prediction model is calculated using the binary cross-entropy loss function.

[0050] The gradient of the loss with respect to the fault prediction model parameters is calculated using the gradient descent algorithm, and the fault prediction model parameters are then updated.

[0051] Based on the Adam optimization algorithm, the parameters of the fault prediction model are dynamically adjusted to minimize the loss function;

[0052] After each training iteration, evaluate and record the performance of the fault prediction model on the validation set.

[0053] Once all training samples in the training set have been used to train the fault prediction model, the training is considered complete. The training samples in the test set are then used to test the performance of the trained fault prediction model.

[0054] Integrate the trained fault prediction model into automated testing equipment;

[0055] The mechanical performance data and optical signal integrity data obtained from real-time monitoring are input into the fault prediction model, and the output is a binary label representing fault and normal.

[0056] As a preferred embodiment of the multi-dimensional testing method for memory chips described in this invention, the following steps are taken: Collecting and processing historical data on the mechanical performance and optical signal integrity of memory chips in multi-rank combinations under normal operating and fault conditions, specifically follows.

[0057] Add a uniform timestamp based on the collection time of each historical data item;

[0058] Mechanical performance data and optical signal integrity data from historical data are integrated into training samples, and binary labels representing normal and fault are added to each training sample.

[0059] High-frequency noise is removed using filtering algorithms, and outliers are removed using statistical methods.

[0060] The Min-Max normalization method is used to map historical data to a specific range.

[0061] As a preferred embodiment of the multi-dimensional testing method for memory chips described in this invention, the fault prediction results based on the fault prediction model, combined with the conversion between linear addresses and physical addresses, are used to locate the faulty memory chip unit. The specific steps are as follows:

[0062] When the fault prediction model predicts a normal binary label, it means that the memory particles in the multi-rank combination are all functioning normally.

[0063] When the fault prediction model predicts a binary label for the fault, it indicates that a memory particle in a multi-rank combination has failed, and the time of the fault occurrence is recorded.

[0064] Based on the linear address range and physical address range of the memory chips on the test board, establish the mapping relationship between linear addresses and physical addresses;

[0065] Based on the fault time detected by the fault prediction model, the corresponding linear address range is extracted from the input data;

[0066] By utilizing the mapping relationship between linear addresses and physical addresses, linear addresses can be converted into physical addresses;

[0067] The Rank number and memory chip number are determined by comparing the faulty physical address with the physical address range of each Rank, as shown in the following expression:

[0068] ;

[0069] ;

[0070] in, The Rank number at the time the fault occurred. For physical address, and They represent the first The starting and ending physical addresses of each Rank. The memory chip number at the time of the failure. The physical address span of a single memory chip. Number The starting physical address allocated to the Rank in the physical address space of memory;

[0071] Automated test equipment (ATE) is used to perform unit tests on the memory chips where the fault is located to verify read / write performance and data integrity.

[0072] Secondly, the present invention provides a multi-dimensional testing system for memory chips, including a multi-rank combination module, a mechanical performance data module, an integrity data module, a fault prediction module, and a fault location module.

[0073] The multi-rank combination module is used to install multiple memory chips to be tested to form a multi-rank combination, and to simulate the high-load environment in actual use by setting an interleaved mapping mode;

[0074] The mechanical performance data module is used to perform high-frequency vibration and stress tests using SAW sensors, monitor the vibration and strain of multi-rank combinations in real time, and output mechanical performance data.

[0075] The integrity data module is used to perform non-contact optical signal integrity testing using a photonic crystal sensor and output optical signal integrity data.

[0076] The fault prediction module is used to predict potential faults based on multi-rank combined mechanical performance data and optical signal integrity data, using a fault prediction model.

[0077] The fault location module is used to locate faulty memory granular units based on the fault prediction results of the fault prediction model and the conversion between linear addresses and physical addresses.

[0078] Thirdly, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, wherein: when the computer program is executed by the processor, it implements any step of the multidimensional testing method for memory particles as described in the first aspect of the present invention.

[0079] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the memory particle multidimensional testing method as described in the first aspect of the present invention.

[0080] The beneficial effects of this invention are as follows: By installing multi-rank combinations and setting interleaved mapping modes, this invention simulates actual high-load environments, making the testing closer to real-world application scenarios and exposing potential problems in advance. It utilizes SAW sensors for high-frequency vibration and stress testing, collecting mechanical performance data in real time to assess the reliability of the memory chips under dynamic stress environments. Through non-contact optical signal integrity testing using photonic crystal sensors, it accurately captures anomalies in high-speed signal transmission, ensuring signal transmission stability. Combining mechanical performance data and optical signal integrity data, it achieves intelligent analysis and early warning of potential faults through a fault prediction model, improving the stability and reliability of memory chips. Based on the mapping between linear addresses and physical addresses, it accurately locates faulty memory cells, providing support for rapid fault maintenance. Attached Figure Description

[0081] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0082] Figure 1 This is a flowchart of the multi-dimensional testing method for memory chips in Example 1.

[0083] Figure 2 This is a block diagram of the memory chip multidimensional testing system in Example 1. Detailed Implementation

[0084] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0085] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0086] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0087] Example 1, referring to Figure 1 and Figure 2This is the first embodiment of the present invention, which provides a multi-dimensional testing method for memory chips, including the following steps:

[0088] S1. Install multiple memory chips to be tested to form a multi-rank combination, and simulate the high-load environment in actual use by setting an interleaved mapping mode.

[0089] PCB materials with good electrical properties and mechanical stability, such as FR-4 or Rogers RO4350B, are used. These materials have low dielectric constant and loss tangent, which can reduce loss and interference during signal transmission.

[0090] Based on the size and pin distribution of the memory chips under test, a multi-rank layout of the test board is constructed. Each rank corresponds to a group of memory chips. Different ranks are arranged on both sides of the test board to increase the test density. For example, 4 ranks can be arranged on one side of the test board and 4 ranks can be arranged on the other side, for a total of 8 ranks.

[0091] The test board integrates interfaces for connecting to test equipment, such as JTAG, SPI, and I2C, to facilitate subsequent automated testing.

[0092] Use an automatic pick-and-place machine to install memory chips onto the pads of the test board. During the installation process, temperature and pressure should be strictly controlled to avoid damaging the memory chips. For BGA packaged memory chips, it is recommended to use an X-ray inspection device to check the solder joint quality and ensure that each pin makes good contact with the pad.

[0093] Connect the test board to the automated test equipment (ATE) and ensure that all interfaces (such as JTAG, SPI, I2C, etc.) are correctly connected;

[0094] Start the self-test program of the automated test equipment to check whether the hardware on the test board is working properly;

[0095] This includes initializing each memory chip via BIOS or firmware to ensure it is in normal working order, verifying that the address mapping register group of the memory controller is correctly configured, ensuring that the interleaved mapping mode can be enabled normally, and checking for short circuits or open circuits in the power and signal traces of each Rank to ensure the integrity of signal transmission.

[0096] Setting up an interleaved mapping mode to simulate a high-load environment in actual use means that the memory controller allocates consecutive memory addresses to different ranks, so that the CPU can open multiple ranks at the same time when accessing memory, thus forming a dynamic "heavy load mode".

[0097] Configure the timing parameters (tRCD, tRP, tRFC, etc.), voltage parameters (VDD, VDDQ, etc.), and frequency parameters (DDR4 / DDR5 operating frequency) of the memory controller according to the specifications of the memory chip under test.

[0098] S2. High-frequency vibration and stress testing is performed using SAW sensors to monitor the vibration and strain of multi-rank combinations in real time and output mechanical performance data.

[0099] Using SAW sensors based on piezoelectric materials, such as ZnO or AlN, multiple SAW sensors are evenly arranged on the test board pads and signal channels to ensure full coverage of all possible stress concentration areas. For example, one SAW sensor is installed at each of the four corners of each memory chip to form a four-point array for more accurate monitoring of the memory chips.

[0100] Use conductive adhesive to fix the SAW sensor. During the fixing process, ensure that the sensor is in close contact with the surface of the memory chip to avoid measurement errors caused by poor contact. For BGA packaged memory chips, it is recommended to use flexible connectors to connect the SAW sensor to the pads on the test board to reduce mechanical interference to the memory chip.

[0101] Under no-load conditions, the initial response characteristics of the SAW sensor, such as sound wave propagation speed, amplitude, and phase, are recorded as a reference benchmark for subsequent tests.

[0102] Mechanical stress and vibration are applied, and the response changes of the SAW sensor are recorded. By comparing the actual values ​​of strain and vibration frequency with the measured values ​​of the SAW sensor, the sensitivity and linearity of the sensor are adjusted.

[0103] Set the vibration frequency range according to the application scenario of the memory chips;

[0104] For example, for server applications, high-frequency vibration (such as 100kHz~1MHz) is set to simulate the mechanical vibration during high-speed data transmission; for mobile device applications, low-frequency vibration (such as 10Hz~100Hz) is set to simulate the mechanical shock during daily use.

[0105] The stress intensity is set according to the specifications of the memory chips and the application scenario;

[0106] For example, for BGA packaged memory chips, a certain bending stress (such as bending deformation of 100μm~500μm) is applied to simulate the mechanical stress of memory chips during insertion, removal or thermal cycling. For TSOP packaged memory chips, a certain shear stress (such as shear force of 10 N~50 N) is applied to simulate the mechanical stress of memory chips during soldering or disassembly.

[0107] Vibration and stress are applied to the test plate according to the set vibration frequency and stress intensity.

[0108] While applying vibration and stress to the test board, the SAW sensor is used to output the propagation speed and phase change of the sound wave by reflecting the sound waves on the surface of each memory chip.

[0109] The vibration frequency of the memory chip is calculated by measuring the time difference of sound wave propagation on the surface of the memory chip, as shown in the following expression:

[0110] ;

[0111] in, This refers to the vibration frequency of the memory chips. For the speed of sound wave propagation, The wavelength of the sound wave. For the time difference of sound wave propagation, The round trip distance from the sound wave emission point to the surface of the memory chip;

[0112] By analyzing the phase change of the sound wave and combining it with the formulas of elasticity, the strain of the memory chip is calculated, as shown in the following expression:

[0113] ;

[0114] in, For the strain of memory chips, The phase difference of the sound waves;

[0115] The vibration frequency and strain of the memory chips are output as mechanical performance data.

[0116] S3. Perform non-contact optical signal integrity testing using a photonic crystal sensor and output optical signal integrity data.

[0117] Photonic crystal sensors are installed on the signal pins of each memory chip and formed in a surround array to more accurately monitor the integrity of optical signals;

[0118] The photonic crystal sensor was calibrated under both no-load and applied optical signal conditions.

[0119] Among them, under no-load conditions, the initial response characteristics of the photonic crystal sensor, such as the propagation speed, amplitude and phase of light waves, are recorded. These data will serve as a reference benchmark for subsequent tests.

[0120] By comparing the actual value of the known signal with the sensor's measured value, the sensor's sensitivity and linearity are adjusted to ensure that it can accurately measure the signal integrity of the memory chip under different load conditions.

[0121] The frequency range for optical signal transmission is set according to the operating frequency of the memory chips and the application scenario.

[0122] For DDR4 / DDR5 memory chips, it is recommended to set a high frequency signal (such as 2GHz~5GHz) to simulate the signal integrity during high-speed data transmission. For low-speed applications, it is recommended to set a lower signal frequency (such as 100MHz~500MHz) to simulate the signal transmission situation in daily use.

[0123] The signal transmission strength range is set according to the voltage parameters of the memory chips and the application scenario;

[0124] For server applications, it is recommended to apply a higher optical signal strength (e.g., 1.2 V~1.8 V) to simulate voltage fluctuations during high-speed data transmission. For mobile device applications, it is recommended to apply a lower optical signal strength (e.g., 0.9 V~1.2 V) to simulate signal transmission in low-power mode.

[0125] Based on the pin distribution and signal routing design of memory chips, differential signal transmission methods (such as differential pairs) are used to reduce electromagnetic interference and signal reflection.

[0126] The automated test equipment (ATE) controls a signal generator to send light wave signals with a set frequency and intensity range to the memory chips.

[0127] Real-time monitoring of the propagation speed, amplitude, and phase changes of light waves using photonic crystal sensors;

[0128] Based on the real-time monitoring of the amplitude change of the optical signal, the optical signal attenuation value is calculated, reflecting the energy loss of the signal during transmission. The expression is as follows:

[0129] ;

[0130] in, This is the attenuation value of the optical signal. The amplitude of the input optical wave signal, The amplitude of the output optical wave signal;

[0131] Based on the propagation speed of light waves, the reflection coefficient of light waves is calculated, reflecting the reflection phenomenon that occurs during signal transmission. The expression is as follows:

[0132] ;

[0133] ;

[0134] in, The reflection coefficient of the light wave signal. For load impedance, The characteristic impedance of the transmission line, The speed at which light waves propagate in the transmission line. The speed at which light waves propagate in a vacuum;

[0135] The phase difference between the input and output optical signals is calculated by monitoring the phase change of the optical signals.

[0136] The attenuation value, reflection coefficient, and phase difference of the optical wave signal are output as optical wave signal integrity data.

[0137] S4. Based on multi-rank combined mechanical performance data and optical signal integrity data, a fault prediction model is used to predict potential faults.

[0138] Collect and process historical data on the mechanical performance and optical signal integrity of memory chips in multi-rank combinations under normal and fault conditions.

[0139] Add a uniform timestamp based on the collection time of each historical data item;

[0140] Mechanical performance data and optical signal integrity data from historical data are integrated into training samples, and binary labels representing normal and fault are added to each training sample (0 represents normal and 1 represents fault).

[0141] Use filtering algorithms (such as low-pass filtering, high-pass filtering, or band-pass filtering) to remove high-frequency noise, and use statistical methods (such as mean filtering and median filtering) to remove outliers.

[0142] By introducing artificial faults (such as randomly adding noise, changing signal strength, etc.), more types of fault data can be generated;

[0143] Using the Min-Max normalization method, historical data is mapped to specific... scope.

[0144] The processed training samples are shuffled and divided into training set, validation set and test set;

[0145] A fault prediction model is constructed based on a convolutional neural network. The training set is input into the fault prediction model. Based on the fault risk score output by the fault prediction model, it is determined whether a fault has occurred, and binary labels representing normal and fault are output.

[0146] Specifically, the input layer takes a multidimensional feature tensor after time windowing. In the convolutional layer, a one-dimensional convolutional kernel is used to extract time-series features. The multidimensional feature tensor is convolved through the first and second convolutional layers, and a max-pooling layer is added with a pooling window size of 2 and a stride of 2 to reduce feature dimensionality while retaining key features. The outputs of the convolutional and pooling layers are flattened and input into a fully connected layer. The ReLU activation function is used to further extract non-linear features. Finally, in the output layer, a fault risk score is output using the Sigmoid activation function. Based on the fault risk score, it is determined whether the memory granules are malfunctioning, and binary labels representing malfunctions and normal operation are output. The expression is as follows:

[0147] ;

[0148] in, To score the failure risk, when When the predicted result of the memory chip is faulty, the fault prediction model outputs 1. When the time is right, it indicates that the memory chip's prediction result is normal, and the fault prediction model outputs 0. This is the weight matrix. For multidimensional feature tensors, For bias terms;

[0149] Based on the predicted binary labels and the actual binary labels, the loss value of the fault prediction model is calculated using the binary cross-entropy loss function, as shown in the following expression:

[0150] ;

[0151] in, Binary cross-entropy loss value, The number of training samples in the training set. This is an index for the number of training samples in the training set. The actual binary labels for the training samples. Binary labels predicted by the fault prediction model;

[0152] The gradient of the loss with respect to the fault prediction model parameters is calculated using the gradient descent algorithm, and the fault prediction model parameters are then updated.

[0153] Based on the Adam optimization algorithm, the parameters of the fault prediction model are dynamically adjusted to minimize the loss function;

[0154] After each training iteration, evaluate and record the performance of the fault prediction model on the validation set (e.g., loss value, accuracy, precision, recall).

[0155] Once all training samples in the training set have been used to train the fault prediction model, the training is considered complete. The training samples in the test set are then used to test the performance of the trained fault prediction model.

[0156] Integrate the trained fault prediction model into automated testing equipment;

[0157] The mechanical performance data and optical signal integrity data obtained from real-time monitoring are input into the fault prediction model, and the output is a binary label representing fault and normal.

[0158] S5. Based on the fault prediction results of the fault prediction model, combined with the conversion between linear address and physical address, the faulty memory cell is located.

[0159] When the fault prediction model predicts a normal binary label, it means that the memory particles in the multi-rank combination are all functioning normally.

[0160] When the fault prediction model predicts a binary label for the fault, it indicates that a memory particle in a multi-rank combination has failed, and the time of the fault occurrence is recorded.

[0161] Based on the linear address range and physical address range of the memory chips on the test board, establish the mapping relationship between linear addresses and physical addresses, as shown in the following expression:

[0162] ;

[0163] ;

[0164] ;

[0165] in, For physical address, As a scaling factor, For linear addresses, Indicates the starting offset of the physical address. and These represent the starting physical address and the ending physical address, respectively. and These represent the starting linear address and the ending linear address, respectively.

[0166] Based on the fault time detected by the fault prediction model, the corresponding linear address range is extracted from the input data;

[0167] Specifically, based on the output time of the fault prediction model, the fault occurrence time window is determined in the input data, and the linear addresses within the fault time window are filtered from the dataset to extract the range of linear addresses related to the fault.

[0168] By utilizing the mapping relationship between linear addresses and physical addresses, linear addresses can be converted into physical addresses;

[0169] The Rank number and memory chip number are determined by comparing the faulty physical address with the physical address range of each Rank, as shown in the following expression:

[0170] ;

[0171] ;

[0172] in, The Rank number at the time the fault occurred. and They represent the first The starting and ending physical addresses of each Rank. The memory chip number at the time of the failure. The physical address span of a single memory chip. Number The starting physical address allocated to the Rank in the physical address space of memory;

[0173] Automated test equipment (ATE) is used to perform unit tests on the memory chips where the fault is located to verify read / write performance and data integrity.

[0174] This embodiment also provides a multi-dimensional testing system for memory chips, including: a multi-rank combination module, a mechanical performance data module, an integrity data module, a fault prediction module, and a fault location module.

[0175] The multi-rank combination module is used to install multiple memory chips under test to form a multi-rank combination, and simulates the high-load environment in actual use by setting an interleaved mapping mode; the mechanical performance data module is used to perform high-frequency vibration and stress testing using a SAW sensor, monitor the vibration and strain of the multi-rank combination in real time, and output mechanical performance data; the integrity data module is used to perform non-contact optical signal integrity testing using a photonic crystal sensor, and output optical signal integrity data; the fault prediction module is used to predict potential faults based on the mechanical performance data and optical signal integrity data of the multi-rank combination using a fault prediction model; the fault location module is used to locate the faulty memory chip unit based on the fault prediction results of the fault prediction model, combined with the conversion between linear address and physical address.

[0176] This embodiment also provides a computer device applicable to the multi-dimensional testing method for memory chips, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the multi-dimensional testing method for memory chips as proposed in the above embodiment.

[0177] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0178] This embodiment also provides a storage medium storing a computer program, which, when executed by a processor, implements the multi-dimensional testing method for memory particles as proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0179] In summary, this invention achieves the following: by installing multi-rank combinations and setting interleaved mapping modes to simulate actual high-load environments, making the testing more closely resemble real-world application scenarios and exposing potential problems in advance; by utilizing SAW sensors for high-frequency vibration and stress testing to collect mechanical performance data in real time and assess the reliability of the memory chips under dynamic stress environments; by using photonic crystal sensors for non-contact optical signal integrity testing to accurately capture anomalies in high-speed signal transmission and ensure signal transmission stability; by combining mechanical performance data and optical signal integrity data, a fault prediction model enables intelligent analysis and early warning of potential faults, improving the stability and reliability of memory chips; and by accurately locating faulty memory cells based on the mapping between linear addresses and physical addresses, providing support for rapid fault maintenance.

[0180] Example 2, referring to Table 1, is the second embodiment of the present invention. To further verify the technical solution of the present invention, experimental simulation data of the multi-dimensional testing method for memory chips are given.

[0181] To verify the performance of multi-rank memory chips in high-load environments and the effectiveness of the fault prediction model, an experimental scheme was designed. First, eight DDR4 memory chips (each with a capacity of 8GB and a frequency of 3200MHz) were selected, and a test board was fabricated using FR-4 PCB material. Based on the size and pin distribution of the memory chips under test, a double-sided multi-rank structure was designed, with four ranks arranged on each side, for a total of eight ranks. A JTAG interface was integrated on the test board for signal transmission and monitoring.

[0182] The memory chips are precisely soldered onto the pads using an automated placement machine. After soldering, each solder joint is inspected using an X-ray inspection device to ensure solder joint quality. Subsequently, the test board is connected to an automated test equipment (ATE) and the ATE's self-test program is run to verify the hardware functionality of the test board.

[0183] At the beginning of the experiment, each memory chip was initialized using BIOS, and the address mapping register configuration of the memory controller was verified to ensure that the interleaved mapping mode was enabled normally. Based on this, the mechanical performance of the memory chips was tested using SAW sensors.

[0184] Each memory chip has an SAW sensor installed at each of its four corners. By applying mechanical stress of different frequencies and intensities, the sensor records the propagation speed, phase change, and vibration frequency of the sound waves. In addition, non-contact optical signal integrity testing is performed based on photonic crystal sensors to monitor key parameters such as signal propagation speed, attenuation value, and reflection coefficient.

[0185] To compare the performance of existing technologies, a single-rank memory chip layout was selected as a control group, and the same testing procedures were used for performance evaluation. All data in the experiment were automatically collected using ATE and recorded in the experimental log. The following is a summary of the experimental data.

[0186] The details are shown in Table 1 below:

[0187] Table 1 Comparison of Experimental Data

[0188]

[0189] Analysis of the above experimental data shows that the multi-rank combination design of the present invention exhibits a significant performance improvement compared with the single-rank combination layout.

[0190] In terms of fault prediction, the multi-rank combination of the present invention predicts a fault rate of 0.002, while the single-rank combination is 0.035, representing a 94.3% reduction in the fault rate. This result fully demonstrates that by combining the mechanical performance data and optical signal integrity data of the multi-rank combination with the fault prediction model, the present invention can more accurately predict potential faults, thereby significantly improving the reliability of memory chips.

[0191] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A multi-dimensional testing method for memory chips, characterized in that: include, Multiple memory chips to be tested are installed to form a multi-rank combination, and a high-load environment in actual use is simulated by setting an interleaved mapping mode. High-frequency vibration and stress testing is performed using SAW sensors to monitor the vibration and strain of multi-rank combinations in real time and output mechanical performance data. Non-contact optical signal integrity testing is performed using a photonic crystal sensor, and optical signal integrity data is output. The specific steps are as follows. Photonic crystal sensors are mounted on the signal pins of each memory chip and formed in a surround array; The photonic crystal sensor was calibrated under both no-load and applied optical signal conditions. The frequency range for optical signal transmission is set according to the operating frequency of the memory chips and the application scenario. The signal transmission strength range is set according to the voltage parameters of the memory chips and the application scenario; Based on the pin distribution and signal routing design of the memory chips, differential signal transmission is used; The automated testing equipment controls the signal generator to send light wave signals with a set frequency and intensity range to the memory chip. Real-time monitoring of the propagation speed, amplitude, and phase changes of light waves using photonic crystal sensors; The attenuation value of the optical signal is calculated based on the amplitude change of the real-time monitored optical signal. Calculate the reflection coefficient of the light wave signal based on the propagation speed of the light wave signal; The phase difference between the input and output optical signals is calculated by monitoring the phase change of the optical signals. The optical signal attenuation value, reflection coefficient, and phase difference are output as optical signal integrity data. Based on multi-rank combined mechanical performance data and optical signal integrity data, a fault prediction model is used to predict potential faults. Based on the fault prediction results from the fault prediction model, and combined with the conversion between linear address and physical address, the faulty memory cell can be located.

2. The multi-dimensional testing method for memory chips as described in claim 1, characterized in that: The process involves installing multiple memory chips to be tested to form a multi-rank combination, and simulating a high-load environment in actual use by setting an interleaved mapping mode. The specific steps are as follows. Based on the size and pin distribution of the memory chip under test, a multi-rank layout of the test board is constructed, with each rank corresponding to a group of memory chips, and different ranks are arranged on the two sides of the test board. The test board integrates an interface for connecting to the test equipment. The memory chips were installed onto the pads of the test board using an automated pick-and-place machine. Connect the test board to the automated testing equipment; Start the self-test program of the automated test equipment to check whether the hardware on the test board is working properly; Set up an interleaved mapping mode to simulate a high-load environment in real-world use; Configure the timing, voltage, and frequency parameters of the memory controller according to the specifications of the memory chip under test.

3. The multi-dimensional testing method for memory chips as described in claim 2, characterized in that: The method of using SAW sensors for high-frequency vibration and stress testing, real-time monitoring of vibration and strain of multi-rank combinations, and outputting mechanical performance data are described in the following steps. Multiple SAW sensors based on piezoelectric materials are evenly arranged on the test board pads and signal channels. Use conductive adhesive to fix the SAW sensor; Record the initial response characteristics of the SAW sensor under no-load conditions; Mechanical stress and vibration are applied, and the response changes of the SAW sensor are recorded. By comparing the actual values ​​of strain and vibration frequency with the measured values ​​of the SAW sensor, the sensitivity and linearity of the sensor are adjusted. Set the vibration frequency range according to the application scenario of the memory chips; The stress intensity is set according to the specifications of the memory chips and the application scenario; Vibration and stress are applied to the test plate according to the set vibration frequency and stress intensity. While applying vibration and stress to the test board, the SAW sensor is used to output the propagation speed and phase change of the sound wave by reflecting the sound waves on the surface of each memory chip. The vibration frequency of the memory chip is calculated by measuring the time difference of sound wave propagation on the surface of the memory chip. By analyzing the phase change of the sound wave and combining it with the formula of elasticity, the strain of the memory chip is calculated. The vibration frequency and strain of the memory chips are output as mechanical performance data.

4. The multi-dimensional testing method for memory chips as described in claim 1, characterized in that: The mechanical performance data and optical signal integrity data based on multi-rank combinations are used to predict potential faults using a fault prediction model. The specific steps are as follows. Collect and process historical data on the mechanical performance and optical signal integrity of memory chips in multi-rank combinations under normal and fault conditions. The processed training samples are shuffled and divided into training set, validation set and test set; A fault prediction model is constructed based on a convolutional neural network. The training set is input into the fault prediction model. Based on the fault risk score output by the fault prediction model, it is determined whether a fault has occurred and the predicted binary label is output. Based on the predicted binary labels and the actual binary labels, the loss value of the fault prediction model is calculated using the binary cross-entropy loss function. The gradient of the loss with respect to the fault prediction model parameters is calculated using the gradient descent algorithm, and the fault prediction model parameters are then updated. Based on the Adam optimization algorithm, the parameters of the fault prediction model are dynamically adjusted to minimize the loss function; After each training iteration, evaluate and record the performance of the fault prediction model on the validation set. Once all training samples in the training set have been used to train the fault prediction model, the training is considered complete. The training samples in the test set are then used to test the performance of the trained fault prediction model. Integrate the trained fault prediction model into automated testing equipment; The mechanical performance data and optical signal integrity data obtained from real-time monitoring are input into the fault prediction model, and the output is a binary label representing fault and normal.

5. The multi-dimensional testing method for memory chips as described in claim 4, characterized in that: The process involves collecting and processing historical data on the mechanical performance and optical signal integrity of memory chips in multi-rank combinations under normal and fault conditions. The specific steps are as follows: Add a uniform timestamp based on the collection time of each historical data item; Mechanical performance data and optical signal integrity data from historical data are integrated into training samples, and binary labels representing normal and fault are added to each training sample. High-frequency noise is removed using filtering algorithms, and outliers are removed using statistical methods. The Min-Max normalization method is used to map historical data to a specific range.

6. The multi-dimensional testing method for memory chips as described in claim 1, characterized in that: The fault prediction results based on the fault prediction model, combined with the conversion between linear addresses and physical addresses, locate the faulty memory cell. The specific steps are as follows. When the fault prediction model predicts a normal binary label, it means that the memory particles in the multi-rank combination are all functioning normally. When the fault prediction model predicts a binary label for the fault, it indicates that a memory particle in a multi-rank combination has failed, and the time of the fault occurrence is recorded. Based on the linear address range and physical address range of the memory chips on the test board, establish the mapping relationship between linear addresses and physical addresses; Based on the fault time detected by the fault prediction model, the corresponding linear address range is extracted from the input data; By utilizing the mapping relationship between linear addresses and physical addresses, linear addresses can be converted into physical addresses; The Rank number and memory chip number are determined by comparing the faulty physical address with the physical address range of each Rank, as shown in the following expression: ； ； in, The Rank number at the time the fault occurred. For physical address, and They represent the first The starting and ending physical addresses of each Rank. The memory chip number at the time of the failure. The physical address span of a single memory chip. Number The starting physical address allocated to the Rank in the physical address space of memory; Automated testing equipment is used to perform unit tests on the memory chips where faults have been located, verifying read / write performance and data integrity.

7. A multi-dimensional testing system for memory chips, based on the multi-dimensional testing method for memory chips according to any one of claims 1 to 6, characterized in that: It includes a multi-rank combination module, a mechanical performance data module, an integrity data module, a fault prediction module, and a fault location module. The multi-rank combination module is used to install multiple memory chips to be tested to form a multi-rank combination, and to simulate the high-load environment in actual use by setting an interleaved mapping mode; The mechanical performance data module is used to perform high-frequency vibration and stress tests using SAW sensors, monitor the vibration and strain of multi-rank combinations in real time, and output mechanical performance data. The integrity data module is used to perform non-contact optical signal integrity testing using a photonic crystal sensor and output optical signal integrity data. The fault prediction module is used to predict potential faults based on multi-rank combined mechanical performance data and optical signal integrity data, using a fault prediction model. The fault location module is used to locate faulty memory granular units based on the fault prediction results of the fault prediction model and the conversion between linear addresses and physical addresses.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the multi-dimensional testing method for memory chips according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the multi-dimensional testing method for memory particles according to any one of claims 1 to 6.

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