Preparation method of semiconductor material without anti-phase domain defect on CMOS (Complementary Metal-Oxide-Semiconductor Transistor) compatible substrate

Abstract

The invention provides a preparation method of a semiconductor material without an anti-phase domain defect on a CMOS (Complementary Metal Oxide Semiconductor) compatible substrate. The preparation method comprises the following steps: preparing a periodic pattern on the surface of the CMOS compatible substrate; performing selective area epitaxial growth on the surface of the CMOS compatible substrate based on the periodic pattern; the period of the periodic pattern is adjusted, surfactant atoms are introduced, the semiconductor material without the anti-phase domain defect is obtained, and the semiconductor material without the anti-phase domain defect comprises an anti-phase domain semiconductor nanowire and a semiconductor nanowire network without the anti-phase domain defect. According to the method, the high-quality selected area epitaxy of the material is realized by regulating and controlling the nucleation mode of the material, and the problems that the process for growing the material is complicated and the crystal quality is poor in a traditional method are solved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of material preparation, and particularly to a method for preparing a semiconductor material without antiphase domain defects on a CMOS-compatible substrate. Background Art

[0002] Antiphase domain defects are structural defects formed during the epitaxial growth of semiconductors. They mainly occur when a polar semiconductor is epitaxially grown on a non-polar semiconductor material, and are formed due to the atoms in the non-polar semiconductor occupying incorrect positions. An antiphase domain boundary is the boundary between antiphase domains, and it is also a charged structural defect. During the epitaxial growth process, when atoms reach the substrate surface, they randomly select lattice positions. If there is unevenness in the atomic layer on the substrate surface, it may lead to disordered atomic arrangement, thus forming antiphase domains. For example, when GaSb is epitaxially grown on Si, Ga and Sb atoms will randomly select lattice positions when they reach the Si substrate surface, and Si will bond with Ga and Sb without discrimination. This will result in part of the initial atomic layer on the Si substrate surface having Ga atoms and the other part having Sb atoms. Therefore, in the subsequent epitaxial growth process, the phenomenon of Ga-Ga or Sb-Sb bonding will occur, and the boundary position is called the antiphase domain boundary. The antiphase domain boundary is a charged structural defect, which will affect the electrical and optical properties of semiconductor materials. Antiphase domain defects have an important impact on the performance of semiconductor devices. For example, in optoelectronic devices, antiphase domain defects may lead to a decrease in carrier lifetime and an increase in scattering, thus affecting the efficiency and performance of the devices. The formation of antiphase domains requires a large amount of energy. From the perspective of growth kinetics, the formation of antiphase domains is not conducive to the energy stability of the epitaxial layer system. Therefore, how to reduce the antiphase domain defect density is the key to growing high-quality semiconductor materials and fabricating high-performance semiconductor devices.

[0003] For a long time, the epitaxial growth of semiconductor materials on CMOS-compatible substrates has attracted great attention. Epitaxially growing semiconductor materials on CMOS-compatible substrates can precisely control the doping concentration and type, thereby optimizing the optoelectronic properties of the devices. In addition, once the epitaxial growth process is highly compatible with the CMOS manufacturing process, it means that the epitaxial growth technology can be introduced into the manufacturing of CMOS devices without significantly modifying the process line. This compatibility helps to reduce production costs, improve production efficiency, and accelerate the popularization and application of new technologies. As mentioned above, when epitaxially growing a semiconductor material with a different polarity from the substrate on a CMOS-compatible substrate, it is difficult to obtain high-quality semiconductor materials due to the existence of antiphase domain defects.

[0004] In recent years, planar semiconductor nanowires and semiconductor nanowire networks have also attracted great attention. Planar semiconductor nanowires and semiconductor nanowire networks are ideal building blocks for developing a new generation of high-performance electronic devices. They have significant surface effects and size effects, making charge transport more efficient. By precisely controlling the growth position and morphology of nanowires and nanowire networks, high-performance electronic logic devices, memory devices, and optoelectronic detection devices can be realized, showing extensive uses and significant advantages in the fields of high-performance electronic devices, artificial intelligence, neuroscience, and biomedicine. When epitaxially growing planar semiconductor nanowires and semiconductor nanowire networks on CMOS-compatible substrates, people have also encountered the problem of high density of antiphase domain defects, making it difficult to fabricate high-quality semiconductor nanowires and semiconductor nanowire networks. In particular, due to the existence of antiphase domain defects, the semiconductor nanowires and semiconductor nanowire networks prepared on CMOS-compatible substrates show obvious island-like growth, and the morphology of the prepared materials is rough and it is difficult to achieve large-scale epitaxy. For example, the maximum lengths of planar GaAs nanowires grown by selective area epitaxy on Si and Ge substrates are 0.8 micrometers and 3 micrometers, respectively. Traditionally, people mainly use complex buffer layer technologies to reduce the antiphase domain defects between the substrate and the epitaxial layer. However, the traditional methods have always faced the problems of complex processes and poor crystal quality. To address these issues, there is an urgent need to invent a method with a simple process that can fundamentally solve the problem of antiphase domain defects, so as to fabricate high-quality semiconductor materials without antiphase domain defects on CMOS-compatible substrates. Summary of the Invention

[0005] In view of the above problems, embodiments of the present disclosure provide a method for preparing a semiconductor material without antiphase domain defects on a CMOS-compatible substrate.

[0006] One aspect of the present disclosure provides a method for preparing a semiconductor material without antiphase domain defects on a CMOS-compatible substrate, including: preparing a periodic pattern on the surface of the CMOS-compatible substrate; performing selective area epitaxial growth on the surface of the CMOS-compatible substrate based on the periodic pattern; adjusting the period of the periodic pattern and introducing surfactant atoms to obtain a semiconductor material without antiphase domain defects, and the semiconductor material without antiphase domain defects includes semiconductor nanowires without reverse domains and semiconductor nanowire networks without antiphase domain defects.

[0007] According to embodiments of the present disclosure, the CMOS-compatible substrate includes a silicon substrate and a germanium substrate.

[0008] According to an embodiment of the present disclosure, preparing a periodic pattern on the surface of a CMOS-compatible substrate includes: depositing a protective layer on the CMOS-compatible substrate; patterning and etching the protective layer and the CMOS-compatible substrate to obtain a periodic pattern. According to an embodiment of the present disclosure, depositing a protective layer on the CMOS-compatible substrate includes: depositing the protective layer on the CMOS-compatible substrate by chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0009] According to an embodiment of the present disclosure, patterning and etching the protective layer and the CMOS-compatible substrate to obtain a periodic pattern includes: patterning the protective layer and the CMOS-compatible substrate by electron beam lithography or photolithography; etching the protective layer and the CMOS-compatible substrate by dry etching or wet etching.

[0010] According to an embodiment of the present disclosure, selective area epitaxial growth is performed on the surface of the CMOS-compatible substrate based on the periodic pattern, including: performing selective area epitaxial growth on the surface of the CMOS-compatible substrate by molecular beam epitaxy, chemical beam epitaxy, or metalorganic vapor phase epitaxy.

[0011] According to an embodiment of the present disclosure, the length of the periodic pattern is on the order of nanometers to centimeters, the width is on the order of nanometers to micrometers, and the height is on the order of nanometers.

[0012] According to an embodiment of the present disclosure, adjusting the period of the periodic pattern and introducing surfactant atoms to obtain a semiconductor material without antiphase domain defects includes: adjusting the length-width spacing between the periodic patterns, where the length-width spacing is on the order of nanometers to micrometers; introducing surfactant atoms during the selective area epitaxy of the surface of the CMOS-compatible substrate to obtain a semiconductor material without antiphase domain defects, and the surfactant atoms are surfactant atoms compatible with semiconductor technology.

[0013] According to an embodiment of the present disclosure, the materials of the non-inverted domain semiconductor nanowires and the non-inverted domain defect semiconductor nanowire network include compound semiconductors or elemental semiconductors.

[0014] According to an embodiment of the present disclosure, the length of the non-inverted domain semiconductor nanowires and the non-inverted domain defect semiconductor nanowire network is on the order of nanometers to centimeters, the width is on the order of nanometers to micrometers, the height is on the order of nanometers to micrometers, and the area of the non-inverted domain semiconductor nanowires and the non-inverted domain defect semiconductor nanowire network is on the order of nanometers to wafer level.

[0015] The preparation method of the semiconductor material without antiphase domain defects on the CMOS-compatible substrate provided by the embodiment of the present disclosure has at least the following beneficial effects:

[0016] The method disclosed in the present disclosure realizes high-quality selective area epitaxy of materials by regulating the nucleation mode of the materials. The process is simple, and it solves the limitation that the growth of the above materials by traditional methods strongly depends on complex buffer layer technologies. In addition, this method is highly compatible with contemporary mature CMOS manufacturing processes, and the prepared semiconductor materials have no antiphase domain defects, which is expected to improve the performance of electronic devices prepared based on this material. Description of the Drawings

[0017] The connections between the various features of the present disclosure are further described below with reference to the drawings. The drawings are all exemplary. Some features are not shown to scale, and in some drawings, the conventional and non-essential features in the field related to the present disclosure may be omitted, or non-essential features for the present disclosure may be shown additionally. The combinations of the various features shown in the drawings are not used to limit the present disclosure. Additionally, throughout this specification, the content referred to by the same reference numerals is also the same. The specific description of the drawings is as follows:

[0018] Figure 1 A flowchart of a method for preparing a semiconductor material without antiphase domain defects on a CMOS-compatible substrate according to an embodiment of the present disclosure is schematically shown. Detailed Description of the Embodiments

[0019] To make the objectives, technical solutions, and advantages of the present disclosure clearer and more understandable, the present disclosure is further described in detail below with reference to specific embodiments and the drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts fall within the scope of protection of the present disclosure.

[0020] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0021] In the present disclosure, unless otherwise clearly defined and limited, the terms "mounted", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or indirectly connected through an intermediate medium, and it can be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0022] In the description of the present disclosure, it should be understood that the orientation or positional relationship indicated by terms such as "longitudinal", "length", "circumferential", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the subsystems or components referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure.

[0023] Throughout the drawings, the same elements are denoted by the same or similar reference numerals. When it may cause confusion in the understanding of the present disclosure, conventional structures or configurations will be omitted. Moreover, the shapes, sizes, and positional relationships of the components in the drawings do not reflect the true sizes, proportions, and actual positional relationships. Additionally, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claims.

[0024] Similarly, in order to streamline the present disclosure and assist in understanding one or more of the various disclosed aspects, in the above description of the exemplary embodiments of the present disclosure, the various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. The description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0025] Furthermore, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Therefore, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0026] Hereinafter, a method for preparing a semiconductor material without antiphase domain defects on a CMOS-compatible substrate provided by an embodiment of the present disclosure will be explained in detail with reference to specific drawings.

[0027] Figure 1 A flowchart of a method for preparing a semiconductor material without antiphase domain defects on a CMOS-compatible substrate according to an embodiment of the present disclosure is schematically shown.

[0028] As Figure 1 shown, the preparation method may include, for example, operation S110 to operation S130.

[0029] Operation S110: Prepare a periodic pattern on the surface of a CMOS-compatible substrate.

[0030] First, prepare a substrate, such as Si and Ge. These substrates are selected to ensure that the semiconductor material prepared on the substrate meets the requirements of the CMOS process, so that the epitaxial growth technology can be introduced into the manufacture of CMOS devices without significantly modifying the process line. Then, deposit a protective layer on the above-mentioned substrate. The protective layer can be deposited by chemical vapor deposition, physical vapor deposition or atomic layer deposition. These deposition methods are used to ensure that the morphology of the protective layer is uniform and dense, so that the unpatterned positions on the substrate can be fully protected. The role of the protective layer is to protect the surface of the unpatterned positions on the substrate from damage during the pattern etching and surface treatment processes, thus avoiding affecting the migration of adsorbed atoms or molecules. The material of the protective layer is a single metal (for example, metal Al, etc.), an oxide or a nitride (for example, silicon oxide, silicon nitride, aluminum oxide, etc.). These materials are selected to ensure that the protective layer is easily removed in subsequent processes. Finally, use micro-nano processing technology to pattern the protective layer and the substrate to obtain a periodic pattern structure. The patterning is achieved by photolithography and electron beam exposure processes. These processes are selected to ensure that the pattern morphology on the patterned substrate is continuous and has good controllability. Dry etching or wet etching is used to etch the protective layer and the substrate. These two types of etching methods are selected to ensure that the pattern sizes obtained by etching are uniform, thus ensuring that the morphologies of the epitaxial semiconductor nanowires and semiconductor nanowire networks are uniform. The length of the periodic pattern structure ranges from the nanometer scale to the centimeter scale, the width ranges from the nanometer scale to the micrometer scale, and the height is at the nanometer scale. These dimensions are used to control the sizes of the semiconductor nanowires and semiconductor nanowire networks. Operation S110 is an essential key step in the present patented technology.

[0031] Operation S120: Perform selective area epitaxial growth on the surface of the CMOS-compatible substrate based on the periodic pattern. Place the substrate with the periodic pattern structure into the equipment for epitaxial growth of semiconductor materials to obtain semiconductor nanowires and semiconductor nanowire networks. The semiconductor material epitaxial methods include molecular beam epitaxy, chemical beam epitaxy or metalorganic vapor phase epitaxy. These epitaxial methods are selected to ensure that atoms or molecules diffuse and migrate sufficiently on the substrate surface until they reach the pattern positions and stop diffusing and nucleating. The epitaxial semiconductor materials are elemental semiconductors or compound semiconductors (for example: GaAs x Sb 1-x , InAs, InSb, PbTe, ZnTe, AlAs, AlSb, etc.). These semiconductor materials are essential materials for developing semiconductor electronic devices. Operation S120 is also an essential key step in the present patented technology.

[0032] Operation S130: Adjust the period of the periodic pattern and introduce surfactant atoms to obtain a semiconductor material without antiphase domain defects. The semiconductor material without antiphase domain defects includes semiconductor nanowires without reverse domains and a semiconductor nanowire network without antiphase domain defects. The growth mode of the semiconductor nanowires and the semiconductor nanowire network is adjusted by adjusting the length-width spacing of the periodic pattern. Adjusting the pattern period includes adjusting the length-width spacing of the pattern, and the spacing between the length and the width is in the order of nanometers to micrometers. Adjusting the pattern period can change the local growth conditions of the material, so that the semiconductor material changes from island growth to layer growth, achieving the purpose of suppressing antiphase domain defects. At the same time, during the entire growth process of the semiconductor nanowires and the semiconductor nanowire network, surfactant atoms compatible with semiconductor technology are introduced. By using the surfactant effect of these atoms, the diffusion length of the reactant atoms can be adjusted, thereby suppressing the island growth of the semiconductor material and promoting the two-dimensional layer growth of the semiconductor material, ultimately achieving the purpose of suppressing antiphase domain defects. Both of these methods achieve high-quality selective epitaxy of the material by controlling the nucleation mode of the material, solving the limitation that the growth of the above materials by traditional methods strongly depends on complex buffer layer technologies.

[0033] There are no antiphase domain defects in the semiconductor nanowires and the semiconductor nanowire network prepared by the above technology. The materials of the semiconductor nanowires and the semiconductor nanowire network without antiphase domain defects include compound semiconductors or elemental semiconductors. The length of the semiconductor nanowires and the semiconductor nanowire network without antiphase domain defects is in the order of nanometers to centimeters, the width is in the order of nanometers to micrometers, and the height is in the order of nanometers to micrometers. The area of the semiconductor nanowires and the semiconductor nanowire network without antiphase domain defects is from nanoscale to wafer scale.

[0034] To more clearly illustrate the method for preparing a semiconductor material without antiphase domain defects on a CMOS-compatible substrate provided by the embodiments of the present disclosure, a specific example is listed below.

[0035] In this example, the selected substrate material is a Ge substrate, the selected protective layer is amorphous silicon oxide, and the method for depositing the protective layer is plasma-enhanced chemical vapor deposition. The selected exposure method is electron beam exposure, and the electron beam resist is PMMA. The pattern etching method is selected as reactive ion beam etching, and the resist stripping is performed using an oxygen plasma stripper. The semiconductor material is GaAs, and the material epitaxy method is selected as molecular beam epitaxy.

[0036] The specific process is as follows:

[0037] Step (1): Using plasma-enhanced chemical vapor deposition technology, deposit an amorphous silicon oxide layer with a thickness of 10 - 20 nm on the Ge substrate to protect the surface of the Ge substrate from being damaged in subsequent processes, so as to ensure that atoms or molecules have a sufficient diffusion length on the Ge substrate to diffuse to the pattern.

[0038] Step (2): Prepare a Ge substrate with a periodic pattern. Decompose the Ge substrate into an ideal size, spin-coat PMMA electron beam resist on it, and then bake it at 100 - 150 °C for 5 - 10 minutes. Expose the substrate using an electron beam exposure device, develop it with a MIBK:IPA = 1:3 solution for 20 - 40 s, and fix it with an IPA solution for 20 - 40 s to obtain nanowires and a nanowire network pattern with a width of about 50 - 100 nm. Etch the silicon oxide at the pattern position of the substrate using a reactive ion beam etching device, and over-etch by 1 - 2 nm. Obtain a Ge substrate with a periodic pattern.

[0039] Step (3): Using the above steps, adjust the length and width spacing of the periodic pattern, and the length and width spacing is in the order of nanometers to micrometers.

[0040] Step (4): Place the processed substrate with a periodic pattern into a molecular beam epitaxy device for epitaxy of GaAs material. During the growth of the GaAs material, introduce a surfactant Sb. By controlling the period of the pattern and the introduction of the surfactant, it is possible to ensure the epitaxy of high-quality GaAs nanowires and GaAs nanowire networks with a large area, excellent selectivity, uniformity, and no antiphase domain defects on the Ge substrate.

[0041] In summary, the preparation method provided by the embodiments of the present disclosure prepares a periodic pattern structure on the surface of a CMOS-compatible substrate; performs selective area epitaxial growth on the material based on the pattern structure, and obtains semiconductor nanowires without antiphase domain defects and semiconductor nanowire networks without antiphase domain defects by adjusting the pattern period and introducing surfactant atoms. Compared with the traditional method of using a complex buffer layer to reduce the density of antiphase domain defects, the present disclosure realizes high-quality selective area epitaxy of the material by regulating the nucleation mode of the material, and the process is simple. In addition, this method is highly compatible with contemporary mature CMOS manufacturing processes, and the prepared semiconductor material has no antiphase domain defects, which is expected to improve the performance of electronic devices prepared based on this material.

[0042] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present disclosure. It should be understood that the above are only the preferred embodiments of the present disclosure and the technical principles applied. Those skilled in the art will understand that the present disclosure is not limited to the specific embodiments described here, and various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present disclosure. Therefore, although the present disclosure has been described in more detail through the above embodiments, the present disclosure is not limited to the above embodiments. Without departing from the concept of the present disclosure, more other equivalent embodiments can be included, all of which belong to the protection scope of the present disclosure.

Claims

1. A method for preparing a semiconductor material without anti-phase domain defects on a CMOS compatible substrate, comprising: Fabricating a periodic pattern on a CMOS compatible substrate surface; Performing selective epitaxial growth on the surface of the CMOS compatible substrate based on the periodic pattern; The period of the periodic pattern is adjusted and surfactant atoms are introduced to obtain a semiconductor material without anti-phase domain defects. The semiconductor material without anti-phase domain defects includes semiconductor nanowires without anti-phase domain defects and a semiconductor nanowire network without anti-phase domain defects.

2. The preparation method according to claim 1, characterized in that: The CMOS compatible substrate includes a silicon substrate and a germanium substrate.

3. The preparation method according to claim 1, characterized in that: The method of preparing a periodic pattern on the surface of a CMOS compatible substrate comprises: Depositing a protective layer on the CMOS compatible substrate; The protective layer and the CMOS compatible substrate are patterned and etched to obtain the periodic pattern.

4. The preparation method according to claim 3, characterized in that: The step of depositing a protective layer on the CMOS compatible substrate comprises: A protective layer is deposited on the CMOS compatible substrate by chemical vapor deposition, physical vapor deposition or atomic layer deposition.

5. The preparation method according to claim 3, characterized in that: The step of patterning the protective layer and the CMOS compatible substrate to obtain the periodic pattern comprises: Patterning the protective layer and the CMOS compatible substrate by electron beam exposure or photolithography; The protective layer and the CMOS compatible substrate are etched by dry etching or wet etching.

6. The preparation method according to claim 1, characterized in that: The selective epitaxial growth on the surface of the CMOS compatible substrate based on the periodic pattern comprises: The selective epitaxial growth is performed on the surface of the CMOS compatible substrate by means of molecular beam epitaxy, chemical beam epitaxy or metal organic vapor phase epitaxy.

7. The preparation method according to claim 1, characterized in that: The periodic pattern has a length of nanometer to centimeter level, a width of nanometer to micrometer level, and a height of nanometer level.

8. The preparation method according to claim 1, characterized in that: The step of adjusting the period of the periodic pattern and introducing surfactant atoms to obtain a semiconductor material without antiphase domain defects comprises: Adjusting the length and width spacing between the periodic patterns, wherein the length and width spacing is in the order of nanometers to micrometers; In the process of performing selective area epitaxy on the surface of the CMOS compatible substrate, surfactant atoms are introduced to obtain a semiconductor material without antiphase domain defects, wherein the surfactant atoms are surfactant atoms compatible with semiconductor technology.

9. The preparation method according to claim 1, characterized in that: The materials of the semiconductor nanowires without anti-phase domain defects and the semiconductor nanowire network without anti-phase domain defects include compound semiconductors or single-element semiconductors.

10. The preparation method according to claim 1, characterized in that: The length of the semiconductor nanowires without inversion domains and the semiconductor nanowire network without inversion domain defects is in the order of nanometers to centimeters, the width is in the order of nanometers to micrometers, and the height is in the order of nanometers to micrometers. The area of ​​the semiconductor nanowires without inversion domains and the semiconductor nanowire network without inversion domain defects is in the order of nanometers to wafers.

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