Integrated circuit with silicide formation barrier

Abstract

The invention relates to an integrated circuit with a silicide formation barrier. A method of forming an integrated circuit by forming (1004) a first silicon body having a first silicon surface; forming (1004) a second silicon body having a second silicon surface; forming (1006) a first silicide barrier layer along the first silicon surface and along the second silicon surface; and forming (1008) a second silicide barrier layer along the first silicide barrier layer. The forming each of the first silicide barrier layer and the second silicide barrier layer includes forming a plasma enhanced chemical vapor deposition (PECVD) layer, and exposing the PECVD layer to a rare gas for a duration of time. Subsequently, the method removes (1012) a portion of the second silicide barrier layer and an underlying portion of the first silicide barrier layer to expose the first silicon surface while leaving at least the first silicide barrier layer on the second silicon surface, and silicides (1014) the first silicon surface.

Description

[0001] Cross - Reference to Related Applications

[0002] This application is related to U.S. Provisional Application No. 63 / 604,137, filed on November 29, 2023 (Attorney Docket No. T103415US01), the entire content of which is incorporated herein by reference. Technical Field

[0003] The described examples relate to integrated circuits (ICs) and fabrication, and more specifically but not exclusively to an IC including a silicide formation blocking structure and / or method. Background Art

[0004] Silicide combines silicon and another element (usually a metal), typically forming a metal silicide as a conductive layer in an IC. Silicide can be used in many locations in a metal oxide semiconductor (MOS) device, such as in a MOS field effect transistor (MOSFET), for example, on either a polysilicon gate or a transistor source / drain region. Silicide can also be formed on an IC polysilicon resistor. Silicide is sometimes formed in selective locations, where selectivity is achieved by forming a blocking structure (or barrier) on certain silicon surfaces while leaving other surfaces exposed, such that subsequent silicide formation occurs only on the exposed surfaces. The blocking structure can be referred to as a silicide blocker, which can be abbreviated as SiBLK.

[0005] In some methods, an SiBLK is formed by depositing bis(tert-butylamino)silane (BTBAS) nitride in a furnace. BTBAS SiBLK formation can provide certain benefits, such as a relatively high tolerance to subsequent hydrofluoric acid (HF) etching and an acceptable level of surface conformality. Conversely, BTBAS SiBLK can have various drawbacks, such as relatively high cost, very finicky chemicals, and lengthy and / or high heating requirements that can negatively impact other IC structures. While the prior art can be implemented in various baseline devices, examples are provided herein that can improve certain of the above concepts, as detailed below. Summary of the Invention

[0006] In an example, there is a method of forming an integrated circuit. The method includes: forming a first silicon surface, forming a second silicon surface, forming a first silicide barrier layer along the first silicon surface and along the second silicon surface, and forming a second silicide barrier layer along the first silicide barrier layer. Forming each of the first silicide barrier layer and the second silicide barrier layer includes forming a plasma enhanced chemical vapor deposition (PECVD) layer and exposing the PECVD layer to a noble gas for a duration. Subsequently, the method removes a portion of the second silicide barrier layer and a underlying portion of the first silicide barrier layer to expose the first silicon surface, while leaving at least the first silicide barrier layer on the second silicon surface, and siliciding the first silicon surface.

[0007] Other aspects are also described and claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a plan and partial view of a semiconductor device as part of an example including a resistor 104R and a transistor 106T.

[0009] Figures 2 to 6 , 7A, 7B, and 7C and 8 are cross-sectional views showing Figure 1 successive fabrication stages of a semiconductor structure and the resulting structure.

[0010] Figure 9A and 9B are cross-sectional views showing additional fabrication stages and the resulting structure, taken along Figure 1 different cross-sectional lines of the semiconductor structure.

[0011] Figure 10 is a flow chart of an example method for fabricating a semiconductor structure. DETAILED DESCRIPTION

[0012] Examples are described with reference to the accompanying drawings. The drawings are provided for illustrative purposes and may not be drawn to scale. Several aspects are described with reference to example applications for illustration, where like features correspond to like reference numerals. In Figure 1 and each subsequent drawing, two or more dimensions are shown and indicated in an x-y-z coordinate space, where in Figure 1The figure shows a plan view in the x-y plane, but it should be understood that it also has features in the z dimension and is understood to extend in a direction out of the shown image plane. The directional references are for the purpose of relative placement, but these terms are not intended to be restrictive as the device can be rotated in space, thereby changing the absolute reference rather than the relative reference. Many specific details, relationships, and methods are set forth to provide an understanding, but the scope is not necessarily limited by the shown order of acts or events as some acts may occur in a different order and / or concurrently with other acts or events. Additionally, all of the acts or events shown may not be required in one or more instances to implement the method.

[0013] The examples relate to semiconductor integrated circuit (IC) fabrication and, more specifically but not exclusively, to an IC that includes multiple silicon surfaces, where at least one silicon surface is ultimately silicided while another silicon surface is prevented from being silicided. For example, in the fabrication of an IC with multiple devices (such as resistors and transistors) on the same substrate, portions of the resistor body and one or more surfaces of the transistors can provide the aforementioned multiple silicon surfaces. Examples are provided herein that can improve certain concepts among the above concepts, as detailed below. Although these examples can be expected to provide various advantages as described above, a specific result is not required unless explicitly recited in a particular claim.

[0014] Figure 1 is a plan and partial view of a semiconductor device 100 (e.g., a part of an IC). The semiconductor device 100 includes a semiconductor substrate 102, such as a part of a silicon wafer. This wafer typically contains multiple locations, each corresponding to the same or different ICs on the wafer, and thus can be repeated at each wafer IC location Figure 1 (and the subsequent figures). The wafer typically provides a p-type or n-type semiconductor, and the semiconductor substrate 102 can represent a part of a bulk wafer or a region formed in combination with the wafer (e.g., wells and / or buried layers and / or epitaxial layers). As detailed in the remaining figures, a resistor region 104 and an active device region (shown by way of example as a transistor region 106) are provided, ultimately forming examples of a corresponding resistor 104R and a transistor 106T that are combined with the semiconductor substrate 102. The resistor 104R and the transistor 106T are represented by Figure 1 certain general features and corresponding regions therein, and additional details, options, and properties will be described later. Ultimately, the figures and the corresponding description provide examples that can provide one or more benefits, such as selective silicidation of such structures, with potential improvements in any one or more of the sufficient resistance to varying HF wet etching rates, SiBLK conformality, particle defect rate, chemical cost, and thermal budget.

[0015] Resistor 104R includes a polysilicon structure 110 (e.g., polysilicon or polysilicon germanium) having a major axis in the x-dimension. The polysilicon structure 110 includes a polysilicon resistor body 112 and opposite first and second ends 114 and 116. The polysilicon resistor body 112 can have a length from 0.2 μm to 100 μm and a width (in the y-dimension) in the range from 0.03 μm to 50 μm. In fact, when the width tends towards the lower value within this range, one or more benefits described later can be achieved. Each of the ends 114 and 116 has a length (in the x-dimension) that can be in the range from 0.03 μm to 0.25 μm and a width (in the y-dimension) that can be in the range from 0.03 μm to 50 μm. Note that the widths of the ends 114 and 116 are shown as being greater than the width of the polysilicon resistor body 112, where a greater end width can be implemented to accommodate the sizes of the contacts 118 and 120, as further described below. And, by way of example, formed in the same step as the polysilicon structure 110, for example by appropriate masking and etching and also from the same polysilicon layer, are one or more dummy polysilicon features 122 and 124, which are, for example, parallel to the respective sidewalls of the polysilicon resistor body 112 and equally opposite and spaced apart from the respective sidewalls. Each of the dummy polysilicon features 122 and 124 can have the same width, which can be slightly less than the width of the polysilicon resistor body 112. The dummy polysilicon features 122 and 124 are not part of the resistance realized via the resistor 104R itself, but can be implemented as part of good or best practice for width control of the polysilicon resistor body 112, for example to affect the plasma etching of the polysilicon material that forms the polysilicon resistor body 112.

[0016] The polysilicon resistor body 112 and its ends 114 and 116 generally provide the resistance of resistor 104R, and the resistance can be accessed by various conductive structures. For example, SiBLK 126 is formed over most of the exposed x / y plane regions of the polysilicon resistor body 112 (as well as over most of the exposed x / y plane regions of dummy polysilicon features 122 and 124). After forming SiBLK 126, various silicide regions are formed, for example, by siliciding the exposed (not blocked by SiBLK 126) polysilicon, resulting in body silicide 128 over the exposed portion of the polysilicon resistor body 112, and first end silicide 130 and second end silicide 132 over the first end 114 and the second end 116, respectively. Accordingly, in the x-y plane, resistor 104R has a partially silicided upper surface. For example, between the first end 114 and the second end 116, the silicide covers a range from 0.2% to 70% of the x / y plane area of resistor 104R, and the remainder is not silicided. After forming the silicides, conductive contacts 118 and 120 are formed. Each of conductive contacts 118 and 120 extends in the z dimension to a respective one of the first end silicide 130 and the second end silicide 132. Contacts 118 and 120 conduct electrically to respective metal layer portions 134 and 136 and can also be part of the respective metal layer portions, which may extend much further in the y dimension than Figure 1 shown. Thus, the resistance provided by resistor 104R can be electrically accessed by coupling to each of metal layer portions 134 and 136.

[0017] Transistor 106T includes trench 140, shown by the dashed line to indicate that it is a predefined region where transistor source / drain regions are formed on opposite sides of transistor gate 142, as further described below. Trench 140 may include one or more doped regions, typically all having the same conductivity type but possibly having different dopant concentrations. For example, semiconductor substrate 102 may have a first conductivity type (e.g., p-type), and trench 140 may include a conductivity type opposite or complementary to that of semiconductor substrate 102 (e.g., n-type). Other alternatives or variations (e.g., buried layers, epitaxial layers, wells, etc.) are understood in the art. As detailed in commonly assigned U.S. Application No. 18 / 345,873, filed Jun. 30, 2023, titled "ZERO TEMPCO RESISTOR WITH SELECTIVE DOPING" and U.S. Application No. 18 / 345,833, filed Jun. 30, 2023, titled "ZERO TEMPCO RESISTOR" (the entire disclosures of both applications are incorporated herein by reference), in some instances, the same dopant implant may also be introduced into some or all of trench 140 and resistor 104R polysilicon structure 110 with or without a non-dopant co-implant species (e.g., carbon, nitrogen).

[0018] Transistor gate 142 includes polysilicon transistor gate 144, which is enclosed within the Figure 1 dashed perimeter shown in, as polysilicon transistor gate 144 is not directly visible in the Figure 1 perspective view. Specifically, Figure 1 the perspective view shows that polysilicon transistor gate 144 is covered by gate silicide 146 formed above (in the z-dimension) polysilicon transistor gate 144. In an example, polysilicon transistor gate 144 is formed in the same polysilicon formation / masking and etching steps as resistor 104R polysilicon structure 110.

[0019] The various regions of transistor 106T may be accessed by various conductive structures. For example, while gate silicide 146 is being formed, source / drain silicide may be formed within the perimeter of trench 140, but at the Figure 1Invisible in [figure reference], because they are below other shown structures. Specifically, after forming the gate silicide 146, conductive contacts 148 are formed to extend in the z-dimension, e.g., to one end of the polysilicon transistor gate 144 / gate silicide 146 that extends beyond the x / y perimeter of the trench 140. The conductive contacts 148 conduct electrically to the metal layer portion 150 and can also be part of the metal layer portion. Similarly, a first conductor group 152 including one or more conductive contacts is formed on the first side of the polysilicon transistor gate 144 and extends downward in the z-dimension to the first source / drain silicide, and is again invisible in [figure reference] (see 902 of [figure reference]). And, a second conductor group 154 including one or more conductive contacts is formed on the second side of the polysilicon transistor gate 144 opposite the first side and extends downward in the z-dimension to the second source / drain silicide, and is again invisible in [figure reference] (see 904 of [figure reference]). Accordingly, the first conductor group 152 can be in electrical communication with the first source / drain region in the trench 140 (see 506 in [figure reference]), and the second conductor group 154 can be in electrical communication with the second source / drain region in the trench 140 (see 508 in [figure reference]). Finally, the first conductor group 152 conducts to the metal layer portion 156 and can also be part of the metal layer portion, and the second conductor group 154 conducts to the metal layer portion 158 and can also be part of the metal layer portion. Figure 1 in [figure reference] Figure 9A 902). And, a second conductor group 154 including one or more conductive contacts is formed on the second side of the polysilicon transistor gate 144 opposite the first side and extends downward in the z-dimension to the second source / drain silicide, and is again invisible in [figure reference] Figure 1 in [figure reference] Figure 9A 904). Accordingly, the first conductor group 152 can be in electrical communication with the first source / drain region in the trench 140 (see 506 in [figure reference]), and the second conductor group 154 can be in electrical communication with the second source / drain region in the trench 140 (see 508 in [figure reference]). Figure 5 506) of [figure reference], and the second conductor group 154 can be in electrical communication with the second source / drain region in the trench 140 (see Figure 5 508) of [figure reference]. Finally, the first conductor group 152 conducts to the metal layer portion 156 and can also be part of the metal layer portion, and the second conductor group 154 conducts to the metal layer portion 158 and can also be part of the metal layer portion.

[0020] Figures 2 to 9B is, for example, a cross-sectional view in the -x dimension (y-z plane) across Figure 1 that represents the successive fabrication stages and resulting structures of the semiconductor device 100 of [figure reference]. However, for simplicity of illustration and description, the dummy polysilicon features 122 and 124 of [figure reference] are not shown. In [figure reference], the semiconductor device 100 is provided at an early fabrication stage. The semiconductor device 100 includes a semiconductor substrate 102, e.g., as part of a silicon wafer. This wafer typically contains multiple locations, each corresponding to the same or different ICs on the wafer, and thus the Figure 1 can be repeated at each wafer IC location Figure 1 process. In [figure reference], the semiconductor device 100 is provided at an early fabrication stage. The semiconductor device 100 includes a semiconductor substrate 102, e.g., as part of a silicon wafer. This wafer typically contains multiple locations, each corresponding to the same or different ICs on the wafer, and thus the Figure 2 process can be repeated at each wafer IC location. Figure 2Illustration of (and subsequent figures). The wafer typically provides a p-type or n-type semiconductor, and the semiconductor substrate 102 may represent a portion of a bulk wafer or a region formed in combination with the wafer (e.g., a well, buried layer, or epitaxial layer). As described above, and detailed in the remaining figures, the semiconductor substrate 102 includes a resistor region 104 and a transistor region 106, ultimately forming examples of a resistor 104R and a transistor 106T therein, respectively. Finally, these figures and the corresponding descriptions provide any one or more of certain benefits related to silicide blocks for selective silicidation.

[0021] Figure 2 Shows a polysilicon resistor body 112 and a polysilicon transistor gate 144. Before forming those structures, a surface isolation structure 202, such as a shallow trench isolation (STI) structure, is formed in a portion of the upper surface 102US of the semiconductor substrate 102 corresponding to the resistor region 104. The surface isolation structure 202 is shown as an STI structure having a thickness in the range of 150 nm to 600 nm, for example, and it can electrically isolate the resistor 104R from the substrate 102 later. Alternative isolation methods can also be used, such as different insulators, local oxidation of silicon (LOCOS) structures, or doped well regions. Subsequently, a threshold voltage (Vt) implantation can be applied to the semiconductor substrate 102, where the dopant type and energy are selected to ultimately adjust the Vt of the transistor 106T, while the surface isolation structure 202 substantially prevents the implanted dopants in the substrate 102 from affecting the resistor in the resistor region 104.

[0022] Figure 2 Also shown is a gate oxide 204OX formed of an oxide layer (not fully shown), which is formed by oxidizing the remaining exposed portion of the upper surface 102US across a portion of the upper surface 102US where, for example, the surface isolation structure 202 is not located. The gate oxide 204OX forming layer may have a thickness of 1 nm to 5 nm. Subsequently, a polysilicon layer is deposited on top of the entire structure shown, conforming to the upper surface 202US of the gate oxide 204OX forming layer and the surface isolation structure 202. The polysilicon layer may be undoped when deposited, or in some instances may be in-situ doped and / or doped by implantation, and it is patterned and etched to form the polysilicon resistor body 112 and the polysilicon transistor gate 144.

[0023] At Figure 3In it, a relatively light dopant implantation, commonly referred to as a lightly doped drain (LDD) implantation, is performed to form a corresponding LDD region 302 below the upper surface 102US. The LDD region is self-aligned with the gate oxide 204OX (and at one end of the transistor 106T, is also self-aligned with the lateral edge of the surface isolation structure 202). The LDD implantation is typically provided at an energy lower than that of the NSD or PSD implantation, and it is selected to have a dopant type corresponding to the desired conduction type of the transistor 106T. For example, for an n-type metal oxide semiconductor (NMOS) transistor, the LDD implantation has an n-type dopant (e.g., arsenic, boron, and / or indium pocket implantation, with an optional germanium pre-amorphization implantation (PAI)), such as arsenic with an energy in the range of 1 keV to 2 keV and a dose in the range of 2e14 to 2e15 atoms / cm 2 range, boron with an energy in the range of 3 keV to 12 keV and a dose in the range of 1e13 to 1e14 atoms / cm 2 range and tilted 0 to 35 degrees and rotated two or four times, and / or indium with an energy in the range of 10 keV to 45 keV and a dose in the range of 1e13 to 1e14 atoms / cm 2 range. As an alternative example, for a p-type metal oxide semiconductor (PMOS) transistor, the LDD implantation has a p-type dopant (e.g., BF 2 (difluoroboron), boron, and / or indium or germanium PAI), such as fluorine with an energy in the range of 1 keV to 5 keV and a dose in the range of 1e14 to 4e15 atoms / cm 2 range, BF 2 with an energy in the range of 1 keV to 5 keV and a dose in the range of 5e14 to 5e15 atoms / cm 2 range, boron with an energy in the range of 0.3 keV to 2 keV and a dose in the range of 5e14 to 5e15 atoms / cm 2 range, and / or indium PAI with an energy in the range of 2 keV to 15 keV and a dose in the range of 1e13 to 5e14 atoms / cm 2 range, or germanium PAI with an energy in the range of 5 keV to 20 keV and a dose in the range of 1e13 to 5e14 atoms / cm 2 range. The PMOS LDD may also include an arsenic / antimony pocket implantation with a dose in the range of 1e13 to 1e14 atoms / cm in the range of 20 keV to 60 keV, or a germanium PAI with a dose in the range of 1e13 to 1e14 atoms / cm in the range of 10 keV to 40 keV 2 range, or an arsenic / antimony pocket implantation with a dose in the range of 1e13 to 1e14 atoms / cm in the range of 10 keV to 40 keV 2Phosphorus pocket implants of doses within the range. During LDD implantation, the polysilicon resistor body 112 (and the entire polysilicon structure 110) may or may not be masked based on the desired result of resistor 104R. If the resistor body 112 (and the polysilicon structure 110) is not masked, within the range where most dopants are involved, the final resistor 104R may have the same dopant type as the LDD implantation. For example, if the LDD implantation is n-type (sometimes called NLDD), then resistor 104R may also be n-type, or in a complementary manner, if the LDD implantation is p-type (sometimes called PLDD), then resistor 104R may also be p-type.

[0024] In Figure 4 In Figure 3 layer 402 (or individual layers) is formed over the structure of

[0025] In Figure 5 In Figure 4 layer 402 of Figure 4a portion of layer 402 (or if layer 402 comprises multiple layers, a portion from one or more of the layers). After forming the spacer 504, source / drain dopant implantation is performed. In the transistor region 106, the source / drain implantation forms corresponding first transistor source / drain regions 506 and second transistor source / drain regions 508 below the upper surface 102US, and the first transistor source / drain regions and the second transistor source / drain regions are self-aligned with the spacer 504 (and for the first source / drain region 506, also self-aligned with the surface isolation structure 202). In the resistor region 104, the source / drain implantation provides the selected dopant into the polysilicon structure 110, including the polysilicon resistor body 112 shown. The source / drain implantation can be n-type (referred to as NSD) or p-type (referred to as PSD), and is selected to have a dopant type corresponding to the desired conduction type of the transistor 106T. As an example of NSD implantation, a combination of arsenic and phosphorus dopants is used, with the energy of arsenic being 5 keV to 35 keV and the dose range being 5e14 to 5e15 atoms / cm 2 , and the energy of phosphorus being 1 keV to 10 keV and the dose range being 5e14 to 5e15 atoms / cm 2 . As an example of PSD implantation, boron dopant is used, with its energy being 1 keV to 10 keV and the dose range being 5e14 to 1e16 atoms / cm 2 , and indium PAI can be optionally added, with its energy being 2 keV to 20 keV and the dose range being 5e13 to 5e14 atoms / cm 2 . The implantation also has a relatively high concentration, for example, generating an initial average dopant concentration of 1e19 / cm 3 to 6e21 / cm 3 in the polysilicon transistor gate 144 and the polysilicon resistor body 112.

[0026] In Figure 6 , the etch stop layer 602 is formed, for example, of silicon oxynitride (SiON) by depositing it over the entire semiconductor device 100. The etch stop layer 600 can have a thickness selected from the range of 3 nm to 10 nm. In an example, the SiON is formed by a PECVD process using silane (SiH 4 ), nitrous oxide (N 2 O), helium (He), and high frequency radio frequency (RF) power.

[0027] In Figures 7A - 7C , corresponding layers are formed over portions of the polysilicon resistor body 112 to create the SiBLK 126, as previously introduced in Figure 1 (as ultimately shown in Figure 8 ). In Figures 7A - 7CIn the illustrated example, a total of N such layers are formed successively, and these layers are combined to provide an accumulation layer, which is then etched to produce SiBLK126, as further described below. Each of the N layers has a sufficiently high conformality metric on both vertical (e.g., x-z plane) and horizontal (e.g., x-y plane) surfaces.

[0028] In Figure 7A , a first SiBLK layer 702 is formed over the entire illustrated structure and accordingly in both the resistor region 104 and the transistor region 106, and an etch stop layer 602 is formed along Figure 6 . Thus, for each of the polysilicon resistor body 112 and the polysilicon transistor gate 144, the first SiBLK layer 702 is substantially conformal with respect to the sidewalls (e.g., in the x-z plane) of each polysilicon structure and the horizontal surfaces (e.g., in the x-y plane) of each polysilicon structure while being separated by the etch stop layer 602. For example, the thickness of the first SiBLK layer 702 along the sidewall of any polysilicon structure sidewall is at least 75% of the thickness of the first SiBLK layer 702 along the upper horizontal surface of any polysilicon structure (exhibiting an overall conformality of 75% or greater). Additionally, in the example, the first SiBLK layer 702 is silicon nitride. Also in the example, the first SiBLK layer 702 is formed in a cycle comprising two steps. In the first step, the SiBLK layer 702 is deposited by chemical vapor deposition (CVD) and further by plasma enhanced CVD (PECVD), for example, within a chamber temperature range of 350 °C to 550 °C and at an RF power within the range of 50 watts to 100 watts. PECVD may use ammonia (NH3) as the nitrogen precursor and silane (SiH4) as the silicon precursor, where the plasma serves as a catalyst to react the gases and deposit the first SiBLK layer 702. The deposition thickness may be less than 2 nm, for example, within the range of 1 nm to 2 nm. In the second step, the deposited layer is treated by continuous exposure to a plasma containing one or more noble gases (such as argon and / or helium) for a period of 10 seconds to 30 seconds. Other noble gases may include elements in the Group 18 element column, including, for example, neon, krypton, and xenon. The treatment step is considered to further densify and improve the silicon / nitrogen bonding in the first SiBLK layer 702. It is also worth noting that compared to the baseline formation of silicide barriers using the BTBAS process, a heat treatment below 30 seconds presents a significantly reduced amount of heat load, occurring either alone or also with the possibility of a lower temperature.

[0029] In Figure 7B , a second SiBLK layer 704 is formed over the entire illustrated structure and accordingly in both the resistor region 104 and the transistor region 106, and along Figure 7AThe first SiBLK layer is formed. In an example, except for positioning, the second SiBLK layer 704 is formed in the same cyclic manner as the first SiBLK layer 702. Thus, within the same scope described above, PECVD deposition of the second SiBLK layer 704 is performed in the first step and it is processed in the second step. In an example, the specific values within each scope remain the same for each repeated cycle. Additionally, the second SiBLK layer 704 also achieves a desirable conformality (e.g., 75% or greater) comparable to that of the first SiBLK layer 702. Thus, the first SiBLK layer 702 and the second SiBLK layer 704 aggregate with a combined thickness of each layer, e.g., two 1.6 nm layers provide a total 3.2 nm silicon nitride layer.

[0030] In Figure 7C , the final SiBLK layer 706 is formed over the entire structure shown and accordingly in both the resistor region 104 and the transistor region 106, and is formed along any previously formed SiBLK layers, a total of N SiBLK layers. Except for positioning, the final SiBLK layer 706 (as with the SiBLK layers between it and the etch stop layer 602) is formed in the same corresponding cyclic manner as those previous layers. Thus, within the same scope described above, PECVD deposition of the final SiBLK layer 706 is performed in the first step and it is processed in the second step. The value of N, i.e., the desired number of the same deposition / processing cycles, can be determined based on the target total thickness across all N layers, which all combine to form a layer stack that is part or all of the entire SiBLK structure. Additionally, each of the N SiBLK layers can achieve a desirable and comparable conformality (e.g., 75% or greater) and can exhibit a detectable interface between it and an adjacent SiBLK layer.

[0031] In Figure 8 a, an etch mask 802 (e.g., photoresist) is formed over and across the stack of N SiBLK layers 702, 704,..., 706 from Figures 7A - 7C . The shape and positioning of the etch mask 802 are such as to produce a resulting SiBLK portion that remains over a selective portion of the polysilicon resistor body 112 so as to correspond to the position of the SiBLK 126 of Figure 1 . Next, silicon nitride etching (e.g., dry etching) is performed downward (in the z - dimension) to the etch stop layer 602, thereby removing portions of the SiBLK layers 702, 704,..., 706 in regions other than those masked by the mask 802.

[0032] Figure 9A and 9Bshows the results of a series of subsequent steps, which are shown in cross-section in the y-dimension at the positions shown. Specifically, for example, a wet etch is used to remove a portion of the etch stop layer 602 that remains after the SiBLK etch of Figure 1 . As a possible advantage of the foregoing step, the SiBLK 126 in Figure 8 is particularly resistant to wet etching (e.g., in the case where the etch includes hydrofluoric acid). Thus, due to the beneficial integrity of the SiBLK 126 in its resistance to wet etching, the subsequent silicidation boundary adjacent to the SiBLK 126 can be improved. Subsequently, for example, an ashing etch is used to remove the etch mask 802. Thus, in Figure 9A , the portions of the SiBLK layers 702, 704,..., 706 that were previously masked in Figure 8 are retained, while no such portions are retained in Figure 9B because there is no etch mask at the position of the perspective view shown. Additionally, the retained SiBLK portions (from layers 702, 704, 706) cumulatively provide the SiBLK 126 of Figure 1 . Thus, the silicide blocking function of the SiBLK 126 is only in the selective positions of the polysilicon resistor body 112 and does not cover the polysilicon transistor gate 144, whereby the exposed polysilicon surface provides the regions in which subsequent silicides are to be formed. Continuing in Figure 9A and 9B , a silicidation step is performed to form silicides on the exposed polysilicon structures. Specifically, the gate silicide 146 introduced in Figure 1 is formed along the polysilicon transistor gate 144, while the first source / drain silicide 902 and the second source / drain silicide 904 are formed along the first transistor source / drain region 506 and the second transistor source / drain region 508, respectively. At the same time, in the dimension shown in Figure 9A , the SiBLK 126 prevents a portion of the polysilicon resistor body 112 from being silicided, while any portion of the polysilicon resistor body 112 that is not covered by the SiBLK 126 (as shown beyond the outer boundary of the SiBLK 126 in the x-y plane in Figure 1 and as shown in Figure 9B ) will receive silicide; correspondingly, Figure 9B shows the addition of the body silicide 128 of Figure 1 .

[0033] Figure 10 is a flowchart of an example method 1000 that outlines various of the foregoing steps for manufacturing the semiconductor device 100 as shown, for example, in Figure 9A and 9B . The method 1000 begins at step 1002, where Figure 1 is obtained.Figure 1 A semiconductor substrate 102. The semiconductor substrate 102 at this stage can be a bare wafer or may have one or more semiconductor features already formed thereon. The semiconductor substrate 102 also includes one or more regions or one or more electrical structures adjacent to such regions, where it is desired to form semiconductors or silicon containing devices such as resistor 104R and transistor 106T. Next, in step 1004, a first silicon surface and a second silicon surface are formed. For example, the first silicon surface can be a polysilicon transistor gate 144 or source / drain regions 506 and 508, and the second silicon surface can be a resistor body 112. Next, in step 1006, a first silicide blocking layer is formed relative to the first silicon surface and the second silicon surface. For example, the first silicide blocking layer can include a first SiBLK layer 702 alone or in combination with an etch stop layer (e.g., etch stop layer 602). Next, in step 1008, the next (e.g., second) silicide blocking layer is formed along the first silicide blocking layer. For example, the second silicide blocking layer can include a second SiBLK layer 704. Next, step 1010 determines whether an additional silicide blocking layer is to be implemented, and if so, method 1000 returns to step 1008 and the next silicide blocking layer is formed along the previously formed silicide blocking layer. If step 1010 determines that an additional silicide blocking layer is to be implemented, method 1000 returns to step 1008, otherwise it proceeds to step 1012. Accordingly, one or more silicide blocking layers are formed, each silicide blocking layer including PECVD formation and noble gas exposure. In step 1012, a portion of the second (and any additional subsequent) silicide blocking layer and the underlying portion of the underlying first silicide blocking layer are removed to expose the first silicon surface while leaving at least the first silicide blocking layer above the second silicon surface. Next, in step 1014, the first silicon surface exposed in step 1012 is silicided. For example, the silicide formed can be a gate silicide 146 (or, to the extent that the resistor end of the polysilicon resistor body 112 is exposed (if it occurs), a body silicide 128). Subsequently, step 1016 generally indicates that after step 1014, additional structures can be formed in combination with transistors, resistors, and interconnects to these and other devices associated with the semiconductor substrate of step 1002.

[0034] Based on the foregoing, those skilled in the art will appreciate that, for example, an example for semiconductor IC manufacturing is provided relative to an IC that includes a silicide blocking structure (e.g., one that includes both a polysilicon resistor and other active devices (e.g., transistors)) implemented therein. Such examples provide various benefits, some of which are described above and still include other benefits. Some examples may include a silicide blocking structure that uses any one or more of lower temperature, shorter thermal cycle exposure, reduced chemical hazards and costs, and sufficient layer conformality. As another example, one or more of the process variables described herein (e.g., deposition power; processing time, etc.) can be tuned in order to adjust layer stack properties (e.g., thickness and HF wet etch rate), while still achieving an acceptable structure and accommodating specific device requirements. Other benefits can also be achieved, including one or more of a reduced layer defect rate and reduced manufacturing costs (e.g., per wafer). Thus, while industrial baseline processes may use other chemical substances or combinations of formulations, the silicide blocker formation of the present invention describes a reverse teaching of the combinations resulting from possible industrial inertia or practice goals, or provides alternatives thereto, thereby providing an alternative and generally sufficiently comprehensive set of advantages for a specific IC implementation. In fact, as IC sizes decrease, baseline methods may cause other problems, such as the formation of undesirable layer shapes (e.g., breadloafing) between closely spaced polysilicon structures, such as where the geometric spacing between adjacent polysilicon structures is 65 nm or less. The teachings of the present invention may also prove more advantageous in such more closely spaced applications. Within the scope of the appended claims, other additional modifications to the described examples are possible, and other examples are possible.

Claims

1. A method of forming an integrated circuit, comprising: forming a first silicon surface; forming a second silicon surface; forming a first silicide blocking layer along the first silicon surface and along the second silicon surface; forming a second silicide blocking layer along the first silicide blocking layer, wherein forming each of the first silicide blocking layer and the second silicide blocking layer comprises: forming a plasma enhanced chemical vapor deposition (PECVD) layer; and exposing the PECVD layer to a noble gas for a duration; removing a portion of the second silicide blocking layer and an underlying portion of the first silicide blocking layer to expose the first silicon surface while leaving at least the first silicide blocking layer above the second silicon surface; as well as After the removing step, the first silicon surface is silicidized. 2 . The method of claim 1 , wherein the first silicon surface comprises a transistor gate or source / drain region and the second silicon surface comprises a resistor body. The method of claim 2 , wherein the transistor gate has a width of 65 nm or less. 4 . The method of claim 1 , wherein each of the first silicide blocking layer and the second silicide blocking layer has the same thickness.

5. The method according to claim 4, wherein the same thickness is to within the range.

6. The method of claim 1 , further comprising forming an integer number N of continuous silicide blocking layers relative to the second silicide blocking layer, wherein each of the continuous silicide blocking layers is formed along a corresponding and previously formed one of the second or other of the continuous silicide blocking layers. 7 . The method of claim 6 , wherein each of the first silicide blocking layer and the second silicide blocking layer and the integer N consecutive silicide blocking layers have the same thickness.

8. The method according to claim 7, wherein the same thickness is to within the range.

9. The method of claim 1, wherein the noble gas is selected from the group consisting of argon and helium.

10. The method of claim 1, wherein the duration is in the range of 1 second to 20 seconds.

11. The method of claim 10, wherein each of the steps of forming a PECVD layer and exposing the PECVD layer is performed in a chamber having a temperature in a range between 350°C and 550°C.

12. The method of claim 1, wherein the removing step comprises removing the portion using hydrofluoric acid.

13. The method of claim 1, wherein each of the first silicide blocking layer and the second silicide blocking layer comprises silicon nitride.

14. The method of claim 1, wherein each of the first silicide barrier layer and the second silicide barrier layer has a conformality of at least 75%.

15. A method of forming an integrated circuit, comprising: forming a plurality of silicide blocking layers over the first silicon surface and the second silicon surface by a process comprising, for each of the plurality of silicide blocking layers, depositing a respective layer by plasma enhanced chemical vapor deposition and then exposing the respective layer to a noble gas for a duration; removing a portion of one or more of the plurality of silicide blocking layers to expose the first silicon surface while leaving the second silicon surface blocked by the plurality of silicide blocking layers; as well as The first silicon surface is silicided.

16. An integrated circuit IC, comprising: a first silicon surface; a second silicon surface; a silicide barrier layer stack along the second silicon surface, comprising a plurality of silicide barrier layers, and wherein each silicide barrier layer in the plurality of silicide barrier layers has a conformality of at least 75%; as well as silicide along the first silicon surface.

17. The IC of claim 16, wherein the silicide blocking layer further comprises an etch stop layer.

18. The IC of claim 16, wherein the second silicon surface includes a first portion along a first plane and a second portion along a second plane different from the first plane, wherein a thickness of the silicide blocking layer stack along the first plane is in a range of 75% to 100% of a thickness of the silicide blocking layer stack along the second plane.

19. The IC of claim 16, wherein the silicon surface comprises a polysilicon resistor body coupled to a planar surface of a semiconductor substrate, the first plane is perpendicular to the planar surface of the semiconductor substrate, and the second plane is parallel to the planar surface of the semiconductor substrate.

20. The IC of claim 19, wherein each of the plurality of silicide blocking layers comprises silicon nitride.

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