Manufacturing method of chip structure
By using the cover layer as a mask in the wet etching process, the undercut phenomenon caused by the difference between the etching mask and the material to be etched is solved, and the shape and volume stability of the patterned conductive structure is achieved, and the reliability of the chip structure is improved.
Patent Information
- Application Number
- CN202410192841.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-28
- Filing Date
- 2024-02-21
- Publication Date
- 2025-05-30
AI Technical Summary
In the wet etching process, the difference in the etching mask and the material of the etching object leads to an undercut phenomenon, which affects the accuracy and reliability of the patterning.
By providing the first and second cover layers as masks on the patterned conductive structure, the first and second wet etching processes are performed, respectively, to ensure that the etching is only under the cover layer without affecting the patterned conductive structure.
The undercut phenomenon of patterned conductive structures is effectively avoided, the stability of its shape and volume is maintained, and the quality of patterning and the reliability of chip structure is improved.
Smart Images
Figure CN120072646A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a chip structure, and particularly to a manufacturing method of a chip structure. Background Art
[0002] When patterning using a wet etching process, undercutting often occurs due to different etching selectivity ratios between the etching mask and the object to be etched, making it impossible to accurately transfer the pattern of the etching mask to the object to be etched. If the materials of the etching mask and the object to be etched are the same, the etching mask will also be etched during the etching process, causing changes in its contour and volume reduction, which may make it difficult to connect during application and reduce the reliability. Summary of the Invention
[0003] The present invention is directed to a manufacturing method of a chip structure, which can improve the undercutting phenomenon and enhance the quality of patterning.
[0004] According to an embodiment of the present invention, the manufacturing method of the chip structure includes the following steps. Provide a substrate. Form a first bump bottom metal material layer on the substrate. Form a second bump bottom metal material layer on the first bump bottom metal material layer. Form a patterned conductive structure on the second bump bottom metal material layer. Form a first covering layer on the top surface and sidewalls of the patterned conductive structure. Perform a first wet etching process to remove the second bump bottom metal material layer not covered by the patterned conductive structure, thereby forming a second bump bottom metal layer. Remove the first covering layer. Form a second covering layer on the top surface and sidewalls of the patterned conductive structure and the sidewalls of the second bump bottom metal layer. Perform a second wet etching process to remove the first bump bottom metal material layer not covered by the patterned conductive structure to form a first bump bottom metal layer. Remove the second covering layer.
[0005] In an embodiment of the present invention, after performing the first wet etching process, there is a gap between the first covering layer and the first bump bottom metal material layer.
[0006] In an embodiment of the present invention, the height of the gap is substantially equal to the thickness of the second bump bottom metal layer.
[0007] In an embodiment of the present invention, the width of the gap is substantially equal to the thickness of the first covering layer.
[0008] In an embodiment of the present invention, after performing the second wet etching process, there is a gap between the second covering layer and the substrate.
[0009] In an embodiment of the present invention, the height of the gap is substantially equal to the thickness of the first bump bottom metal layer.
[0010] In an embodiment of the present invention, the width of the gap is substantially equal to the thickness of the second covering layer.
[0011] In an embodiment of the present invention, the sidewalls of the first bump bottom metal layer, the sidewalls of the second bump bottom metal layer, and the sidewalls of the patterned conductive structure are substantially flush.
[0012] In an embodiment of the present invention, the first covering layer and the second covering layer include photoresist.
[0013] In an embodiment of the present invention, the patterned conductive structure includes a first conductive structure and a second conductive structure, and the materials of the first conductive structure and the second conductive structure are different.
[0014] Based on the above, the manufacturing method of the chip structure of the present invention uses the first covering layer or the second covering layer disposed on the patterned conductive structure as a mask, so that the first wet etching process undercuts to below the first covering layer without undercutting to below the patterned conductive structure, and the second wet etching process undercuts to below the second covering layer without undercutting to below the patterned conductive structure, which can keep the patterned conductive structure maintain substantially the same shape and volume before and after the first wet etching process and the second wet etching process, and avoid the undercut phenomenon of the patterned conductive structure, improving the quality of patterning and further improving the reliability of the chip structure. Description of the Drawings
[0015] Figures 1A to 1I is a schematic diagram of a chip structure according to an embodiment of the present invention;
[0016] Figures 2A to 2G is a schematic diagram of a chip structure according to an embodiment of the present invention. Detailed Description of the Invention
[0017] Reference will now be made in detail to exemplary embodiments of the present invention. The examples of the exemplary embodiments are illustrated in the drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0018] The exemplary embodiments of the present invention will be described fully hereinafter with reference to the accompanying drawings, but the present invention can be implemented in many different forms and should not be construed as limited to the embodiments described herein. In the drawings, for the sake of clarity, the sizes and thicknesses of the various regions, portions, and layers may not be drawn to actual scale.
[0019] The directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are with reference to the directions of the drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.
[0020] In the following embodiments, the same or similar components will be denoted by the same or similar reference numerals, and their redundant descriptions will be omitted. In addition, features in different embodiments can be combined with each other without conflict, and simple equivalent changes and modifications made according to this specification or claims still fall within the scope covered by this patent.
[0021] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various components, parts, regions, layers, and / or portions, these components, parts, regions, and / or portions should not be limited by these terms. These terms are used to distinguish one component, part, region, layer, or portion from another component, part, region, layer, or portion. Thus, the first component, part, region, layer, or portion discussed below may be referred to as the second component, part, region, layer, or portion without departing from the teachings herein.
[0022] Figures 1A to 1I is a schematic diagram of a chip structure according to an embodiment of the present invention.
[0023] Please refer to Figure 1A , a substrate 100 is provided. For example, the substrate 100 can be a chip or a wafer, but the present invention is not limited thereto. In some embodiments, the substrate 100 includes a base 102, pads 104, and a protective layer 106. The pads 104 are disposed on the surface 102a of the base 102, and the protective layer 106 is disposed on the surface 102a of the base 102 and covers part of the pads 104. In other words, the protective layer 106 has an opening OP1 that exposes a part of the top surface of the pads 104. Figure 1A Only the base 102 is schematically shown in Figure 1A and its detailed structure is omitted. It should be understood that devices such as active components, passive components, integrated circuits, etc. can be provided in the base 102 and are externally connected through the pads 104. In addition,
[0024] Please continue to refer to Figure 1A, a first under bump metallization (UBM) material layer 110' is formed on a substrate 100, and a second under bump metallization material layer 120' is formed on the first under bump metallization material layer 110'. In some embodiments, the first under bump metallization material layer 110' is conformally formed on the surface 106a of the protective layer 106 and fills the opening OP1 to directly contact a part of the top surface of the pad 104. Thereafter, the second under bump metallization material layer 120' is conformally formed on the first under bump metallization material layer 110'. In some embodiments, the forming methods of the first under bump metallization material layer 110' and the second under bump metallization material layer 120' may respectively include a sputtering process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable deposition processes.
[0025] In some embodiments, the material of the first under bump metallization material layer 110' may include titanium, titanium tungsten (TiW), its alloy, or other suitable metal materials. In some embodiments, the second under bump metallization material layer 120' may include gold, copper, nickel, its alloy, or other suitable metal materials.
[0026] Please refer to Figure 1B , a patterned conductive structure 130 is formed on the second under bump metallization material layer 120'. For example, a patterned photoresist layer PR may be first formed on the second under bump metallization material layer 120', wherein the patterned photoresist layer PR has an opening OP2 to expose a part of the second under bump metallization material layer 120'. The position of the opening OP2 corresponds to the position of the pad 104. Then, a conductive material is deposited in the opening OP2 to form the patterned conductive structure 130. In some embodiments, the forming methods of the conductive material may respectively include an electroplating process, an electroless plating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable deposition processes. In some embodiments, the material of the patterned conductive structure 130 may be the same as the material of the second under bump metallization material layer 120', but the present invention is not limited thereto. Figure 1B The patterned conductive structure 130 is shown as a single-layer structure in [reference], but it is not intended to limit the present invention. In other embodiments, the patterned conductive structure 130 may have a composite structure, such as a material combination of copper / nickel / gold, but the present invention is not limited thereto.
[0027] Please refer to Figure 1C , the patterned photoresist layer PR is removed. In some embodiments, the patterned photoresist layer PR may be removed by a yellow light development process, etching, or other suitable photoresist removal process methods.
[0028] Please refer to Figure 1D, a first covering layer 140 is formed on the top surface 130t and the sidewalls 130s of the patterned conductive structure 130. For example, a first covering material layer (not shown) can be conformally formed on the second under-bump metal material layer 120' and the patterned conductive structure 130 first, and then a part of the first covering material layer is removed to form the first covering layer 140 on the top surface 130t and the sidewalls 130s of the patterned conductive structure 130.
[0029] In some embodiments, the first covering layer 140 or the first covering material layer can be a material that is easy to remove, such as photoresist, but the present invention is not limited thereto. In an embodiment where the first covering layer 140 or the first covering material layer is photoresist, the first covering material layer can be formed on the second under-bump metal material layer 120' and the patterned conductive structure 130 by spin coating, physical vapor deposition process, chemical vapor deposition process, or other suitable deposition processes, and then the first covering material layer can be exposed and developed through a photomask (not shown) to remove the first covering material layer that does not cover the patterned conductive structure 130, while retaining the first covering material layer on the top surface 130t and the sidewalls 130s of the patterned conductive structure 130.
[0030] In some embodiments, the thickness of the first covering layer 140 can be determined by calculating the range or width of the undercut of the second under-bump metal material layer 120' under the mask during a subsequent first wet etching process at a predetermined etching time. For example, the thickness t1 of the first covering layer 140 is substantially equal to the width of the undercut of the second under-bump metal material layer 120' under the mask. The above-mentioned predetermined etching time refers to, for example, the time required to completely remove the second under-bump metal material layer 120' that is not covered by the mask.
[0031] Please refer to Figure 1E , a first wet etching process is performed to remove the second under-bump metal material layer 120' that is not covered by the patterned conductive structure 130, and a second under-bump metal layer 120 is formed. For example, the first covering layer 140 and the patterned conductive structure 130 can be used as a mask, and an etching solution with a high etching selectivity to the second under-bump metal material layer 120' is selected to perform the first wet etching process. Since the top surface 130t and the sidewalls 130s of the patterned conductive structure 130 are covered by the first covering layer 140, during the first wet etching process, the patterned conductive structure 130 is protected by the first covering layer 140, so that its profile can be maintained, that is, the patterned conductive structure 130 still substantially maintains the same shape and volume as before the first wet etching process after the first wet etching process.
[0032] In some embodiments, after the first wet etching process, there is a gap g1 between the first cover layer 140 and the first under bump metallization layer 110'. That is to say, the second under bump metallization layer 120' originally located between the first cover layer 140 and the first under bump metallization layer 110' is removed during the first wet etching process. Since the undercut phenomenon generated during the first wet etching process occurs in the second under bump metallization layer 120' under the first cover layer 140 on the sidewall 130s of the patterned conductive structure 130 and does not undercut the second under bump metallization layer 120' under the patterned conductive structure 130, no undercut phenomenon will occur under the patterned conductive structure 130.
[0033] In some embodiments, the width w1 of the gap g1 is substantially equal to the thickness t1 of the first cover layer 140. In some embodiments, the height h1 of the gap g1 is substantially equal to the thickness t2 of the second under bump metal layer 120. In this way, the orthographic projection area of the second under bump metal layer 120 on the substrate 100 is substantially the same as the orthographic projection area of the patterned conductive structure 130 on the substrate 100. Herein, the width w1 of the gap g1 refers to the distance that the gap g1 depresses inward from the outer surface of the first cover layer 140; the height h1 of the gap g1 refers to the distance between the bottom surface of the first cover layer 140 and the top surface of the first under bump metallization layer 110'.
[0034] Please refer to Figure 1F , and remove the first cover layer 140. In some embodiments, the first cover layer 140 can be removed by a yellow light development process, etching, or other suitable processes for removing photoresist.
[0035] Please refer to Figure 1G , and form a second cover layer 150 on the top surface 130t and sidewall 130s of the patterned conductive structure 130 and on the sidewall 120s of the second under bump metal layer 120. For example, a second cover material layer (not shown) can be first conformally formed on the first under bump metallization layer 110' and the patterned conductive structure 130, and then a part of the second cover material layer is removed to form the second cover layer 150 on the top surface 130t and sidewall 130s of the patterned conductive structure 130 and on the sidewall 120s of the second under bump metal layer 120.
[0036] In some embodiments, the second cover layer 150 or the second cover material layer may be a material that is easily removable, such as photoresist, but the present invention is not limited thereto. In an embodiment where the second cover layer 150 or the second cover material layer is photoresist, the second cover material layer may be formed on the first bump bottom metal material layer 110' and the patterned conductive structure 130 by spin coating, physical vapor deposition process, chemical vapor deposition process, or other suitable deposition processes. Then, the second cover material layer may be exposed and developed through a photomask (not shown) to remove the second cover material layer that does not cover the patterned conductive structure 130, while retaining the second cover material layer on the top surface 130t and sidewalls 130s of the patterned conductive structure 130 and the sidewalls 120s of the second bump bottom metal layer 120.
[0037] In some embodiments, the thickness of the second cover layer 150 may be determined by calculating the range or width of the undercut of the first bump bottom metal material layer 110' under the mask during a subsequent second wet etching process for a predetermined etching time. For example, the thickness t3 of the second cover layer 150 is substantially equal to the width of the undercut of the first bump bottom metal material layer 110' under the mask. The above-mentioned predetermined etching time refers to, for example, the time required to completely remove the first bump bottom metal material layer 110' that is not covered by the mask.
[0038] Please refer to Figure 1H , and perform a second wet etching process to remove the first bump bottom metal material layer 110' that is not covered by the patterned conductive structure 130 to form the first bump bottom metal layer 110. For example, the second cover layer 150 and the patterned conductive structure 130 may be used as a mask, and an etching solution with a high etching selectivity for the first bump bottom metal material layer 110' may be selected to perform the second wet etching process. Since the top surface 130t and sidewalls 130s of the patterned conductive structure 130 and the sidewalls 120s of the second bump bottom metal layer 120 are covered by the second cover layer 150, during the second wet etching process, the patterned conductive structure 130 and the second bump bottom metal layer 120 are protected by the second cover layer 150, so that their profiles can be maintained. That is to say, the patterned conductive structure 130 and the second bump bottom metal layer 120 still substantially maintain the same shape and volume after the second wet etching process as before the second wet etching process.
[0039] In some embodiments, after performing the second wet etching process, there is a gap g2 between the second covering layer 150 and the protective layer 106. That is to say, the first under bump metal material layer 110' originally located between the second covering layer 150 and the protective layer 106 is removed during the second wet etching process. Since the undercut phenomenon generated during the second wet etching process occurs in the first under bump metal material layer 110' under the second covering layer 150 on the sidewall 130s of the patterned conductive structure 130 and will not undercut the first under bump metal material layer 110' under the patterned conductive structure 130, no undercut phenomenon will occur under the patterned conductive structure 130.
[0040] In some embodiments, the width w2 of the gap g2 is substantially equal to the thickness t3 of the second covering layer 150. In some embodiments, the height h2 of the gap g2 is substantially equal to the thickness t4 of the first under bump metal layer 110. In this way, the orthographic projection area of the first under bump metal layer 110 on the substrate 100 is substantially the same as the orthographic projection area of the patterned conductive structure 130 on the substrate 100. Herein, the width w2 of the gap g2 refers to the distance that the gap g2 is recessed inward from the outer surface of the second covering layer 150; the height h2 of the gap g2 refers to the distance between the bottom surface of the second covering layer 150 and the top surface of the protective layer 106.
[0041] Please refer to Figure 1I , and remove the second covering layer 150. In some embodiments, the second covering layer 150 can be removed by a yellow light development process, etching, or other suitable processes for removing photoresist.
[0042] Based on the above, the manufacturing of the chip structure 10 can be generally completed.
[0043] The chip structure 10 includes a substrate 100, a first under bump metal layer 110, a second under bump metal layer 120, and a patterned conductive structure 130. The substrate 100 includes a base 102, pads 104, and a protective layer 106. The pads 104 are disposed on the base 102, and the protective layer 106 is disposed on the base 102 and part of the pads 104. The first under bump metal layer 110 is disposed on the pads 104, and the second under bump metal layer 120 is disposed on the first under bump metal layer 110. The patterned conductive structure 130 is disposed on the second under bump metal layer 120.
[0044] In some embodiments, the sidewalls 110s of the first under bump metal layer 110, the sidewalls 120s of the second under bump metal layer 120, and the sidewalls 130s of the patterned conductive structure 130 are substantially flush.
[0045] In this embodiment, the width of the patterned conductive structure 130 is less than the width of the pad 104, but the present invention is not limited thereto. In other embodiments, the width of the patterned conductive structure 130 is greater than the width of the pad 104.
[0046] In Figure 1I it, the patterned conductive structure 130 may be a bump structure for external connection. The first under bump metal layer 110 is disposed between the second under bump metal layer 120 and the pad 104 and can serve as a diffusion barrier layer to reduce metal diffusion. The second under bump metal layer 120 is disposed between the first under bump metal layer 110 and the patterned conductive structure 130 and can increase the adhesion between the bump structure (i.e., the patterned conductive structure 130) and the pad 104. In other feasible embodiments, the patterned conductive structure 130 may also be a bump structure directly formed on the protective layer 106 without being electrically connected to the pad 104. That is to say, the setting of the first under bump metal layer 110 and the second under bump metal layer 120 can also increase the adhesion between the bump structure (i.e., the patterned conductive structure 130) and the protective layer 106. For example, the patterned conductive structure 130 may be a bump having a single material, such as a gold bump. In the embodiment where the patterned conductive structure 130 is a gold bump, the material of the first under bump metal layer 110 may include titanium tungsten, and the material of the second under bump metal layer 120 may include gold. In other embodiments, the patterned conductive structure 130 may be a bump having a composite material, such as a copper / nickel / gold bump. In the embodiment where the patterned conductive structure 130 is a copper / nickel / gold bump, the material of the first under bump metal layer 110 may include titanium, and the material of the second under bump metal layer 120 may include copper.
[0047] Since the manufacturing method of the chip structure 10 in this embodiment does not undercut under the patterned conductive structure 130 by respectively undercutting under the first cover layer 140 and the second cover layer 150 in the first wet etching process and the second wet etching process, the patterned conductive structure 130 can maintain substantially the same shape and volume before and after the first wet etching process and the second wet etching process, and avoid the undercut phenomenon under the patterned conductive structure 130, improving the patterning quality and thus enhancing the reliability of the chip structure 10.
[0048] Figures 2A to 2G is a schematic diagram of a chip structure according to an embodiment of the present invention. It must be noted here that Figures 2A to 2G the embodiment of Figures 1A to 1I adopts the component numbers and some contents of the embodiment of
[0049] Please refer toFigure 2A , a substrate 100 is provided, a first under-bump metal material layer 110' is formed on the substrate 100, and a second under-bump metal material layer 120' is formed on the first under-bump metal material layer 110'. The foregoing process is similar to the process of Figure 1A , so the relevant description can be referred to Figure 1A . Details are not described herein.
[0050] Please continue to refer to Figure 2A , a patterned conductive structure 130 is formed on the second under-bump metal material layer 120'. The patterned conductive structure 130 may include a first conductive structure 132 and a second conductive structure 134. The materials of the first conductive structure 132 and the second conductive structure 134 are different. For example, the material of the first conductive structure 132 may include copper, and the material of the second conductive structure 134 may include gold, but the present invention is not limited thereto. Figure 2A Although the patterned conductive structure 130 shown in Figures 1B to 1C includes a two-layer structure, it is not intended to limit the present invention. The patterned conductive structure 130 may have one or more layers of structure according to actual needs. In other embodiments, a third conductive structure (not shown) may also be included between the first conductive structure 132 and the second conductive structure 134, and the material of the third conductive structure may include nickel, for example. The formation method of the patterned conductive structure 130 can be referred to the above
[0051] Please refer to Figure 2B , a first covering layer 140 is formed on the top surface 130t and the sidewalls 130s of the patterned conductive structure 130. For example, a first covering material layer (not shown) may be conformally formed on the second under-bump metal material layer 120' and the patterned conductive structure 130 first, and then a part of the first covering material layer is removed to form the first covering layer 140 on the top surface 130t and the sidewalls 130s of the patterned conductive structure 130. In Figure 2B , the top surface 130t of the patterned conductive structure 130 is the top surface 134t of the second conductive structure 134, and the sidewalls 130s of the patterned conductive structure 130 are composed of the sidewalls 132s of the first conductive structure 132 and the sidewalls 134s of the second conductive structure 134.
[0052] In some embodiments, the first cover layer 140 or the first cover material layer may be a material that is easily removable, such as photoresist, but the present invention is not limited thereto. In an embodiment where the first cover layer 140 or the first cover material layer is photoresist, the first cover material layer may be formed on the second under-bump metal material layer 120' and the patterned conductive structure 130 by spin coating, physical vapor deposition process, chemical vapor deposition process, or other suitable deposition processes. Then, the first cover material layer may be exposed and developed through a photomask (not shown) to remove the first cover material layer that does not cover the patterned conductive structure 130, while retaining the first cover material layer on the top surface 134t and sidewalls 134s of the second conductive structure 134 and the sidewalls 132s of the first conductive structure 132.
[0053] In some embodiments, the thickness of the first cover layer 140 may be determined by calculating the range or width of the undercut of the second under-bump metal material layer 120' under the mask during a subsequent first wet etching process for a predetermined etching time. For example, the thickness t1 of the first cover layer 140 is substantially equal to the width of the undercut of the second under-bump metal material layer 120' under the mask. The above-mentioned predetermined etching time refers to, for example, the time required to completely remove the second under-bump metal material layer 120' that is not covered by the mask.
[0054] Please refer to Figures 2C to 2G , and perform a first wet etching process to remove the second under-bump metal material layer 120' that is not covered by the patterned conductive structure 130, thereby forming the second under-bump metal layer 120. Then, remove the first cover layer 140. Form a second cover layer 150 on the top surface 130t and sidewalls 130s of the patterned conductive structure 130 and the sidewalls 120s of the second under-bump metal layer 120. Perform a second wet etching process to remove the first under-bump metal material layer 110' that is not covered by the patterned conductive structure 130 to form the first under-bump metal layer 110. Then, remove the second cover layer 150. Figures 2C to 2G The process of Figures 1E to 1I is similar to the above Figures 1E to 1I process, so the relevant description can refer to
[0055] Based on the above, the fabrication of the chip structure 20 can be generally completed.
[0056] The chip structure 20 includes a substrate 100, a first under-bump metal layer 110, a second under-bump metal layer 120, and a patterned conductive structure 130. The substrate 100 includes a base 102, pads 104, and a protective layer 106. The pads 104 are disposed on the base 102, and the protective layer 106 is disposed on the base 102 and part of the pads 104. The first under-bump metal layer 110 is disposed on the pads 104, and the second under-bump metal layer 120 is disposed on the first under-bump metal layer 110. The patterned conductive structure 130 is disposed on the second under-bump metal layer 120. The patterned conductive structure 130 includes a first conductive structure 132 and a second conductive structure 134. The second conductive structure 134 is disposed on the first conductive structure 132, and the material of the first conductive structure 132 is different from the material of the second conductive structure 134.
[0057] In some embodiments, the sidewalls 110s of the first under-bump metal layer 110, the sidewalls 120s of the second under-bump metal layer 120, the sidewalls 132s of the first conductive structure 132, and the sidewalls 134s of the second conductive structure 134 are substantially flush.
[0058] In this embodiment, the width of the patterned conductive structure 130 is greater than the width of the pads 104, but the present invention is not limited thereto.
[0059] In Figure 2G , the patterned conductive structure 130 can be used as a redistribution layer (RDL) to redistribute the circuit layers. The first under-bump metal layer 110 is disposed between the second under-bump metal layer 120 and the pads 104 and can serve as a diffusion barrier layer to reduce metal diffusion. The second under-bump metal layer 120 is disposed between the first under-bump metal layer 110 and the patterned conductive structure 130 and can increase the adhesion between the redistribution layer (RDL) (i.e., the patterned conductive structure 130), the pads 104, and the protective layer 106. For example, the first conductive structure 132 of the patterned conductive structure 130 can include copper, the second conductive structure 134 of the patterned conductive structure 130 can include gold, the material of the first under-bump metal layer 110 can include titanium, and the material of the second under-bump metal layer 120 can include copper.
[0060] Figure 2G shows schematically one layer of the redistribution layer, but is not intended to limit the present invention. The number of redistribution layers can be adjusted to multiple layers according to actual requirements.
[0061] Since the manufacturing method of the chip structure 20 of this embodiment does not undercut under the patterned conductive structure 130 by undercutting under the first covering layer 140 and under the second covering layer 150 respectively through the first wet etching process and the second wet etching process, the patterned conductive structure 130 can maintain substantially the same shape and volume before and after the first wet etching process and the second wet etching process, and the undercut phenomenon under the patterned conductive structure 130 can be avoided, so that the quality of patterning is improved, and further the reliability of the chip structure 20 is improved.
[0062] In summary, the manufacturing method of the chip structure of the present invention uses the first covering layer or the second covering layer provided on the patterned conductive structure as a mask, so that the first wet etching process undercuts under the first covering layer and does not undercut under the patterned conductive structure, and the second wet etching process undercuts under the second covering layer and does not undercut under the patterned conductive structure, so that the patterned conductive structure can maintain substantially the same shape and volume before and after the first wet etching process and the second wet etching process, and the undercut phenomenon under the patterned conductive structure can be avoided, so that the quality of patterning is improved, and further the reliability of the chip structure is improved.
[0063] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for manufacturing a chip structure, characterized in that: include: providing a substrate; forming a first under-bump metal material layer on the substrate; forming a second under bump metal material layer on the first under bump metal material layer; forming a patterned conductive structure on the second under-bump metal material layer; forming a first covering layer on the top surface and sidewalls of the patterned conductive structure; Performing a first wet etching process to remove the second under bump metal material layer not covered by the patterned conductive structure to form a second under bump metal layer; removing the first covering layer; forming a second covering layer on the top surface and the sidewalls of the patterned conductive structure and on the sidewalls of the second under bump metal layer; Performing a second wet etching process to remove the first under bump metal material layer not covered by the patterned conductive structure to form a first under bump metal layer; as well as The second covering layer is removed.
2. The method for manufacturing a chip structure according to claim 1, characterized in that: After the first wet etching process is performed, a gap is formed between the first covering layer and the first under bump metal material layer.
3. The method for manufacturing a chip structure according to claim 2, characterized in that: The height of the gap is equal to the thickness of the second under bump metallurgy layer.
4. The method for manufacturing a chip structure according to claim 2, characterized in that: The width of the gap is equal to the thickness of the first covering layer.
5. The method for manufacturing a chip structure according to claim 1, characterized in that: After the second wet etching process is performed, a gap is formed between the second covering layer and the substrate.
6. The method for manufacturing a chip structure according to claim 5, characterized in that: The height of the gap is equal to the thickness of the first under bump metallurgy layer.
7. The method for manufacturing a chip structure according to claim 5, characterized in that: The width of the gap is equal to the thickness of the second covering layer.
8. The method for manufacturing a chip structure according to claim 1, characterized in that: The sidewall of the first UBM layer and the sidewall of the second UBM layer are aligned with the sidewall of the patterned conductive structure.
9. The method for manufacturing a chip structure according to claim 1, characterized in that: The first covering layer and the second covering layer include photoresist.
10. The method for manufacturing a chip structure according to claim 1, characterized in that: The patterned conductive structure includes a first conductive structure and a second conductive structure, and a material of the first conductive structure is different from a material of the second conductive structure.