Chip three-dimensional packaging method

Abstract

The invention belongs to the technical field of semiconductor packaging, and particularly relates to a three-dimensional packaging method for a chip. Comprising the following steps: S1, preparing a 12-inch silicon wafer; s2, preparing a first N-layer metal interconnection line; s3, wafer-level temporary bonding is carried out on the first N layers of metal interconnection lines; s4, thinning the silicon back of the silicon wafer through wafer-level thinning equipment; s5, carrying out the process development of the aluminum bonding finger with the thickness of 5 microns; s6, forming a wafer-level multi-layer re-wiring silicon substrate; step S7, scribing the wafer-level multi-layer rewiring silicon substrate to form a core particle integrated substrate with a customized size; step S8, preparing and forming a core particle integrated micro module; step S9, reconstructing and preparing a 12-inch wafer; step S10, thinning the resin surface by using wafer-level resin thinning equipment; according to the invention, the integration density of the core particles is improved, the metal interconnection between the functional core particles is greatly shortened, and the heating, the power consumption and the delay are reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and particularly relates to a three-dimensional chip packaging method. Background Art

[0002] Three-dimensional interconnection is based on planar circuits and uses the third dimension to achieve the integration of multiple layers of devices within a single chip. That is, a large planar circuit is divided into several logically related functional modules distributed on multiple adjacent chip layers, and then the multi-layer chips are integrated through three-dimensional vertical interconnection penetrating the substrate. Three-dimensional interconnection can achieve the vertical integration of multi-chips with different functions and different processes, greatly reducing the length of global interconnection, thereby significantly reducing interconnection delay, increasing the speed of integrated circuits, and reducing the power consumption of chips.

[0003] Currently, the three-dimensional integration of wafer-level packaging is mainly the vertical interconnection of metal copper pillars on a silicon wafer and chiplets. The metal copper pillar vias on the silicon wafer are prepared through a series of processes such as deep silicon etching of vias on the silicon wafer, growth of an insulating layer on the via wall, growth of a seed layer on the via wall, and electroplating filling of metal in the vias. The process for preparing metal vias on a silicon wafer is relatively mature. However, the process of welding the vias on the silicon wafer to the multi-chiplet placement is difficult, and the material and processing costs are high. Not only high-end equipment is required for processing, such as high-precision wafer-level placement machines, wafer-level underfill equipment, etc. On the other hand, after the through-silicon wafer is prepared, it is 200um, with a large wafer warpage, resulting in difficult placement, and there is a problem of easy cracking of the silicon wafer during the multi-chiplet integration process. This significantly reduces the packaging yield of three-dimensional integration and increases the raw material and chiplet costs. Summary of the Invention

[0004] The purpose of the present invention is to overcome the above deficiencies of the prior art and provide a three-dimensional chip packaging method to solve the problems such as the difficult process of welding the vias on the silicon wafer to the multi-chiplet ports and the high risk of cracking of the 200um silicon wafer in the prior art.

[0005] To solve the above technical problems, the present invention provides a three-dimensional chip packaging method, including the following steps:

[0006] Step S1: Etch a plurality of blind holes on a 12-inch silicon substrate through a deep silicon etching device to form a 12-inch silicon wafer, and perform metallization filling in the blind holes through a metal electroplating process;

[0007] Step S2: Prepare the first N-layer metal interconnections on the 12-inch silicon wafer after metallization filling;

[0008] Step S3: Coat a temporary bonding adhesive on the first N-layer metal interconnections through a full-automatic spin coating device, and perform wafer-level temporary bonding with a silicon carrier bonding carrier plate on the temporary bonding adhesive;

[0009] Step S4: After thinning the silicon back of the 12-inch silicon wafer by a wafer-level thinning device to a thickness of 20 μm to 30 μm from the blind hole, dry etching is performed by a deep silicon etching device until the metal inside the blind hole is exposed;

[0010] Step S5: Develop an aluminum bonding finger process with a thickness of 5 μm at the location where the metal inside the blind hole is exposed;

[0011] Step S6: Peel off the temporary bonding adhesive and the silicon carrier bonding carrier plate to form a wafer-level multi-layer re-wired silicon substrate;

[0012] Step S7: Dice the wafer-level multi-layer re-wired silicon substrate by a wafer-level dicing device to form a core chip integrated substrate with a customized size;

[0013] Step S8: Solder the core chip with a tin-containing lead-out terminal and the resin through-hole chip to the core chip integrated substrate to prepare a core chip integrated micro-module;

[0014] Step S9: Lay multiple core chip integrated micro-modules flat in a 12-inch wafer encapsulation mold, and inject resin into the encapsulation mold by a wafer-level encapsulation device to reconstruct and prepare a 12-inch wafer;

[0015] Step S10: Thin the resin surface by a wafer-level resin thinning device until the core chip with the tin-containing lead-out terminal and the resin through-hole chip are exposed;

[0016] Step S11: Prepare the second N-layer metal interconnections on the 12-inch wafer, and finally form a 12-inch wafer-level resin-embedded core chip double-sided multi-layer integrated micro-module;

[0017] Step S12: Flip multiple 12-inch wafer-level resin-embedded core chip double-sided multi-layer integrated micro-modules onto the pads on a 12-inch core chip integrated resin wafer through a high-precision alignment device, and perform soldering through a wafer-level reflow device to finally fabricate a packaging structure for 3D integration of core chips.

[0018] Preferably, in step S1, the aspect ratio of the blind hole etching is 200 μm:20 μm.

[0019] Preferably, in step S1, the material for the metallization filling is copper.

[0020] Preferably, in step S2, on the 12-inch silicon wafer after the metallization filling, first coat a polyimide passivation layer with a thickness of 3 μm to 7 μm by a photoresist spin-coating device, and then electroplate a metal re-wiring with a thickness of 2 μm to 5 μm by a metal electroplating device to prepare the first N-layer metal interconnections.

[0021] Preferably, in step S6, the temporary bonding adhesive on the first N-layer metal interconnection line and the silicon carrier bonding carrier are peeled off by a fully automatic laser debonding device to form the wafer-level multi-layer re-wired silicon substrate.

[0022] Preferably, after soldering in step S8, it further includes: filling the gap between the die chip with a tin lead-out end and the resin via chip and the die integrated substrate.

[0023] Preferably, in step S11, on the 12-inch wafer, a polyimide passivation layer with a thickness of 3 μm to 7 μm is first coated by a photoresist spin-coating device, and then a metal re-wiring with a thickness of 2 μm to 5 μm is electroplated by a metal electroplating device to prepare the second N-layer metal interconnection line.

[0024] Preferably, in steps S2 and S11, the materials of the first N-layer metal interconnection line and the second N-layer metal interconnection line are metal or a mixed material of metal and metal nitride.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] 1. The three-dimensional packaging method of the present invention reduces wafer warpage through the resin reconstruction process of embedding multiple die integrated micromodules, thereby increasing the number of integrated metal interconnection layers and expanding the compatibility of such processes for chip processing; in addition, compared with the process of forming a micromodule by welding a through-silicon wafer and a die, this process can overcome the problems of fragility and chipping of the micromodule through resin embedding, greatly improving the support strength and reliability, and thus improving the yield of the packaging structure.

[0027] 2. The present invention can integrate dies with different substrates and different functions on a wafer-level heterogeneous three-dimensional structure. Without changing the two-dimensional area of the integrated body and only increasing the three-dimensional height, it greatly improves the die integration density, significantly shortens the metal interconnection between each functional die, and reduces heat generation, power consumption, and delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a flowchart of a three-dimensional packaging method for a chip according to the present invention.

[0029] Figure 2 is a schematic structural diagram of the present invention in which a plurality of blind holes are etched on a 12-inch silicon substrate by a deep silicon etching device to form a 12-inch silicon wafer, and metalized filling is performed in the blind holes by a metal electroplating process.

[0030] Figure 3 is a schematic structural diagram of the present invention in which a first N-layer metal interconnection line is prepared on the silicon wafer after metalized filling.

[0031] Figure 4 It is a structural schematic diagram of applying temporary bonding glue on the first N-layer metal interconnection line by a full-automatic spin coating device, and performing wafer-level temporary bonding with a silicon-based bonding carrier on the temporary bonding glue in the present invention.

[0032] Figure 5 It is a structural schematic diagram of thinning the silicon back of a silicon wafer by using a wafer-level thinning device in the present invention until the metal in the blind hole is exposed.

[0033] Figure 6 It is a structural schematic diagram of the process development of 5 μm thick aluminum bonding fingers at the metal exposed in the blind hole in the present invention.

[0034] Figure 7 It is a structural schematic diagram of peeling off the temporary bonding adhesive and the silicon-carrying bonding carrier to form a wafer-level multi-layer rewiring silicon substrate in the present invention.

[0035] Figure 8 It is a structural schematic diagram of the present invention in which a wafer-level multi-layer rewiring silicon substrate is diced by a wafer-level dicing device to form a core particle integrated substrate of a customized size.

[0036] Figure 9 The present invention is a schematic structural diagram of welding a core particle chip with a tin-containing lead-out terminal and a resin through-hole chip to a core particle integrated substrate to prepare a core particle integrated micromodule.

[0037] Figure 10 The present invention is a schematic diagram of the structure of laying multiple core integrated micro-modules flat in a 12-inch wafer plastic packaging mold, injecting resin into the plastic packaging mold using wafer-level plastic packaging equipment, and reconstructing and preparing a 12-inch wafer.

[0038] Figure 11 It is a structural schematic diagram of the present invention using wafer-level resin thinning equipment to thin the resin surface until the core particle chip containing tin lead-out ends and the resin through-hole chip are exposed.

[0039] Figure 12 It is a schematic diagram of the structure of preparing a second N-layer metal interconnection line on a wafer in the present invention, and finally forming a 12-inch wafer-level resin-embedded core particle double-sided multi-layer integrated micromodule.

[0040] Figure 13 It is a structural schematic diagram of the present invention in which multiple wafer-level resin embedded core double-sided multi-layer integrated micro-modules are flipped onto pads on a 12-inch core integrated resin wafer level through high-precision alignment equipment.

[0041] Figure 14 The present invention is a schematic diagram of a packaging structure for three-dimensional integration of core particles, which is finally manufactured by welding through wafer-level reflow equipment.

[0042] In the figure: 1 - 12-inch silicon substrate, 2 - blind hole, 3 - first N-layer metal interconnect line, 4 - temporary bonding adhesive, 5 - silicon carrier bonding carrier plate, 6 - wafer-level multi-layer rewiring silicon substrate, 7 - chiplet integration substrate, 8 - chiplet chip with tin-containing lead-out ends, 9 - resin via hole chip, 10 - chiplet integration micro-module, 11 - second N-layer metal interconnect line, 12 - 12-inch wafer-level resin-embedded chiplet double-sided multi-layer integration micro-module, 13 - pad. Detailed implementation manners

[0043] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0044] As Figure 1 shown, an embodiment of the present invention provides a three-dimensional chip packaging method, including:

[0045] Step S1: Etch a plurality of blind holes 2 on a 12-inch silicon substrate 1 through a deep silicon etching device to make a 12-inch silicon wafer, and perform metallization filling in the blind holes 2 through a metal electroplating process, as Figure 2 shown.

[0046] In the embodiment of the present invention, the aspect ratio of the blind holes 2 etched on the silicon substrate 1 is 200μm:20μm, having good electrical performance, with a typical impedance matching value of 50 ohms, insertion loss of -17dB to 20dB @ 8GHz, and supporting a rate of 24GT / s; the metal material for metallization filling is copper.

[0047] Step S2: Prepare the first N-layer metal interconnect line 3 on the metallized silicon wafer, as Figure 3 shown.

[0048] In the embodiment of the present invention, a polyimide passivation layer with a thickness of 3μm to 7μm is coated on the metallized silicon wafer through a photoresist spin-coating device. The passivation layer within this thickness range can effectively reduce the processing flatness and warpage of the passivation layer. By electroplating a metal rewiring with a thickness of 2μm to 5μm through a metal electroplating device, it can have a good coefficient of thermal expansion match with the above passivation layer, greatly reducing the delamination risk between the metal rewiring and the passivation layer. Prepare the first N-layer metal interconnect line 3, and the material of the first N-layer metal interconnect line 3 is a metal or a mixed material of a metal and a metal nitride.

[0049] Step S3: Coat the temporary bonding adhesive 4 on the first N-layer metal interconnect line 3 through a fully automatic spin-coating device, and perform wafer-level temporary bonding with the silicon carrier bonding carrier plate 5 on the temporary bonding adhesive 4, as Figure 4 shown.

[0050] Step S4: Thinning the back of the silicon wafer by a wafer-level thinning equipment. After thinning to a thickness of 20 μm to 30 μm from the blind via, the integrity of the blind via before exposing the metal copper pillar can be protected, and the risk of silicon wafer thinning fragments can also be reduced. Then, dry etching is performed by a deep silicon etching equipment until the metal in the blind via 2 is exposed, as Figure 5 shown.

[0051] Step S5: Develop an aluminum bonding finger process with a thickness of 5 μm at the position where the metal in the blind via 2 is exposed, as Figure 6 shown.

[0052] Step S6: Peel off the temporary bonding adhesive 4 and the silicon carrier bonding carrier plate 5 to form a wafer-level multi-layer re-wiring silicon substrate 6, as Figure 7 shown.

[0053] In the embodiment of the present invention, the temporary bonding adhesive 4 and the silicon carrier bonding carrier plate 5 on the first N-layer metal interconnection line 3 are peeled off by a full-automatic laser debonding equipment to form a wafer-level multi-layer re-wiring silicon substrate 6.

[0054] Step S7: Dicing the wafer-level multi-layer re-wiring silicon substrate 6 by a wafer-level dicing equipment to form a diced chip integrated substrate 7 with a customized size, as Figure 8 shown.

[0055] Step S8: Weld the diced chip 8 with a tin-containing lead-out end and the resin through-hole chip 9 to the diced chip integrated substrate 7, and fill the gap between the diced chip 8 with a tin-containing lead-out end and the resin through-hole chip 9 and the diced chip integrated substrate 7 to prepare a diced chip integrated micro-module 10, as Figure 9 shown.

[0056] Step S9: Lay multiple diced chip integrated micro-modules 10 flat in a 12-inch wafer encapsulation mold, and inject resin into the encapsulation mold by a wafer-level encapsulation equipment to reconstruct and prepare a 12-inch wafer, as Figure 10 shown.

[0057] Step S10: Thin the resin surface by a wafer-level resin thinning equipment until the diced chip 8 with a tin-containing lead-out end and the resin through-hole chip 9 are exposed, as Figure 11 shown.

[0058] Step S11: Fabricate a second N-layer metal interconnection line 11 on the wafer to finally form a 12-inch wafer-level resin-embedded diced chip double-sided multi-layer integrated micro-module 12, as Figure 12 shown.

[0059] In an embodiment of the present invention, a polyimide passivation layer with a thickness of 3 μm to 7 μm is coated on a wafer through a photoresist spin-coating device, and a metal redistribution layer with a thickness of 2 μm to 5 μm is electroplated through a metal electroplating device to prepare a second N-layer metal interconnect line 11. The material of the second N-layer metal interconnect line 11 is a metal or a mixed material of a metal and a metal nitride.

[0060] Step S12: A plurality of wafer-level resin-embedded die double-sided multi-layer integrated micromodules 12 are flip-chip mounted onto pads 13 on a 12-inch die integrated resin wafer through a high-precision alignment device, as Figure 13 shown, and are soldered through a wafer-level reflow device to finally form a package structure for die three-dimensional integration, as Figure 14 shown.

[0061] In summary, the present invention can integrate dies with different substrates and different functions on a wafer-level heterogeneous three-dimensional structure. Without changing the two-dimensional area of the integrated body and only increasing the three-dimensional height, the die integration density is greatly improved, the metal interconnection between each functional die is significantly shortened, and the heat generation, power consumption, and delay are reduced. After integration, the micromodule and the resin of the present invention are reconstructed into a 12-inch wafer, which can effectively evenly distribute stress, reduce the wafer warpage caused by stress, and is beneficial to better matching the coefficient of thermal expansion between the resin wafer, the metal interconnection layer, and the polyimide passivation layer, thereby improving the processing yield, preparation difficulty, and the number of metal interconnect lines. The process of embedding the micromodule in the resin proposed by the present invention provides a resin support for the micromodule, effectively avoiding the problem of the fragility of the 200-μm die integrated substrate, and improving the environmental adaptability, structural integrity, and reliability of the product. It does not require complex processes such as wafer-level die bonding and wafer-level underfill. Only a relatively common single-chip die bonding and underfill process is needed to assemble the chip and the die integrated substrate, which can reduce the production equipment investment cost and shorten the process flow, making it more suitable for industrialization, especially for the three-dimensional packaging of multi-I / O chips.

[0062] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A chip three-dimensional packaging method, characterized in that: The steps include: Step S1: etching a plurality of blind holes (2) on a 12-inch silicon substrate (1) by using a deep silicon etching device, thereby manufacturing a 12-inch silicon wafer, and performing metallization filling in the blind holes (2) by using a metal electroplating process; Step S2: preparing a first N-layer metal interconnection line (3) on the 12-inch silicon wafer after metallization filling; Step S3: coating the first N-layer metal interconnection line (3) with a temporary bonding adhesive (4) by means of a fully automatic spin coating device, and performing wafer-level temporary bonding on the temporary bonding adhesive (4) with a silicon-based bonding carrier (5); Step S4: thinning the silicon back of the 12-inch silicon wafer to a distance of 20 μm to 30 μm from the blind hole (2) by using a wafer-level thinning device, and then performing dry etching by using a deep silicon etching device until the metal in the blind hole (2) is exposed; Step S5: developing a 5 μm thick aluminum bonding finger process at the metal exposed in the blind hole (2); Step S6: peeling off the temporary bonding adhesive (4) and the silicon-based bonding carrier (5) to form a wafer-level multi-layer rewiring silicon substrate (6); Step S7: Slicing the wafer-level multi-layer rewiring silicon substrate (6) by wafer-level dicing equipment to form a chip integrated substrate (7) of customized size; Step S8: welding the core particle chip (8) with the tin-containing lead-out terminal and the resin through-hole chip (9) to the core particle integrated substrate (7) to prepare a core particle integrated micromodule (10); Step S9: laying a plurality of the core integrated micro-modules (10) flat in a 12-inch wafer plastic packaging mold, injecting into the plastic packaging mold using a wafer-level plastic packaging device, and reconstructing to prepare a 12-inch wafer; Step S10: thinning the resin surface using a wafer-level resin thinning device until the core particle chip (8) with the tin-containing lead-out terminal and the resin through-hole chip (9) are exposed; Step S11: preparing a second N-layer metal interconnection line (11) on the 12-inch wafer, and finally forming a 12-inch wafer-level resin-embedded core particle double-sided multi-layer integrated micromodule (12); Step S12: A plurality of the 12-inch wafer-level resin embedded core double-sided multi-layer integrated micromodules (12) are flipped onto pads (13) on a 12-inch core integrated resin wafer level through high-precision alignment equipment, and are soldered through wafer-level reflow equipment to finally form a packaging structure for core three-dimensional integration.

2. A chip three-dimensional packaging method according to claim 1, characterized in that: In the step S1, the blind hole (2) is etched with a depth-to-width ratio of 200 μm:20 μm.

3. A chip three-dimensional packaging method as claimed in claim 1, characterized in that: In the step S1, the material of the metallization filling is copper.

4. A chip three-dimensional packaging method as claimed in claim 1, characterized in that: In the step S2, a polyimide passivation layer with a thickness of 3 μm to 7 μm is firstly coated on the 12-inch silicon wafer after the metallization filling by a photoresist spin coating device, and then a metal rewiring with a thickness of 2 μm to 5 μm is electroplated by a metal electroplating device to prepare the first N-layer metal interconnection line (3).

5. A chip three-dimensional packaging method as claimed in claim 1, characterized in that: In the step S6, the temporary bonding glue (4) and the silicon-based bonding carrier (5) on the first N-layer metal interconnection line (3) are peeled off by a fully automatic laser debonding device to form the wafer-level multi-layer rewiring silicon substrate (6).

6. A chip three-dimensional packaging method as claimed in claim 1, characterized in that: After welding, the step S8 further comprises: filling the gap between the core particle chip (8) with the tin-containing lead-out terminal and the resin through-hole chip (9) and the core particle integrated substrate (7).

7. A chip three-dimensional packaging method as claimed in claim 1, characterized in that: In the step S11, a polyimide passivation layer with a thickness of 3 μm to 7 μm is firstly coated on the 12-inch wafer by a photoresist spin coating device, and then a metal rewiring with a thickness of 2 μm to 5 μm is electroplated by a metal electroplating device to prepare the second N-layer metal interconnection line (11).

8. A chip three-dimensional packaging method as claimed in claim 1, characterized in that: In the step S2 and the step S11, the material of the first N-layer metal interconnection line (3) and the second N-layer metal interconnection line (11) is metal or a mixed material of metal and metal nitride.

Images