Method for manufacturing back stage of semiconductor
During the rear-stage manufacturing process of semiconductor chips, chemical vapor deposition technology is used to adjust the compressive stress of the dielectric layer and the nitride layer, and the packaging crack problem caused by insufficient film strength of the chip protection layer is solved, and the yield of the chip is improved.
Patent Information
- Application Number
- CN202311639531.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-30
- Publication Date
- 2025-05-30
AI Technical Summary
During the rear-section manufacturing process of semiconductor chips, the film strength of the chip protective layer is insufficient, resulting in crack problems easily occur during packaging.
The first dielectric layer is deposited on the first nitride layer by chemical vapor deposition, and the compressive stress reaches a specific value by adjusting the low-frequency energy parameters; the second dielectric layer is deposited on the metal liner layer and the compressive stress is adjusted in the same way; finally, the second nitride layer is deposited on the second dielectric layer, and the compressive stress is further adjusted to increase the compressive stress value of the overall structure.
By increasing the compressive stress values of the first dielectric layer, the second dielectric layer and the second nitride layer, the cracking problem during packaging is solved and the yield of the semiconductor chip is improved.
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Figure CN120072664A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a method for manufacturing the back-end of a semiconductor. Background Art
[0002] Semiconductors are used in fields such as integrated circuits, consumer electronics, communication systems, photovoltaic power generation, lighting, and high-power power conversion. For example, a diode is a device made of a semiconductor.
[0003] From the perspective of both technology and economic development, the importance of semiconductors is extremely great. The core units of most electronic products, such as computers, mobile phones, or digital recorders, are extremely closely related to semiconductors.
[0004] In related technologies, during the manufacturing process of semiconductor chips and other products, especially in the RV process and CB process of the back-end manufacturing, due to the insufficient strength of the film of the chip protective layer, cracks are likely to occur during packaging. Summary of the Invention
[0005] The purpose of the present disclosure is to provide a method for manufacturing the back-end of a semiconductor to solve the technical problems existing in related technologies.
[0006] To achieve the above purpose, the present disclosure provides a method for manufacturing the back-end of a semiconductor, and the back-end manufacturing method includes:
[0007] Providing a first nitride layer on a top metal layer;
[0008] Depositing a first dielectric layer on the first nitride layer by chemical vapor deposition, and adjusting the low-frequency energy parameter to make the compressive stress of the first dielectric layer a first compressive stress value;
[0009] Etching the first dielectric layer and the first nitride layer to form a first etching groove;
[0010] Providing a metal liner layer on the surface of the first dielectric layer and in the first etching groove;
[0011] Etching the metal liner layer;
[0012] Depositing a second dielectric layer on the metal liner layer by chemical vapor deposition, and adjusting the low-frequency energy parameter to make the compressive stress of the second dielectric layer a second compressive stress value;
[0013] Depositing a second nitride layer on the second dielectric layer by chemical vapor deposition, and adjusting the low-frequency energy parameter to make the compressive stress of the second nitride layer a third compressive stress value.
[0014] Optionally, etching the first dielectric layer and the first nitride layer to form a first etching groove includes:
[0015] Performing photolithographic masking on a partial surface of the first dielectric layer to form a first photoresist layer;
[0016] Etching the first dielectric layer and a part of the first nitride layer not protected by the first photoresist layer;
[0017] Removing the first photoresist layer;
[0018] Opening the first nitride layer to form the first etching groove communicating with the top metal layer.
[0019] Optionally, disposing a metal liner layer on the surface of the first dielectric layer and within the first etching groove includes:
[0020] Disposing a barrier layer on the surface of the first dielectric layer and the inner surface of the first etching groove;
[0021] Disposing an adhesive layer on the surface of the barrier layer;
[0022] Disposing a metal liner body layer on the surface of the adhesive layer;
[0023] Disposing an anti-reflection layer on the surface of the metal liner body layer;
[0024] Wherein, the metal liner layer includes the barrier layer, the adhesive layer, the metal liner body layer, and the anti-reflection layer.
[0025] Optionally, disposing a metal liner layer on the surface of the first dielectric layer and within the first etching groove further includes:
[0026] Disposing a second photoresist layer on a partial surface of the anti-reflection layer;
[0027] Etching the metal liner layer;
[0028] Removing the second photoresist layer;
[0029] Removing etching residues and photoresist residues in the etching process by wet cleaning;
[0030] Further removing polymer residues by a thermal oxidation ashing process.
[0031] Optionally, after depositing a second nitride layer on the second dielectric layer by chemical vapor deposition, the post-segment manufacturing method further includes:
[0032] Performing photolithographic masking on a partial surface of the second nitride layer to form a third photoresist layer;
[0033] Etch the second nitride layer, the second dielectric layer, and the anti-reflection layer that are not protected by the third photoresist layer.
[0034] Optionally, after etching the second nitride layer, the second dielectric layer, and the anti-reflection layer that are not protected by the third photoresist layer, the post-segment manufacturing method further includes:
[0035] Remove the third photoresist layer;
[0036] Remove the etch residues and photoresist residues in the etching process through wet cleaning;
[0037] Adopt a thermal oxidation ashing process to further remove polymer residues.
[0038] Optionally, the metal pad body layer is made of aluminum material.
[0039] Optionally, the first dielectric layer and the second dielectric layer are configured as silicon dioxide layers; the first nitride layer and the second nitride layer are configured as silicon nitride layers.
[0040] Optionally, the first compressive stress value of the first dielectric layer is between 2.6*10^8 Pa and 3.1*10^8 Pa; the second compressive stress value of the second dielectric layer is between 2.6*10^8 Pa and 3.1*10^8 Pa; the third compressive stress value of the second nitride layer is between 2.2*10^9 Pa and 2.7*10^9 Pa.
[0041] Optionally, the top metal layer is made of copper material.
[0042] In the above technical solution, the first dielectric layer is deposited on the first nitride layer by chemical vapor deposition, and the compressive stress of the first dielectric layer is made the first compressive stress value by adjusting the low-frequency energy parameters; and the second dielectric layer is deposited on the metal pad layer by chemical vapor deposition, and the compressive stress of the second dielectric layer is made the second compressive stress value by adjusting the low-frequency energy parameters; in addition, the second nitride layer is deposited on the second dielectric layer by chemical vapor deposition, and the compressive stress of the second nitride layer is made the third compressive stress value by adjusting the low-frequency energy parameters; thereby improving the compressive stress of the first dielectric layer, the second dielectric layer, and the second nitride layer, meeting the requirements of the compressive stress value, avoiding cracks during packaging, and improving the yield rate.
[0043] Other features and advantages of the present disclosure will be described in detail in the subsequent specific implementation section. Brief Description of the Drawings
[0044] The accompanying drawings are used to provide a further understanding of the present disclosure and form a part of the specification. Together with the following detailed description, they are used to explain the present disclosure, but do not limit the present disclosure. In the accompanying drawings:
[0045] Figure 1 is a flowchart of a method for manufacturing the back end of a semiconductor according to an embodiment of the present disclosure.
[0046] Figures 2 to 6 is the RV (Redistribution Via) process in a method for manufacturing the back end of a semiconductor according to an embodiment of the present disclosure, which is used to connect the top metal layer and the metal pad layer.
[0047] Figures 7 to 9 is the APL (Aluminum Pad Layer) process in a method for manufacturing the back end of a semiconductor according to an embodiment of the present disclosure. The main material is aluminum and it is used to connect external circuits.
[0048] Figures 10 to 12 is the CB (Chip Barrier) process in a method for manufacturing the back end of a semiconductor according to an embodiment of the present disclosure, which is used to protect the chip.
[0049] Description of Reference Numerals
[0050] 1. Top metal layer; 2. First nitrogen oxide layer; 3. First dielectric layer; 30. First photoresist layer; 4. Metal pad layer; 40. Second photoresist layer; 41. Barrier layer; 42. Glue layer; 43. Metal pad body layer; 44. Anti-reflection layer; 5. Second dielectric layer; 6. Second nitride layer; 60. Third photoresist layer; First etching groove 100. Detailed Description of the Embodiment
[0051] The following provides a detailed description of the specific embodiments of the present disclosure in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and do not limit the present disclosure.
[0052] Referring to Figures 1 to 12 as shown, the present disclosure provides a method for manufacturing the back end of a semiconductor, and the method for manufacturing the back end includes:
[0053] S11, disposing a first nitride layer 2 on the top metal layer 1;
[0054] S12, depositing a first dielectric layer 3 on the first nitride layer 2 by chemical vapor deposition, and adjusting the low-frequency energy parameters to make the compressive stress of the first dielectric layer 3 be a first compressive stress value;
[0055] S13, etching the first dielectric layer 3 and the first nitride layer 2 to form a first etching groove 100;
[0056] S14. A metal cushion layer 4 is disposed on the surface of the first dielectric layer 3 and within the first etching groove 100;
[0057] S15. Etch the metal cushion layer 4;
[0058] S16. Deposit a second dielectric layer 5 on the metal cushion layer 4 by chemical vapor deposition, and adjust the low-frequency energy parameters to make the compressive stress of the second dielectric layer 5 be a second compressive stress value;
[0059] S17. Deposit a second nitride layer 6 on the second dielectric layer 5 by chemical vapor deposition, and adjust the low-frequency energy parameters to make the compressive stress of the second nitride layer 6 be a third compressive stress value.
[0060] In the above technical solution, the first dielectric layer 3 is deposited on the first nitride layer 2 by chemical vapor deposition, and the low-frequency energy parameters are adjusted to make the compressive stress of the first dielectric layer 3 be a first compressive stress value; and the second dielectric layer 5 is deposited on the metal cushion layer 4 by chemical vapor deposition, and the low-frequency energy parameters are adjusted to make the compressive stress of the second dielectric layer 5 be a second compressive stress value; in addition, the second nitride layer 6 is deposited on the second dielectric layer 5 by chemical vapor deposition, and the low-frequency energy parameters are adjusted to make the compressive stress of the second nitride layer 6 be a third compressive stress value; thereby improving the compressive stress of the first dielectric layer 3, the second dielectric layer 5, and the second nitride layer 6, meeting the requirements of the compressive stress value, avoiding cracks during encapsulation, and improving the yield rate.
[0061] Optionally, the first compressive stress value of the first dielectric layer 3 is between 2.6×10^8 Pa and 3.1×10^8 Pa; the second compressive stress value of the second dielectric layer 5 is between 2.6×10^8 Pa and 3.1×10^8 Pa; the third compressive stress value of the second nitride layer 6 is between 2.2×10^9 Pa and 2.7×10^9 Pa. This makes the compressive stresses of the first dielectric layer 3, the second dielectric layer 5, and the second nitride layer 6 meet the requirements.
[0062] For example, the first compressive stress value of the first dielectric layer 3 can be 2.6×10^8 Pa, or the first compressive stress value of the first dielectric layer 3 can be 3.1×10^8 Pa, or the first compressive stress value of the first dielectric layer 3 can be 2.8×10^8 Pa.
[0063] For example, the second compressive stress value of the second dielectric layer 5 can be 2.6×10^8 Pa, or the second compressive stress value of the second dielectric layer 5 can be 3.1×10^8 Pa, or the second compressive stress value of the second dielectric layer 5 can be 2.8×10^8 Pa.
[0064] For example, the third compressive stress value of the second nitride layer 6 may be 2.2×10^9 Pa, or the third compressive stress value of the second nitride layer 6 may be 2.7×10^9 Pa, or the third compressive stress value of the second nitride layer 6 may be 2.5×10^9 Pa.
[0065] In addition, the compressive stress of the first dielectric layer 3 can be made to be the first compressive stress value by adjusting the low-frequency energy parameter to be 20% higher than the original low-frequency energy parameter; the compressive stress of the second dielectric layer 5 can be made to be the second compressive stress value by adjusting the low-frequency energy parameter to be 20% higher than the original low-frequency energy parameter; the compressive stress of the second nitride layer 6 can be made to be the third compressive stress value by adjusting the low-frequency energy parameter to be 20% higher than the original low-frequency energy parameter. However, the present disclosure does not specifically limit the low-frequency energy parameter.
[0066] Optionally, referring to Figure 1 、 Figures 2 to 6 as shown, etching the first dielectric layer 3 and the first nitride layer 2 to form a first etching groove 100 includes: performing photolithographic masking on a partial surface of the first dielectric layer 3 to form a first photoresist layer 30; etching the first dielectric layer 3 not protected by the first photoresist layer 30 and a partial first nitride layer 2; removing the first photoresist layer 30; opening the first nitride layer 2 to form a first etching groove 100 communicating with the top metal layer 1.
[0067] In this embodiment, etching can be performed using an etching machine. The etching machine ionizes a fluorine-based or chlorine-based gas in a vacuum reaction chamber using high-power radio frequency energy. The radio frequency energy decomposes molecules and ionizes atoms, filling the reaction chamber with various plasma components. These plasma components remove the silicon located as an isolation region on the silicon wafer through physical etching and chemical etching. After each etching process is completed, the silicon wafer needs to be de-glued and cleaned in a series of chemical reagents. In addition, the above-mentioned first photoresist layer 30 can be formed by directly imprinting the pattern of a specific mask on the semiconductor device coated with glue using a lithography machine. The imprinted pattern of the first photoresist layer 30 is used to protect those regions of the semiconductor device that do not need to be etched.
[0068] Referring to Figures 7 to 9 as shown, a metal liner layer 4 is disposed on the surface of the first dielectric layer 3 and inside the first etching groove 100, including: disposing a barrier layer 41 on the surface of the first dielectric layer 3 and the inner surface of the first etching groove 100; disposing an adhesive layer 42 on the surface of the barrier layer 41; disposing a metal liner body layer 43 on the surface of the adhesive layer 42; disposing an anti-reflection layer 44 on the surface of the metal liner body layer 43; wherein, the metal liner layer 4 includes the barrier layer 41, the adhesive layer 42, the metal liner body layer 43, and the anti-reflection layer 44.
[0069] In this embodiment, by providing the barrier layer 41, the metal of the metal gasket body layer 4 can be effectively blocked from entering the top metal layer 1, playing a good blocking role. Secondly, the glue layer 42 can enhance the connection stability. The metal gasket body layer 43 can be made of aluminum, but the present disclosure does not limit the specific material of the metal gasket body layer 43. The anti-reflection layer 44 is used to absorb the lithography reflected light.
[0070] Optionally, as shown in Figures 7 to 9 , a metal gasket layer 4 is provided on the surface of the first dielectric layer 3 and in the first etching groove 100, and further includes: providing a second photoresist layer 40 on a partial surface of the anti-reflection layer 44; etching the metal gasket layer 4; removing the second photoresist layer 40; removing the etching residues and photoresist residues in the etching process by wet cleaning; and further removing the polymer residues by a thermal oxidation ashing process.
[0071] The above-mentioned second photoresist layer 40 can use a lithography machine to directly print the pattern of a specific mask on the photoresist-coated semiconductor device, and the printed pattern of the second photoresist layer 40 is used to protect the areas of the semiconductor device that do not need to be etched.
[0072] In other embodiments, as shown in Figures 10 to 12 , after depositing the second nitride layer 6 on the second dielectric layer 5 by chemical vapor deposition, the back-end manufacturing method further includes: performing a photolithography mask on a partial surface of the second nitride layer 6 to form a third photoresist layer 60; etching the second nitride layer 6, the second dielectric layer 5, and the anti-reflection layer 44 that are not protected by the third photoresist layer 60.
[0073] The above-mentioned third photoresist layer 60 can use a lithography machine to directly print the pattern of a specific mask on the photoresist-coated semiconductor device, and the printed pattern of the third photoresist layer 60 is used to protect the areas of the semiconductor device that do not need to be etched.
[0074] In another embodiment, after etching the second nitride layer 6, the second dielectric layer 5, and the anti-reflection layer 44 that are not protected by the third photoresist layer 60, the back-end manufacturing method further includes: removing the third photoresist layer 60; removing the etching residues and photoresist residues in the etching process by wet cleaning; and further removing the polymer residues by a thermal oxidation ashing process to improve the yield.
[0075] Optionally, the above-mentioned first dielectric layer 3 and second dielectric layer 5 may be configured as silicon dioxide layers; the first nitride layer 2 and second nitride layer 6 may be configured as silicon nitride layers, but the present disclosure does not limit the specific materials of the first dielectric layer 3, second dielectric layer 5, first nitride layer 2, and second nitride layer 6. Additionally, the above-mentioned top metal layer 1 may be made of copper, but the present disclosure also does not limit the specific material of the top metal layer 1.
[0076] The preferred embodiments of the present disclosure have been described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0077] In addition, it should be noted that, among the various specific technical features described in the above specific embodiments, without conflict, they can be combined in any suitable manner. To avoid unnecessary repetition, the present disclosure will not separately describe various possible combination methods.
[0078] Furthermore, any combination can be made between various different embodiments of the present disclosure, as long as it does not violate the idea of the present disclosure, and it should also be regarded as the content disclosed by the present disclosure.
Claims
1. A method for fabricating the backend of a semiconductor, characterized in that, the backend fabrication method includes: providing a first nitride layer on a top metal layer; depositing a first dielectric layer on the first nitride layer by chemical vapor deposition, and adjusting low-frequency energy parameters to make the compressive stress of the first dielectric layer be a first compressive stress value; etching the first dielectric layer and the first nitride layer to form a first etch groove; providing a metal liner layer on the surface of the first dielectric layer and within the first etch groove; etching the metal liner layer; depositing a second dielectric layer on the metal liner layer by chemical vapor deposition, and adjusting low-frequency energy parameters to make the compressive stress of the second dielectric layer be a second compressive stress value; depositing a second nitride layer on the second dielectric layer by chemical vapor deposition, and adjusting low-frequency energy parameters to make the compressive stress of the second nitride layer be a third compressive stress value.
2. The method for fabricating the backend of a semiconductor according to claim 1, characterized in that, the etching of the first dielectric layer and the first nitride layer to form a first etch groove includes: performing photolithographic masking on a partial surface of the first dielectric layer to form a first photoresist layer; etching the first dielectric layer and a partial portion of the first nitride layer not protected by the first photoresist layer; removing the first photoresist layer; opening the first nitride layer to form the first etch groove communicating with the top metal layer.
3. The method for fabricating the backend of a semiconductor according to claim 1, characterized in that, the providing of a metal liner layer on the surface of the first dielectric layer and within the first etch groove includes: providing a barrier layer on the surface of the first dielectric layer and the inner surface of the first etch groove; providing an adhesive layer on the surface of the barrier layer; providing a metal liner body layer on the surface of the adhesive layer; providing an anti-reflection layer on the surface of the metal liner body layer; wherein, the metal liner layer includes the barrier layer, the adhesive layer, the metal liner body layer, and the anti-reflection layer.
4. The method for fabricating the backend of a semiconductor according to claim 3, characterized in that, the providing of a metal liner layer on the surface of the first dielectric layer and within the first etch groove further includes: performing photolithographic masking on a partial surface of the anti-reflection layer to form a second photoresist layer; etching the metal liner layer; removing the second photoresist layer; removing etch residues and photoresist residues in the etching process by wet cleaning; further removing polymer residues by a thermal oxidation ashing process.
5. The method for fabricating the backend of a semiconductor according to claim 3, characterized in that, after depositing a second nitride layer on the second dielectric layer by chemical vapor deposition, the backend fabrication method further includes: performing photolithographic masking on a partial surface of the second nitride layer to form a third photoresist layer; etching the second nitride layer, the second dielectric layer, and the anti-reflection layer not protected by the third photoresist layer.
6. The method for fabricating the backend of a semiconductor according to claim 5, It is characterized in that after etching the second nitride layer, the second dielectric layer, and the anti-reflection layer that are not protected by the third photoresist layer, the post-section manufacturing method further includes: removing the third photoresist layer; removing etch residues and photoresist residues in the etching process through wet cleaning; further removing polymer residues by using a thermal oxidation ashing process.
7. The post-section manufacturing method of a semiconductor according to claim 3, It is characterized in that the metal pad body layer is made of aluminum.
8. The post-section manufacturing method of a semiconductor according to any one of claims 1-7, It is characterized in that the first dielectric layer and the second dielectric layer are configured as silicon dioxide layers; the first nitride layer and the second nitride layer are configured as silicon nitride layers.
9. The post-section manufacturing method of a semiconductor according to claim 8, It is characterized in that the first compressive stress value of the first dielectric layer is between 2.6*10^8 Pa and 3.1*10^8 Pa; the second compressive stress value of the second dielectric layer is between 2.6*10^8 Pa and 3.1*10^8 Pa; the third compressive stress value of the second nitride layer is between 2.2*10^9 Pa and 2.7*10^9 Pa.
10. The post-section manufacturing method of a semiconductor according to any one of claims 1-7, It is characterized in that the top metal layer is made of copper.