Defective structure manufacturing method and wafer defect detection method
By thinning the substrate wafer and forming defect structures, and using defect scanning machines to detect defect structures, the problem of difficulty in detecting internal defects of wafers is solved, and efficient defect detection and cost reduction are achieved.
Patent Information
- Application Number
- CN202311610860.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-28
- Publication Date
- 2025-05-30
AI Technical Summary
Traditional optical methods are difficult to detect defects inside the substrate wafer, resulting in increased physical and electrical failure efficiency of the chip.
By thinning the first wafer with surface exposed defective particles formed by thinning the wafer to be detected, and forming an auxiliary layer on its surface, forming a defect structure, and the number and size of the defective structure are detected by using a defect scanning machine.
It realizes effective detection of internal defects of wafers, reduces detection costs, and facilitates defect detection across process nodes.
Smart Images
Figure CN120072669A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuit manufacturing processes, and particularly to a method for fabricating a defect structure and a method for detecting wafer defects. Background Art
[0002] In the manufacture of semiconductor integrated circuits, particles or defects may be introduced during various process steps. The impact of these particles or defects on the quality of integrated circuits is becoming increasingly significant, and the necessity and importance of on-line defect detection are increasing day by day.
[0003] The process of fabricating a substrate wafer is generally as follows: First, an ingot is formed by crystal pulling, then the ingot is cut to form a blank wafer, and then the blank wafer is subjected to a grinding and profiling process to form a substrate wafer. However, defects are generated during the crystal pulling process. When these substrate wafers enter the semiconductor manufacturing process, the physical failure rate and electrical failure rate of the chips will increase. Since the defects in the substrate wafer exist inside the substrate wafer, traditional optical methods can only detect the defects on the surface of the substrate. How to detect the defects inside the substrate wafer has become an urgent problem to be solved. Summary of the Invention
[0004] Based on this, it is necessary to provide a method for fabricating a defect structure and a method for detecting wafer defects in view of the above problems.
[0005] A method for fabricating a defect structure, the defect structure being used to assist in detecting defects of a wafer to be detected, the method for fabricating the defect structure comprising:
[0006] Thinning the wafer to be detected by a first preset thickness to form a first wafer with the defects to be detected on the surface exposed;
[0007] Forming an auxiliary layer on the surface of the first wafer; the auxiliary layer surrounds the side surface of the defect particle to be detected and together with the defect particle to be detected constitutes a defect structure.
[0008] The method for fabricating a defect structure provided by the embodiments of the present application thins the wafer to be detected by a first preset thickness, so that the defects to be detected on the wafer to be detected are exposed on the surface of the first wafer, and then an auxiliary layer is formed on the surface of the first wafer. The auxiliary layer and the defects to be detected together constitute a defect structure. In this way, the outer diameter size of the defects to be detected can be enlarged through the defect structure. Thus, the defect structure can be detected by a defect scanner to obtain the quantity and size of the defect structure, which is convenient for process personnel to analyze the quantity and size of the defects to be detected. This defect structure helps to realize defect detection across process nodes, that is, detecting smaller-sized defect particles through a low-precision process machine, which not only helps to detect the internal defects of the wafer, but also helps to reduce the detection cost.
[0009] In one embodiment, the wafer to be detected has a preset depth for fabricating semiconductor devices, and the first preset thickness is less than or equal to the preset depth.
[0010] In one embodiment, the step of thinning the wafer to be detected by the first preset thickness to form a first wafer with the surface exposing defect particles to be detected includes:
[0011] Selectively etching the wafer to be detected by using a first dry etching process to remove the wafer material of the wafer to be detected and retain the defect particles to be detected on the surface of the first wafer.
[0012] In one embodiment, the process gas of the first dry etching process includes chlorine, hydrogen bromide, oxygen, and a helium-oxygen mixture.
[0013] In one embodiment, in the process gas of the first dry etching process, the flow rate of chlorine is greater than or equal to 10 sccm and less than or equal to 40 sccm, the flow rate of hydrogen bromide is greater than or equal to 100 sccm and less than or equal to 300 sccm, the flow rate of oxygen is greater than or equal to 20 sccm and less than or equal to 100 sccm, and the flow rate of the helium-oxygen mixture is greater than 0 sccm and less than or equal to 20 sccm.
[0014] In one embodiment, the chamber pressure of the first dry etching process is greater than or equal to 10 mTorr and less than or equal to 80 mTorr;
[0015] The source RF power of the first dry etching process is greater than or equal to 100 watts and less than or equal to 1000 watts;
[0016] The bias RF power of the first dry etching process is greater than or equal to -150 watts and less than or equal to 400 watts;
[0017] The process time of the first dry etching process is greater than or equal to 95 s and less than or equal to 1160 s.
[0018] In one embodiment, the step of forming an auxiliary layer on the surface of the first wafer includes:
[0019] Forming an auxiliary material layer on the first wafer, and the auxiliary material layer covers the surface of the first wafer and the surface of the defect particles to be detected;
[0020] Etching the auxiliary material layer by using a second dry etching process to form the auxiliary layer.
[0021] In one embodiment, the material of the auxiliary material layer includes at least one of silicon dioxide and silicon nitride.
[0022] In a second aspect, an embodiment of the present application provides a method for detecting wafer defects. Specifically, the defect structure fabricated by using the defect structure fabrication method in the first aspect is detected, and the quantity and size of the defect structure are obtained.
[0023] In one embodiment, a defect scanner is used to scan and detect the defect structure.
[0024] The distance between the surface of the auxiliary layer close to the defect particle to be detected and the surface of the auxiliary layer far from the defect particle to be detected, the minimum scan size of the defect scanner, and the outer diameter of the defect particle to be detected satisfy the following relational expression:
[0025] 2H + D ≥ L;
[0026] Wherein, H is the distance between the surface of the auxiliary layer close to the defect particle to be detected and the surface of the auxiliary layer far from the defect particle to be detected, D is the outer diameter of the defect particle to be detected, and L is the minimum scan size of the defect scanner.
[0027] The method for detecting wafer defects provided by the embodiment of the present application detects the defect structure to obtain the quantity and size of the defect structure, which is convenient for process personnel to analyze the quantity and size of the particles to be detected in the wafer to be detected. This detection method can achieve defect detection across process nodes, that is, detecting smaller-sized defect particles through a low-precision process machine, which not only realizes the detection of internal defects in the wafer but also helps to reduce the detection cost. Description of the Drawings
[0028] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments or exemplary embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0029] Figure 1 It is a schematic diagram of the wafer manufacturing process in the traditional technology.
[0030] Figure 2 For Figure 1 It is a schematic diagram from a blank wafer to a substrate wafer as shown.
[0031] Figure 3 It is a schematic flow diagram of a defect structure fabrication method provided by an embodiment of the present application.
[0032] Figure 4 For Figure 3Schematic structural diagram in the manufacturing method process shown
[0033] Figure 5 is Figure 4 Schematic structural diagram of the wafer to be detected shown in
[0034] Figure 6 Schematic diagram of the size and quantity distribution of wafer defects at a specific depth provided by an embodiment of the present application
[0035] Figure 7 Schematic diagram of the size and quantity distribution of wafer defects at different depths provided by an embodiment of the present application
[0036] Reference numerals:
[0037] 11, ingot; 12, blank wafer; 13, substrate wafer; 14, defect
[0038] 21, wafer to be detected; 22, first wafer; 23, defect particle to be detected; 24, auxiliary material layer; 25, auxiliary layer; 26, defect structure Detailed implementation manners
[0039] To make the above objects, features, and advantages of the present application more apparent and understandable, the following will describe the detailed implementation manners of the present application with reference to the accompanying drawings. Many specific details are set forth in the following description to fully understand the present application. However, the present application can be implemented in many other ways different from those described herein. Those skilled in the art can make similar improvements without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application
[0041] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below could be denoted as a second element, component, region, layer, or portion.
[0042] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also have other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0043] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / have", etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the related listed items.
[0044] Embodiments of the present application are described with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, so that variations in the shapes shown can be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the figures are substantially schematic, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.
[0045] As described in the background art, with reference to Figure 1 shown, the manufacturing process of the substrate wafer 13 is generally as follows: First, an ingot 11 is formed by pulling a crystal, then the ingot 11 is cut to form a blank wafer 12, and then the blank wafer 12 is subjected to a grinding and profiling process to form the substrate wafer 13. Further referring to Figure 2 shown, defects 14 will be generated during the crystal pulling process. These defects 14 are located inside the blank wafer 12. After the grinding and profiling process, even if a part is removed, defects 14 still exist in the substrate wafer 13. The inflow of these substrate wafers 13 into the semiconductor manufacturing process will cause an increase in the physical failure rate and electrical failure rate of the chips. Since the defect 14 exists inside the substrate wafer 13, traditional optical methods can only detect the defects 14 on the surface of the substrate. How to detect the defects 14 inside the substrate wafer 13 has become an urgent problem to be solved.
[0046] To solve the above problems, embodiments of the present application provide a method for manufacturing a defect structure and a method for detecting wafer defects. Among them, the defect structure can enlarge the outer diameter size of the defect particles to be detected, which helps to achieve defect detection across process nodes, that is: detecting smaller-sized defect particles through a low-precision process machine tool not only helps to detect the defects inside the wafer, but also helps to reduce the detection cost.
[0047] In a first aspect, with reference to Figure 3 and in combination with Figure 4 shown, embodiments of the present application provide a method for manufacturing a defect structure, which is used to assist in detecting the defects of a wafer to be detected. The method for manufacturing the defect structure specifically includes the following steps:
[0048] S100: Thinning the wafer 21 to be detected by a first preset thickness to form a first wafer 22 with the surface exposing the defect particles 23 to be detected. Here, the wafer 21 to be detected is the substrate wafer. The first wafer 22 refers to the wafer formed after thinning the wafer 21 to be detected. In one example, the wafer 21 to be detected can be etched through an etching process to achieve the thinning of the wafer 21 to be detected.
[0049] Here, it should be noted that, as shown in FIGS. (a), (b), and (c) in Figure 4 During the thinning process, only the self-material of the wafer 21 to be detected is removed, and the defect particles in the wafer 21 to be detected are not removed. This step is to ensure that after the wafer 21 to be detected is thinned by the first preset thickness, the defect particles 23 to be detected on the surface of the first wafer 22 are retained, facilitating the detection of the defect particles 23 to be detected in the subsequent steps.
[0050] S200: Forming an auxiliary layer 25 on the surface of the first wafer 22. The auxiliary layer 25 surrounds the side surface of the defect particles 23 to be detected and jointly forms a defect structure 26 with the defect particles 23 to be detected. Exemplarily, the auxiliary layer 25 can be formed through a thin film deposition process. In a specific example, the auxiliary layer 25 can be formed through a chemical vapor deposition process and an etching process.
[0051] It should be noted that the defect particles 23 to be detected have a bottom surface and a top surface arranged oppositely, where the bottom surface is in contact with the surface of the first wafer 22, and the surface connecting the top surface and the bottom surface is the side surface. In one example, the auxiliary layer 25 surrounds the outer periphery of the defect particles 23 to be detected, and the outer periphery of the defect particles 23 to be detected is the side surface of the defect particles 23 to be detected.
[0052] The method for fabricating the defect structure provided by the embodiments of the present application thins the wafer 21 to be detected by a first preset thickness, exposing the defect particles 23 to be detected on the surface of the first wafer 22, and then forming an auxiliary layer 25 on the surface of the first wafer 22. The auxiliary layer 25 and the defect particles 23 to be detected jointly form a defect structure 26. In this way, the outer diameter size of the defect particles 23 to be detected can be enlarged through the defect structure 26. Thus, by scanning and detecting the defect structure 26 with a defect scanner, the quantity and size of the defect structure 26 can be obtained, facilitating the process personnel to analyze the quantity and size of the particles to be detected in the wafer to be detected. This defect structure helps to achieve defect detection across process nodes, that is: detecting smaller-sized defect particles through a low-precision process machine tool not only helps to detect internal defects of the wafer but also helps to reduce the detection cost.
[0053] In one of the embodiments, referring to Figure 5As shown, the wafer 21 to be detected has a preset depth a for fabricating semiconductor devices, and the first preset thickness is less than or equal to the preset depth a.
[0054] Here, the preset depth refers to the physical depth of the wafer 21 to be detected for fabricating semiconductor devices. Therefore, detecting the defective particles within this physical depth is of great significance for the semiconductor manufacturing process. In the embodiments of the present application, by making the first preset thickness less than or equal to the preset depth, the defective particles within the physical depth can be detected more accurately.
[0055] In one of the embodiments, S100 specifically includes the following steps:
[0056] S110: Use the first dry etching process to selectively etch the wafer 21 to be detected, so as to remove the wafer material of the wafer 21 to be detected and retain the defective particles 23 to be detected on the surface of the first wafer 22. By using the dry etching process, on the one hand, it is convenient to selectively etch the wafer 21 to be detected and retain the defective particles 23 to be detected; on the other hand, compared with wet etching, the by-product impurities of dry etching are less, which can reduce the influence of by-product impurities on the detection accuracy.
[0057] In one of the embodiments, the process gas of the first dry etching process includes chlorine, hydrogen bromide, oxygen, and helium-oxygen mixture.
[0058] It should be noted that the types and particle size distributions of the defective particles inside the wafer 21 to be detected are as follows:
[0059] Table of types and particle size distributions of defective particles
[0060] Number Type of defective particles Particle size range 1 <![CDATA[SiO 2 > 0.15 - 0.25um 2 <![CDATA[Fe 3 O 4 > 0.02 - 0.04um 3 <![CDATA[Al 2 O 3 > 0.02 - 0.04um 4 Cr <0.04um 5 Fe <0.04um 6 Ni <0.04um 7 Au 0.045 - 0.065um 8 Ag 0.045 - 0.065um
[0061] It can be seen from the above table that the types of defective particles are relatively complex. The combination of the above process gases has, on the one hand, a high selectivity for silicon dioxide. Exemplarily, the etching rate of silicon is 90 times that of silicon dioxide; on the other hand, it has almost no etching effect on metal particles. Therefore, the above process gases can preferably retain the defective particles on the premise of being able to etch silicon.
[0062] In one of the embodiments, in the process gas of the first dry etching process, the flow rate of chlorine is greater than or equal to 10 sccm and less than or equal to 40 sccm, the flow rate of hydrogen bromide is greater than or equal to 100 sccm and less than or equal to 300 sccm, the flow rate of oxygen is greater than or equal to 20 sccm and less than or equal to 100 sccm, and the flow rate of the helium-oxygen mixture is greater than 0 sccm and less than or equal to 20 sccm. By making the flow rate of the process gas within the above range, on the one hand, it can have a high etching rate for silicon, and on the other hand, it can have a high selectivity for defective particles.
[0063] In one embodiment, the chamber pressure of the first dry etching process is greater than or equal to 10 mTorr and less than or equal to 80 mTorr. The source RF power of the first dry etching process is greater than or equal to 100 Watts and less than or equal to 1000 Watts. The bias RF power of the first dry etching process is greater than or equal to -150 Watts and less than or equal to 400 Watts. The process time of the first dry etching process is greater than or equal to 95 s and less than or equal to 1160 s. By making the process parameters of the first dry etching process within the above ranges, it is beneficial to etch the wafer.
[0064] It should be noted that the first dry etching process may include multiple sub-steps. When the value of the first preset thickness is different, the process parameters of a certain sub-step can be adjusted to meet different etching depths.
[0065] In one embodiment, referring to Figure 4 Figures (d) and (e) in, S200: Form an auxiliary layer 25 on the surface of the first wafer 22. The auxiliary layer 25 surrounds the side surface of the defect particle 23 to be detected and together with the defect particle 23 to be detected constitutes a defect structure 26, which specifically includes the following steps:
[0066] S210: Form an auxiliary material layer 24 on the first wafer 22. The auxiliary material layer 24 covers the surface of the first wafer 22 and the surface of the defect particle 23 to be detected. Specifically, an auxiliary material layer 24 with a second preset thickness can be formed. Exemplarily, the auxiliary material layer 24 can be formed by a thin film deposition process. In a specific example, the auxiliary material layer 24 can be formed by a chemical vapor deposition process.
[0067] S220: Use a second dry etching process to etch the auxiliary material layer 24 to form the auxiliary layer 25.
[0068] By using a dry etching process, on the one hand, it is convenient to selectively etch the auxiliary material layer 24; on the other hand, compared with wet etching, the by-product impurities of dry etching are less, which can reduce the influence of by-product impurities on the detection accuracy.
[0069] In one embodiment, when detecting a defect, a defect scanner is used to scan the defect structure. Specifically, the second preset thickness, the minimum scan size of the defect scanner, and the outer diameter of the defect particle 23 to be detected satisfy the following relationship:
[0070] 2H + D ≥ L
[0071] Wherein, H is the second preset thickness, D is the outer diameter of the defect particle 23 to be detected, and L is the minimum scanning size of the defect scanning stage. Here, the minimum scanning size of the defect scanning stage is the maximum scanning accuracy of the defect scanning stage.
[0072] Here, 2H + D can be understood as the outer diameter size of the defect structure 26. By controlling the second preset thickness of the auxiliary material layer 24 and making the second preset thickness satisfy the above relationship, it is possible to ensure the accurate scanning of the defect scanning stage for the defect particle 23 to be detected.
[0073] In a specific example, the minimum scanning size of the defect scanning stage is 90 nm, the second preset thickness is 50 nm, and the enlarged sizes of the outer diameters of the defect particles 23 to be detected with different outer diameters are shown in the following table:
[0074] D (nm) H (nm) 2H + D (nm) L (nm) 90 0 90 90 65 50 165 90 45 50 145 90 32 50 132 90 28 50 128 90 12 50 112 90
[0075] It can be seen from the above table that on the premise that the second preset thickness is 50 nm, the defect particle 23 to be detected with an outer diameter of 12 nm can be enlarged to 112 nm, thus meeting the scanning accuracy of the defect scanning stage. It can be seen that the manufacturing method provided by the embodiments of the present application helps to achieve defect detection across process nodes, that is: detecting smaller-sized defect particles through a low-precision process stage not only helps to detect internal defects of the wafer but also helps to reduce the detection cost.
[0076] Here, it should be noted that the second preset thickness can be deduced by the minimum scanning size of the defect scanning stage and the minimum outer diameter of the defect particle 23 to be detected. Exemplarily, there are many types of particle sizes of the defect particles on the surface of the first wafer 22, such as 5 nm, 10 nm, 20 nm, 50 nm, etc. However, in actual semiconductor devices, only defect particles with a diameter greater than or equal to 20 nm affect the performance of the semiconductor device. Then, the defect particles with a diameter greater than or equal to 20 nm are defined as the defect particles 23 to be detected, and substituting 20 nm and the minimum scanning size of the defect scanning stage into the above formula, the second preset thickness can be obtained.
[0077] In one of the embodiments, the material of the auxiliary material layer 24 includes at least one of silicon dioxide and silicon nitride.
[0078] In one of the embodiments, the material of the auxiliary material layer 24 is silicon dioxide. The process gases of the second dry etching process include oxygen, carbon tetrafluoride, trifluoromethane, argon, octafluorocyclobutane, and carbon monoxide. The combination of the above process gases, on the one hand, has a high etching rate for silicon dioxide, and on the other hand, hardly corrodes metal particles, which is beneficial to retaining the defect particles 23 made of metal material.
[0079] In one embodiment, in the process gas of the second dry etching process, the flow rate of oxygen is greater than or equal to 5 sccm and less than or equal to 35 sccm, the flow rate of carbon tetrafluoride is greater than or equal to 5 sccm and less than or equal to 70 sccm, the flow rate of trifluoromethane is greater than or equal to 5 sccm and less than or equal to 90 sccm, the flow rate of argon is greater than or equal to 20 sccm and less than or equal to 350 sccm, the flow rate of octafluorocyclobutane is greater than 0 sccm and less than or equal to 20 sccm, and the flow rate of carbon monoxide is greater than 100 sccm and less than or equal to 350 sccm. By making the flow rate of the process gas within the above range, on the one hand, a higher etching rate for silicon dioxide can be achieved, and on the other hand, a higher selectivity for the defect particles 23 to be detected made of metal materials can be obtained.
[0080] In one embodiment, the chamber pressure of the second dry etching process is greater than or equal to 2 mTorr and less than or equal to 350 mTorr. The bias RF power of the second dry etching process is greater than or equal to 50 W and less than or equal to 1000 W. The process time of the second dry etching process is greater than or equal to 15 s and less than or equal to 520 s. By making the process parameters of the second dry etching process within the above range, it is beneficial to etch the auxiliary material layer 24.
[0081] In one embodiment, the material of the auxiliary material layer 24 is silicon nitride. The process gas of the second dry etching process includes oxygen, argon, and fluoromethane. The combination of the above process gases has, on the one hand, a higher etching rate for silicon nitride, and on the other hand, hardly corrodes the defect particles 23 to be detected, which is beneficial to retaining the defect particles 23 to be detected.
[0082] In one embodiment, in the process gas of the second dry etching process, the flow rate of oxygen is greater than or equal to 10 sccm and less than or equal to 100 sccm, the flow rate of argon is greater than or equal to 10 sccm and less than or equal to 100 sccm, and the flow rate of fluoromethane is greater than or equal to 10 sccm and less than or equal to 90 sccm. By making the flow rate of the process gas within the above range, on the one hand, a higher etching rate for silicon nitride can be achieved, and on the other hand, a higher selectivity for the defect particles 23 to be detected can be obtained.
[0083] In one embodiment, the chamber pressure of the second dry etching process is greater than or equal to 20 mTorr and less than or equal to 200 mTorr. The bias RF power of the second dry etching process is greater than or equal to 85 W and less than or equal to 355 W. The process time of the second dry etching process is greater than or equal to 10 s and less than or equal to 500 s. By making the process parameters of the second dry etching process within the above range, it is beneficial to etch the auxiliary material layer 24.
[0084] It can be understood that the process time of the second dry etching process is related to the second preset thickness of the auxiliary material layer 24. The second dry etching process includes multiple sub-steps. When the second preset thickness is different, the process parameters of a certain step in the second dry etching process can be adjusted to adjust the process time.
[0085] In a second aspect, an embodiment of the present application provides a method for detecting wafer defects. Specifically, the defect structure fabricated by the method for fabricating a defect structure described in any one of the embodiments in the first aspect is detected, and the number and size of the defect structure are obtained. Here, the size of the defect structure refers to the outer diameter of the defect structure.
[0086] The method for detecting wafer defects provided by the embodiment of the present application obtains the number and size of the defect structure by detecting the defect structure, which is convenient for process personnel to analyze the number and size of the particles to be detected in the wafer to be detected. This detection method can achieve defect detection across process nodes, that is, by using a low-precision process machine to detect smaller-sized defect particles, it not only realizes the detection of internal defects in the wafer but also helps to reduce the detection cost. In addition, this detection method can accurately identify the quality of wafers in the same batch.
[0087] In one of the embodiments, a defect scanner is used to scan and detect the defect structure.
[0088] Specifically, the distance between the surface of the auxiliary layer close to the particle to be detected and the surface of the auxiliary layer far from the particle to be detected, the minimum scan size of the defect scanner, and the outer diameter of the particle to be detected satisfy the following relational expression:
[0089] 2H + D ≥ L
[0090] Wherein, H is the distance between the surface of the auxiliary layer close to the particle to be detected and the surface of the auxiliary layer far from the particle to be detected, D is the outer diameter of the particle to be detected, and L is the minimum scan size of the defect scanner.
[0091] Here, it should be noted that the distance between the surface of the auxiliary layer close to the particle to be detected and the surface of the auxiliary layer far from the particle to be detected can be understood as the thickness of the auxiliary layer. Further, the thickness of the auxiliary layer is equal to the thickness of the second auxiliary layer in the embodiment of the first aspect.
[0092] It can be understood that the relationship that H, D, and L in the embodiment of the present application need to satisfy is the same as the relationship that H, D, and L in the embodiment of the first aspect need to satisfy, and the embodiment of the present application will not elaborate here.
[0093] The applicant detected the defect particles of the wafer according to the detection method in the embodiment of the present application. Figure 6Schematic diagram of the size and number distribution of defective particles on different wafers at a specific depth. Figure 7 Schematic diagram of the size and number distribution of defective particles at different depths of the wafer. It can be seen from the figure that the deeper the etching depth of the wafer, the more the number of defective particles, that is: the higher the requirements for the wafer in evaluating semiconductor devices, and it shows a proportional linear relationship.
[0094] In a third aspect, an embodiment of the present application provides a method for detecting wafer defects, which specifically includes the following steps:
[0095] S10: Thinning the wafer to be detected by a first preset thickness to form a first wafer with the surface exposing the defective particles to be detected.
[0096] S20: Forming an auxiliary layer on the surface of the first wafer. The auxiliary layer surrounds the side surface of the defective particles to be detected and together with the defective particles to be detected constitutes a defective structure.
[0097] S30: Detecting the defective structure to obtain the number and size of the defective structure.
[0098] The method for detecting wafer defects provided by the embodiment of the present application thins the wafer to be detected by a first preset thickness, so that the defective particles to be detected on the wafer to be detected are exposed on the surface of the first wafer. Then, an auxiliary layer is formed on the surface of the first wafer. The auxiliary layer and the defective particles to be detected together constitute a defective structure. In this way, the outer diameter size of the defective particles to be detected can be enlarged. By scanning the defective structure with a defect scanner, the number and size of the defective structure are obtained, which is convenient for process personnel to further analyze. This detection method can achieve defect detection across process nodes, that is: detecting smaller-sized defective particles through a low-precision process machine tool, which not only realizes the detection of internal defects of the wafer, but also helps to reduce the detection cost. In addition, this detection method can accurately identify the quality of wafers in the same batch.
[0099] It should be understood that in the embodiment of the present application, at least a part of the steps in the drawings may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps in other steps.
[0100] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.
[0101] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.
Claims
1. A method for fabricating a defect structure, the defect structure being used to assist in detecting defects of a wafer to be detected, characterized in that, the method for fabricating the defect structure includes: thinning the wafer to be detected by a first preset thickness to form a first wafer with a surface exposing the defect particles to be detected; forming an auxiliary layer on the surface of the first wafer; the auxiliary layer surrounds the side surface of the defect particles to be detected and together with the defect particles to be detected constitutes a defect structure.
2. The method for fabricating a defect structure according to claim 1, characterized in that, the wafer to be detected has a preset depth for fabricating semiconductor devices, and the first preset thickness is less than or equal to the preset depth.
3. The method for fabricating a defect structure according to claim 1, characterized in that, the step of thinning the wafer to be detected by a first preset thickness to form a first wafer with a surface exposing the defect particles to be detected includes: selectively etching the wafer to be detected by using a first dry etching process to remove the wafer material of the wafer to be detected and retain the defect particles to be detected on the surface of the first wafer.
4. The method for fabricating a defect structure according to claim 3, characterized in that, the process gas of the first dry etching process includes chlorine, hydrogen bromide, oxygen and helium-oxygen mixture.
5. The method for fabricating a defect structure according to claim 4, characterized in that, in the process gas of the first dry etching process, the flow rate of chlorine is greater than or equal to 10 sccm and less than or equal to 40 sccm, the flow rate of hydrogen bromide is greater than or equal to 100 sccm and less than or equal to 300 sccm, the flow rate of oxygen is greater than or equal to 20 sccm and less than or equal to 100 sccm, and the flow rate of the helium-oxygen mixture is greater than 0 sccm and less than or equal to 20 sccm.
6. The method for fabricating a defect structure according to claim 4, characterized in that, the chamber pressure of the first dry etching process is greater than or equal to 10 mTorr and less than or equal to 80 mTorr; the source RF power of the first dry etching process is greater than or equal to 100 watts and less than or equal to 1000 watts; the bias RF power of the first dry etching process is greater than or equal to -150 watts and less than or equal to 400 watts; the process time of the first dry etching process is greater than or equal to 95 s and less than or equal to 1160 s.
7. The method for fabricating a defect structure according to any one of claims 1-6, characterized in that, the step of forming an auxiliary layer on the surface of the first wafer includes: forming an auxiliary material layer on the first wafer, the auxiliary material layer covering the surface of the first wafer and the surface of the defect particles to be detected; etching the auxiliary material layer by using a second dry etching process to form the auxiliary layer.
8. The method for fabricating a defect structure according to claim 7, characterized in that, the material of the auxiliary material layer includes at least one of silicon dioxide and silicon nitride.
9. A method for detecting wafer defects, characterized in that, Detect the defective structure manufactured by the manufacturing method of the defective structure described in any one of claims 1-7, and obtain the quantity and size of the defective structure.
10. The method for detecting wafer defects according to claim 9, wherein, a defect scanner is used to scan and detect the defective structure; the distance between the surface of the auxiliary layer close to the defective particle to be detected and the surface of the auxiliary layer far from the defective particle to be detected, the minimum scanning size of the defect scanner, and the outer diameter of the defective particle to be detected satisfy the following relational expression: 2H + D ≥ L; wherein, H is the distance between the surface of the auxiliary layer close to the defective particle to be detected and the surface of the auxiliary layer far from the defective particle to be detected, D is the outer diameter of the defective particle to be detected, and L is the minimum scanning size of the defect scanner.