A switching chip, circuit system and electronic device

Abstract

This invention provides a switching chip, circuit system, and electronic device. The chip includes a gate pin, a source pin, and a drain pin, and also integrates a boost module, a reverse-current protection module, a switching NMOS transistor, and a pull-down module. By multiplexing the ground terminal of the boost module as its own input control terminal, this invention allows the switching chip to be compatible with existing PMOS high-side switching chips without the need for an additional ground pin, thereby reducing the application cost of the switching chip. Furthermore, because the conduction of the switching NMOS transistor by the boost module is independent of the parameters of the internal circuitry of the boost module, the circuit debugging costs for different application scenarios are eliminated, further reducing the application cost of the switching chip. In addition, the first pull-down NMOS transistor in the pull-down module is connected between the gate and source of the switching NMOS transistor, and the switching on and off of the first pull-down NMOS transistor is controlled by a switch control signal, so that the first pull-down NMOS transistor is turned on when the switch control signal is high, thereby quickly turning off the switching NMOS transistor.

Description

Technical Field

[0001] This invention relates to the field of circuit switches, and more particularly to a switch chip, circuit system, and electronic device. Background Technology

[0002] Using MOSFETs as switches has become a common practice in the industry. Specific applications can be broadly categorized into high-side switching and low-side switching. High-side switches are coupled between the power supply and the load, while low-side switches are coupled between the load and ground.

[0003] Although current technologies typically choose PMOS transistors as high-side switches, under the premise of the same voltage rating and impedance, the size of PMOS transistors is 2-3.5 times larger than that of NMOS transistors. Therefore, using NMOS transistors as high-side switches can significantly reduce circuit costs compared to using PMOS transistors.

[0004] However, existing switching chips that use NMOS transistors as high-side switches have high application costs because they require device debugging for boost circuits in different application scenarios and have low pin compatibility.

[0005] Therefore, providing a switching chip that can reduce both circuit and application costs has become a pressing technical problem for the industry. Summary of the Invention

[0006] This invention provides a switching chip, a circuit system, and an electronic device, which can reduce both the circuit cost and the application cost of the switching chip.

[0007] To solve the above-mentioned technical problems, the present invention provides a switching chip, comprising:

[0008] The device has a gate pin, a source pin, and a drain pin. The gate pin is connected to a switch control signal, the source pin is connected to the power supply voltage, and the drain pin is connected to the load.

[0009] A boost module, with its ground terminal connected to the gate pin and its power supply terminal connected to the source pin, is used to boost the difference between the power supply voltage and the switch control signal and output the corresponding boost voltage.

[0010] The anti-backflow module has its input terminal connected to the output terminal of the boost module. The anti-backflow module is used to: completely disconnect the connection between its own input terminal and output terminal when the switch control signal is high level; and establish the connection between its own input terminal and output terminal when the switch control signal is low level.

[0011] A switching NMOS transistor, with its drain connected to the source pin, its gate connected to the output terminal of the anti-reverse-current module, and its source connected to the drain pin;

[0012] A pull-down module includes a first pull-down NMOS transistor, a first pull-down resistor, a pull-down diode, and a second pull-down NMOS transistor. The drain of the first pull-down NMOS transistor is connected to the output terminal of the anti-reverse-current module, the source of the first pull-down NMOS transistor is connected to the source of the switching NMOS transistor, the gate of the first pull-down NMOS transistor is connected to the drain of the second pull-down NMOS transistor, and the substrate of the first pull-down NMOS transistor is connected to the terminal with the lower voltage between its source and its drain. The first terminal of the first pull-down resistor is connected to the gate of the switching NMOS transistor, and the second terminal of the first pull-down resistor is connected to the anode of the pull-down diode. The cathode of the pull-down diode is connected to the gate of the first pull-down NMOS transistor. The gate of the second pull-down NMOS transistor is connected to the source pin, the source of the second pull-down NMOS transistor is connected to the gate pin, the drain of the second pull-down NMOS transistor is connected to the gate of the first pull-down NMOS transistor, and the substrate of the second pull-down NMOS transistor is connected to its own source.

[0013] The boost module, the anti-backflow module, the switching NMOS transistor, and the pull-down module are all integrated into the same chip.

[0014] Optionally, the pull-down module further includes: a second pull-down resistor, a third pull-down NMOS transistor, and a third pull-down resistor;

[0015] The first end of the second pull-down resistor is connected to the output end of the anti-backflow module, and the second end of the second pull-down resistor is connected to the first end of the first pull-down resistor;

[0016] The gate of the third pull-down NMOS transistor is connected to the second terminal of the second pull-down resistor, the drain of the third pull-down NMOS transistor is connected to the first terminal of the second pull-down resistor, the source of the third pull-down NMOS transistor is connected to the source of the first pull-down NMOS transistor, and the substrate of the third pull-down NMOS transistor is connected to its own source.

[0017] The first end of the third pull-down resistor is connected to the gate of the switching NMOS transistor, and the second end of the third pull-down resistor is connected to the source of the switching NMOS transistor.

[0018] Optionally, the first pull-down resistor, the second pull-down resistor, and the third pull-down resistor are all greater than or equal to a first threshold value, which is used to characterize the minimum resistance value required to maintain normal operation of the switching NMOS transistor.

[0019] Optionally, the boost module is a charge pump circuit.

[0020] Optionally, the charge pump is specifically a second-order voltage-doubling charge pump.

[0021] Optionally, the anti-reverse current module includes a first PMOS transistor, whose gate is connected to the source pin, whose source serves as the input terminal of the anti-reverse current module, and whose drain serves as the output terminal of the anti-reverse current module. The substrate of the first PMOS transistor is connected to its own source.

[0022] Optionally, the anti-reverse current module includes a second PMOS transistor, whose gate is connected to the source pin, whose source serves as the input terminal of the anti-reverse current module, whose drain serves as the output terminal of the anti-reverse current module, and whose substrate is connected to the terminal with the highest voltage between its own source and its own drain.

[0023] Optionally, the difference between the power supply voltage and the high level of the switch control signal is less than a second threshold, which is used to characterize the minimum operating voltage of the boost module.

[0024] The present invention also provides a circuit system including the aforementioned switch chip.

[0025] The present invention also provides an electronic device, including the aforementioned circuit system.

[0026] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0027] The switching chip provided by this invention reuses the ground terminal of the boost module as its input control terminal, enabling it to be compatible with existing PMOS high-side switching chips without requiring additional ground pins. This improves the chip's compatibility and reduces its application cost. Furthermore, since the boost module outputs a boost voltage based on the difference between the external power supply voltage and the external switch control signal, the conduction of the NMOS transistor is independent of the internal circuit parameters. Compared to existing high-side switching chips with integrated NMOS transistors, this invention eliminates the need to redesign the boost module for different application scenarios, further reducing application cost. Finally, by configuring the first pull-down NMOS transistor, the first pull-down resistor, the pull-down diode, and the second pull-down NMOS transistor, the first pull-down NMOS transistor is quickly turned on when the switch control signal is high, accelerating the turn-off of the NMOS transistor. This allows the switching chip to be suitable for high-frequency or low-duty-cycle applications.

[0028] Meanwhile, the anti-backflow module and the pull-down module ensure that the switching NMOS transistor is completely turned off when the switch control signal is high, thus ensuring rapid turn-off while achieving zero standby power consumption during the turn-off of the switching NMOS transistor.

[0029] Furthermore, by setting the second pull-down resistor and the third pull-down NMOS transistor, it is ensured that the first pull-down NMOS transistor is not broken down when the switching NMOS transistor is turned on. Attached Figure Description

[0030] Figure 1 A schematic diagram of the circuit structure of the switching chip provided in an embodiment of the present invention. Figure 1 ;

[0031] Figure 2 A schematic diagram of the circuit structure of the switching chip provided in an embodiment of the present invention. Figure 2 ;

[0032] Figure 3 A schematic diagram of the circuit structure of the switching chip provided in an embodiment of the present invention. Figure 3 . Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The terms "gate," "source," "drain," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0034] Although using a PMOS transistor as a high-side switch eliminates the need for an additional boost circuit, its size is 2-3.5 times larger than that of an NMOS transistor for the same voltage rating and impedance. Therefore, to reduce circuit cost, those skilled in the art often prefer NMOS transistors as high-side switches, even when additional boost circuitry is required, increasing circuit complexity.

[0035] However, using NMOS transistors as high-side switches still presents the following problems:

[0036] 1. When it is necessary to replace the high-side switch of a PMOS transistor with a high-side switch of an NMOS transistor, the high-side switch of the NMOS transistor requires an additional boost circuit, and this boost circuit requires a ground terminal. Therefore, when using the high-side switch of the NMOS transistor to replace the high-side switch of the PMOS transistor, it is necessary to add a boost circuit and an additional ground pin on the basis of the original high-side switch. This results in the incompatibility of the pin architecture between the high-side switch of the NMOS transistor and the high-side switch of the PMOS transistor, thereby increasing the application cost of replacing the high-side switch of the NMOS transistor.

[0037] 2. In different application scenarios, the parameters of the internal components of the boost circuit need to be adjusted for the high-side switch of the existing NMOS transistor to ensure that the output voltage of the boost circuit can fully turn on the NMOS transistor, which further increases the application cost of the high-side switch of the NMOS transistor in different application scenarios.

[0038] In view of this, embodiments of the present invention provide a new switching chip to greatly reduce the application cost of the switching chip as a high-side switch in different application scenarios.

[0039] in, Figure 1 A schematic diagram of the circuit structure of the switching chip provided in an embodiment of the present invention. Figure 1 .

[0040] Please refer to Figure 1 The switching chip provided in this embodiment of the invention includes:

[0041] The circuit consists of a gate pin G, a source pin S, and a drain pin D. The gate pin G is connected to the switch control signal V1, the source pin S is connected to the power supply voltage VDD, and the drain pin D is connected to the load.

[0042] The boost module 10 has its ground terminal AGND connected to the gate pin G and its power supply terminal AVDD connected to the source pin S. The boost module 10 is used to boost the difference between the power supply voltage VDD and the switch control signal V1 and output the corresponding boost voltage VGC.

[0043] The anti-backflow module 20 has its input terminal connected to the output terminal of the boost module 10. The anti-backflow module 20 is used to: completely disconnect the connection between its own input terminal and output terminal when the switch control signal V1 is high; and establish the connection between its own input terminal and output terminal when the switch control signal V1 is low.

[0044] The NMOS transistor MN1 is a switch, with its drain connected to the source pin S, its gate connected to the output terminal of the anti-reverse-current module 20, and its source connected to the drain pin D.

[0045] The pull-down module 30 includes a first pull-down NMOS transistor MN2, a first pull-down resistor R1, a pull-down diode D1, and a second pull-down NMOS transistor MN3. The drain of the first pull-down NMOS transistor MN2 is connected to the output terminal of the anti-reverse-current module 20, the source of the first pull-down NMOS transistor MN2 is connected to the source of the switching NMOS transistor MN1, the gate of the first pull-down NMOS transistor MN2 is connected to the drain of the second pull-down NMOS transistor, and the substrate of the first pull-down NMOS transistor MN2 is connected to the terminal with the lower voltage between its source and drain. The first pull-down resistor R1, the first pull-down diode D1, the first pull-down resistor R1, the first pull-down diode D1, and the second pull-down NMOS transistor MN3 are connected to the output terminal of the anti-reverse-current module 20. The first end of the first pull-down resistor R1 is connected to the gate of the switching NMOS transistor MN1, and the second end of the first pull-down resistor R1 is connected to the positive terminal of the pull-down diode D1; the negative terminal of the pull-down diode D1 is connected to the gate of the first pull-down NMOS transistor MN2; the gate of the second pull-down NMOS transistor MN3 is connected to the source pin, the source of the second pull-down NMOS transistor MN3 is connected to the gate pin, the drain of the second pull-down NMOS transistor MN3 is connected to the gate of the first pull-down NMOS transistor MN2, and the substrate of the second pull-down NMOS transistor MN3 is connected to its own source.

[0046] The boost module 10, the anti-backflow module 20, the switching NMOS transistor MN1, and the pull-down module 30 are all integrated into the same chip.

[0047] To ensure the pin architecture of the switching chip in this embodiment is compatible with existing PMOS high-side switches, this invention reuses the ground terminal AGND of the internal boost module 10 as the input control terminal of the boost module 10 and connects this ground terminal AGND to the gate pin G of the switching chip. This avoids the need to additionally set a ground terminal AGND pin for the boost module 10 on the switching chip. Since the gate pin G is connected to the switch control signal V1, the gate pin G of the switching chip of this invention is equivalent to the gate pin G of an existing PMOS high-side switch. Because the source pin S and drain pin D of the switching chip of this invention are connected to the power supply voltage VDD and the load, respectively, the source pin S and drain pin D of the switching chip of this invention are equivalent to the source pin S and drain pin D of an existing PMOS high-side switch, respectively. As can be seen from the above, this invention, by integrating an NMOS transistor and without additionally setting a ground terminal AGND pin, achieves pin architecture compatibility with existing PMOS high-side switches, thereby reducing the application cost of the switching chip.

[0048] Furthermore, the boost module 10 of the switching chip outputs a boost voltage VGC based on the difference between the externally input power supply voltage VDD and the externally input switch control signal V1. Therefore, the conduction of the NMOS transistor MN1 by the boost module 10 is independent of the device parameters of the internal circuit of the boost module 10. Compared with the high-side switch of the existing integrated NMOS transistor, the switching chip of the present invention does not need to readjust the device parameters of the internal circuit of the boost module 10 in different application scenarios, thereby further reducing the application cost of the switching chip.

[0049] Secondly, when the switch control signal V1 transitions from low to high, the anti-backflow module 20 completely disconnects its input and output terminals. The gate of the switching NMOS transistor MN1 remains at its original boost voltage VGC and is in a floating state. For example, if the power supply voltage VDD is 5V and the boost module 10 is specifically a second-order voltage doubler charge pump, then when the switch control signal V1 is low, the boost module 10 will output a boost voltage VGC of 8V-10V. This 8V-10V boost voltage VGC will remain at the gate VG of the switching NMOS transistor MN1 even when the anti-backflow module 20 completely disconnects its input and output terminals.

[0050] At this time, the second pull-down NMOS transistor MN3 will be turned off, leaving the gate of the first pull-down NMOS transistor MN2 in a floating state. Therefore, the boost voltage VG can be quickly applied to the gate of the first pull-down NMOS transistor MN2 through the path formed by the first pull-down resistor R1 and the pull-down diode D1. Since the source voltage of both the first pull-down NMOS transistor MN2 and the source voltage of the switching NMOS transistor MN1 are maintained at the power supply voltage VDD, the first pull-down NMOS transistor MN2 will be quickly turned on by the boost voltage VG, rapidly pulling the gate of the switching NMOS transistor MN1 down to the source of the switching NMOS transistor MN1, thereby achieving rapid turn-off of the switching NMOS transistor MN1.

[0051] For example, if the boost voltage VG is 9V and the power supply voltage VDD is 5V, then after subtracting the turn-on voltage of the pull-down diode D1, approximately 8.3V will be applied to the gate of the first pull-down NMOS transistor MN2. A gate-source voltage of 3.3V is sufficient to turn on the first pull-down NMOS transistor MN2, causing the gate of the switching NMOS transistor MN1 to be quickly pulled down to the source of the switching NMOS transistor MN1, thereby achieving rapid turn-off of the switching NMOS transistor MN1.

[0052] When the switch control signal V1 is high, in addition to the first pull-down NMOS transistor MN2 being quickly turned on, the second pull-down NMOS transistor MN3 will also be turned off because its gate-source voltage is close to 0V. However, the high level of the switch control signal V1 will be transmitted to the gate of the first pull-down NMOS transistor MN2 through the body diode of the second pull-down NMOS transistor MN3. Since the boost voltage VG at the gate of the switch NMOS transistor MN1 will act on the gate of the first pull-down NMOS transistor MN2, the switch NMOS transistor MN1 will be turned off due to the conduction of the first pull-down NMOS transistor MN2, thereby pulling down the gate voltage of the switch NMOS transistor MN1 to the source voltage, turning off the switch NMOS transistor MN2, and finally pulling down both the gate voltage and the source voltage of the switch NMOS transistor MN1 to 0V.

[0053] Originally, the first pull-down NMOS transistor MN2 would also be turned off because its gate-source voltage is 0V. However, at this time, the high level of the switch control signal V1 will be transmitted to the gate of the first pull-down NMOS transistor MN2 through the body diode of the second pull-down NMOS transistor MN3, which will keep the first pull-down NMOS transistor MN2 on, thereby ensuring that the switch NMOS transistor MN1 remains off when the switch control signal V1 is high.

[0054] When the switch control signal V1 is low, the second pull-down NMOS transistor MN3 will be turned on to transmit the low-level switch control signal V1 to the gate of the first pull-down NMOS transistor MN2, so that the first pull-down NMOS transistor MN2 is turned off, thereby ensuring that the normal conduction of the switch NMOS transistor MN1 is not affected.

[0055] It should be noted that although the boost voltage VG at the gate of the switching NMOS transistor MN1 is high when the switch control signal V1 is low, the first pull-down resistor limits the current flow from the gate of the switching NMOS transistor MN1 to the gate of the first pull-down NMOS transistor MN2. Furthermore, because the switch control signal V1 is transmitted to the gate of the first pull-down NMOS transistor MN2 through the second pull-down NMOS transistor, the gate of the first pull-down NMOS transistor MN2 is 0V and thus turned off.

[0056] Finally, through the anti-backflow module 20 and the first pull-down NMOS transistor MN2, it is ensured that the switching NMOS transistor MN1 is completely turned off when the switch control signal V1 is high, ensuring rapid turn-off while achieving zero standby power consumption during the turn-off of the switching NMOS transistor.

[0057] As a supplementary explanation, the function of the pull-down diode D1 is that when the switching NMOS transistor MN1 is turned off due to the high level of the switching control signal V1, the switching control signal V1 acting on the gate of the first pull-down NMOS transistor MN2 will not flow back to the gate of the switching NMOS transistor MN1 through the path of the first pull-down resistor R1.

[0058] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0059] in, Figure 2 A schematic diagram of the circuit structure of the switching chip provided in an embodiment of the present invention. Figure 2 .

[0060] Please refer to Figure 2 As a specific implementation, in order to prevent the drain of the first pull-down NMOS transistor MN2 from being broken down by the high voltage of the boost voltage VG, the pull-down module 30 further includes: a second pull-down resistor R2, a third pull-down NMOS transistor MN4 and a third pull-down resistor R3.

[0061] The first end of the second pull-down resistor R2 is connected to the output end of the anti-backflow module 20, and the second end of the second pull-down resistor R2 is connected to the first end of the first pull-down resistor R1.

[0062] The gate of the third pull-down NMOS transistor MN4 is connected to the second terminal of the second pull-down resistor R2, the drain of the third pull-down NMOS transistor MN4 is connected to the first terminal of the second pull-down resistor R2, the source of the third pull-down NMOS transistor MN4 is connected to the source of the first pull-down NMOS transistor MN2, and the substrate of the third pull-down NMOS transistor MN4 is connected to its own source.

[0063] The first end of the third pull-down resistor R3 is connected to the gate of the switching NMOS transistor MN1, and the second end of the third pull-down resistor R3 is connected to the source of the switching NMOS transistor MN1.

[0064] The specific working principle of this implementation method is as follows:

[0065] When the switch control signal V1 changes from low level to high level, the first pull-down NMOS transistor MN2 will be turned on. The principle of its turn-on is the same as described above and will not be repeated here.

[0066] After the first pull-down NMOS transistor MN2 is turned on, the source voltage of the switching NMOS transistor MN1 is transmitted to the source of the third pull-down NMOS transistor MN4 through the first pull-down NMOS transistor MN2. Since the source voltage of the switching NMOS transistor MN1 is equal to the power supply voltage VDD at this time, and the gate voltage of the switching NMOS transistor MN1 is still at the high boost voltage VG, the third pull-down NMOS transistor MN4 will be turned on. For example, if the power supply voltage VDD is 5V, the high boost voltage VG is 9V, and because the gate of the first pull-down NMOS transistor MN2 is in a floating state, the gate voltage of the third pull-down NMOS transistor MN4 is equal to 9V, and its source voltage is equal to 5V, thus the third pull-down NMOS transistor MN4 is turned on.

[0067] After the third pull-down NMOS transistor MN4 is turned on, the source voltage of the switching NMOS transistor MN1 will be transmitted to the gate of the switching NMOS transistor MN1 through the third pull-down NMOS transistor MN4 and the first pull-down NMOS transistor MN2. Since the gate of the switching NMOS transistor MN1 is also in a floating state at this time and has no driving capability, the gate voltage of the switching NMOS transistor MN1 is equal to its own source voltage, thus turning off the switching NMOS transistor MN1.

[0068] After the NMOS transistor MN1 is turned off, its source voltage is pulled down to ground AGND by the load, causing its gate voltage to be pulled down to 0V, thus turning off the third pull-down NMOS transistor MN4. At this time, the first pull-down NMOS transistor MN2 is turned on, and the principle of its turn-on has been described above and will not be repeated here. Furthermore, the substrate of the third pull-down NMOS transistor MN4 is connected to its own source, thus the gate and source of the NMOS transistor MN1 are connected through the body diodes of the turned-on first pull-down NMOS transistor MN2 and the third pull-down NMOS transistor MN4. Simultaneously, the third pull-down resistor R3 further ensures the connection between the gate and source of the NMOS transistor MN1, thereby ensuring that the NMOS transistor MN1 remains in the off state.

[0069] When the switch control signal V1 is low, the gate of the first pull-down NMOS transistor MN2 is 0V, and MN2 is turned off. At this time, the gate voltage of the third pull-down NMOS transistor MN4 is equal to the voltage division of the gate voltage of the switch NMOS transistor MN1 by the first pull-down resistor R1 and the second pull-down resistor R2. The source of the third pull-down NMOS transistor MN4 is in a floating state, so MN4 is turned on.

[0070] After the third pull-down NMOS transistor MN4 is turned on, its source voltage will be lower than its gate voltage. This ensures that the gate-drain voltage, gate-source voltage, and source-drain voltage of the first pull-down NMOS transistor MN2 will not exceed its own withstand voltage, thus ensuring that MN2 will not be damaged without using a high-voltage NMOS transistor. Similarly, the gate-drain voltage, gate-source voltage, and source-drain voltage of the third pull-down NMOS transistor MN4 will also not exceed its own withstand voltage, thus ensuring that MN2 will not be damaged without using a high-voltage NMOS transistor.

[0071] For example, both the first pull-down NMOS transistor MN2 and the third pull-down NMOS transistor MN4 are standard 5V low-voltage NMOS transistors. When the switch control signal V1 is low, the power supply voltage VDD is 5V, the gate voltage of the switching NMOS transistor MN1 is 9V, and the resistance of the first pull-down resistor R1 is equal to the resistance of the second pull-down resistor R2. Therefore, the gate voltage of the third pull-down NMOS transistor MN4 is approximately 4.5V, and the source voltage of the third pull-down NMOS transistor MN4 is clamped at around 3.5V due to the NMOS transistor's turn-on threshold. Therefore, the gate-source voltage, source-drain voltage, and gate-drain voltage of the third pull-down NMOS transistor MN4 all do not exceed 5V. At this time, the gate voltage of the first pull-down NMOS transistor MN2 is 0V, its source voltage is equal to the source voltage of the third pull-down NMOS transistor MN4 and equals 3.5V, and its drain voltage is equal to the source voltage of the switching NMOS transistor MN1 and equals 5V. Therefore, the gate-source voltage, source-drain voltage and gate-drain voltage of the first pull-down NMOS transistor MN2 do not exceed 5V.

[0072] It should be noted that, in order to ensure that the first pull-down resistor R1, the second pull-down resistor R2 and the third pull-down resistor R3 do not affect the normal switching of the NMOS transistor MN1, the resistance values ​​of the first pull-down resistor R1, the second pull-down resistor R2 and the third pull-down resistor R3 should all be set above the first threshold value.

[0073] The first threshold is used to characterize the minimum resistance required to maintain normal operation of the NMOS switching transistor. For example, if the boost module can provide a drive current of 1mA, the first threshold is calculated using the following formula:

[0074] Rth = VG / Ith; Formula (1) where Rth is used to characterize the first threshold; VG is used to characterize the gate voltage of the switching NMOS transistor; and Ith is used to characterize the maximum value of the current allowed to be shunted in the resistor branch when driving the switching NMOS transistor.

[0075] When the gate-source voltage of the switching NMOS transistor is equal to 10V and Ith is equal to 10μA, the first threshold is set to 1MΩ. Of course, the specific value of the first threshold depends on the driving capability of the boost module and the capacitance of the switching NMOS transistor, and is not limited here.

[0076] Of course, in addition to setting the second pull-down resistor R2, the third pull-down NMOS transistor MN4, and the third pull-down resistor R3, the same effect can also be achieved by setting the first pull-down NMOS transistor MN2 to a high-voltage MOS transistor, which is not limited here.

[0077] in, Figure 3 A schematic diagram of the circuit structure of the switching chip provided in an embodiment of the present invention. Figure 3 .

[0078] Please refer to Figure 3 In one specific implementation, the anti-reverse current module includes a first PMOS transistor, whose gate is connected to the source pin, whose source serves as the input terminal of the anti-reverse current module, and whose drain serves as the output terminal of the anti-reverse current module. The substrate of the first PMOS transistor is connected to its own source.

[0079] The following explanation uses the example of a power supply voltage VDD of 5V, a boost module that is a second-order voltage multiplier charge pump, and a switch control signal V1 with high and low levels of 5V and 0V respectively, to illustrate the working principle of the anti-backflow module 20 and the pull-down module 30:

[0080] When the switch control signal V1 is low, the voltage difference between the power supply terminal AVDD and the ground terminal AGND of the boost module is 5V. The boost module boosts this voltage difference and outputs a 10V boost voltage VGC to the source of the first PMOS transistor MP1. Since the gate of the first PMOS transistor MP1 is connected to the 5V power supply voltage VDD, the source-gate voltage difference of the first PMOS transistor MP1 is 5V, which is greater than the threshold voltage of the first PMOS transistor MP1, thus turning on the first PMOS transistor MP1. Because the drain of the first PMOS transistor MP1 is connected to the gate of the switching NMOS transistor MN1, the boost voltage VG acts on the gate of the switching NMOS transistor MN1 to turn on the switching NMOS transistor MN1.

[0081] When the switch control signal V1 is high, the voltage difference between the power supply terminal AVDD and the ground terminal AGND of the boost module is 0V. This voltage difference is less than the normal operating voltage of the boost module, so the boost module outputs a boost voltage VGC of approximately 5V to the source of the first PMOS transistor MP1. The gate of the first PMOS transistor MP1 is connected to a 5V power supply voltage VDD, so the source-gate voltage difference of the first PMOS transistor MP1 is approximately 0V, which is less than the threshold voltage of the first PMOS transistor MP1, thus turning off the first PMOS transistor MP1. Because the anode of the body diode of the first PMOS transistor MP1 is connected to its drain, and the cathode of the body diode is connected to its source, when the first PMOS transistor MP1 is turned off, the boost voltage VGC will not be transmitted from its source to its drain through the body diode of the first PMOS transistor MP1, preventing the boost voltage VGC from acting on the gate VG of the switching NMOS transistor MN1, thereby completely isolating the output of the boost module from the gate of the switching NMOS transistor MN1.

[0082] Of course, in addition to the first PMOS transistor M2 mentioned above, other PMOS transistor switching circuits with anti-reverse current function in the anti-reverse current module 20 are also within the protection scope of this invention and are not limited here.

[0083] In one specific implementation, the switch control signal V1 is a periodic PWM pulse signal. Furthermore, the difference between the high level of the PWM pulse signal and the power supply voltage VDD must be less than a second threshold. This second threshold characterizes the minimum operating voltage of the boost module.

[0084] As described above, when the PWM pulse signal is high, the boost module outputs a boost voltage VGC that is approximately equal to the power supply voltage VDD, indicating that the boost module is not working. Furthermore, the boost module only functions normally when the voltage difference between its power supply terminal AVDD and ground terminal AGND is greater than a second threshold. Therefore, by setting the difference between the high level of the PWM pulse signal and the power supply voltage VDD to be less than the second threshold, it is ensured that the boost module is not working when the PWM pulse signal is high, thereby ensuring that the anti-reverse current module 20 functions, allowing the pull-down module 30 to turn off the switching NMOS transistor MN1.

[0085] In summary, the switching chip provided by this invention reuses the ground terminal of the boost module as its input control terminal, enabling it to be compatible with existing PMOS high-side switching chips without requiring additional ground pins. This improves the chip's compatibility and reduces its application cost. Furthermore, since the boost module outputs a boost voltage based on the difference between the external power supply voltage and the external switch control signal, the conduction of the NMOS transistor is independent of the parameters of the internal circuitry. Compared to existing high-side switching chips with integrated NMOS transistors, this invention eliminates the need to redesign the boost module for different application scenarios, further reducing application cost. Finally, by configuring the first pull-down NMOS transistor, the first pull-down resistor, the pull-down diode, and the second pull-down NMOS transistor, the first pull-down NMOS transistor is quickly turned on when the switch control signal is high, accelerating the turn-off of the NMOS transistor. This allows the switching chip to be suitable for high-frequency or low-duty-cycle scenarios.

[0086] Meanwhile, the anti-backflow module and the pull-down module ensure that the switching NMOS transistor is completely turned off when the switch control signal is high, thus ensuring rapid turn-off while achieving zero standby power consumption during the turn-off of the switching NMOS transistor.

[0087] Furthermore, by setting the second pull-down resistor and the third pull-down NMOS transistor, it is ensured that the first pull-down NMOS transistor is not broken down when the switching NMOS transistor is turned on.

[0088] This invention also provides a circuit system including the switching chip provided in this invention.

[0089] This invention also provides an electronic device, including the circuit system provided in this invention.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A switching chip, characterized in that, include: The device includes a gate pin, a source pin, and a drain pin. The gate pin is connected to a switch control signal, the source pin is connected to a power supply voltage, and the drain pin is connected to a load. A boost module, with its ground terminal connected to the gate pin and its power supply terminal connected to the source pin, is used to boost the difference between the power supply voltage and the switch control signal and output the corresponding boost voltage. The anti-backflow module has its input terminal connected to the output terminal of the boost module. The anti-backflow module is used to: completely disconnect the connection between its own input terminal and output terminal when the switch control signal is high level; and establish the connection between its own input terminal and output terminal when the switch control signal is low level. A switching NMOS transistor, with its drain connected to the source pin, its gate connected to the output terminal of the anti-reverse-current module, and its source connected to the drain pin; A pull-down module includes a first pull-down NMOS transistor, a first pull-down resistor, a pull-down diode, and a second pull-down NMOS transistor. The drain of the first pull-down NMOS transistor is connected to the output terminal of the anti-reverse-current module, the source of the first pull-down NMOS transistor is connected to the source of the switching NMOS transistor, the gate of the first pull-down NMOS transistor is connected to the drain of the second pull-down NMOS transistor, and the substrate of the first pull-down NMOS transistor is connected to the terminal with the lower voltage between its source and its drain. The first terminal of the first pull-down resistor is connected to the gate of the switching NMOS transistor, and the second terminal of the first pull-down resistor is connected to the anode of the pull-down diode. The cathode of the pull-down diode is connected to the gate of the first pull-down NMOS transistor. The gate of the second pull-down NMOS transistor is connected to the source pin, the source of the second pull-down NMOS transistor is connected to the gate pin, the drain of the second pull-down NMOS transistor is connected to the gate of the first pull-down NMOS transistor, and the substrate of the second pull-down NMOS transistor is connected to its own source. The boost module, the anti-backflow module, the switching NMOS transistor, and the pull-down module are all integrated into the same chip.

2. The switching chip according to claim 1, characterized in that, The pull-down module further includes: a second pull-down resistor, a third pull-down NMOS transistor, and a third pull-down resistor; The first end of the second pull-down resistor is connected to the output end of the anti-backflow module, and the second end of the second pull-down resistor is connected to the first end of the first pull-down resistor; The gate of the third pull-down NMOS transistor is connected to the second terminal of the second pull-down resistor, the drain of the third pull-down NMOS transistor is connected to the first terminal of the second pull-down resistor, the source of the third pull-down NMOS transistor is connected to the source of the first pull-down NMOS transistor, and the substrate of the third pull-down NMOS transistor is connected to its own source. The first end of the third pull-down resistor is connected to the gate of the switching NMOS transistor, and the second end of the third pull-down resistor is connected to the source of the switching NMOS transistor.

3. The switching chip according to claim 2, characterized in that, The first pull-down resistor, the second pull-down resistor, and the third pull-down resistor are all greater than or equal to a first threshold value, which is used to characterize the minimum resistance value for maintaining normal drive of the switching NMOS transistor.

4. The switching chip according to claim 1, characterized in that, The boost module is a charge pump circuit.

5. The switching chip according to claim 4, characterized in that, The charge pump is specifically a second-order voltage-multiplying charge pump.

6. The switching chip according to claim 1, characterized in that, The anti-reverse current module includes a first PMOS transistor, whose gate is connected to the source pin, whose source serves as the input terminal of the anti-reverse current module, and whose drain serves as the output terminal of the anti-reverse current module. The substrate of the first PMOS transistor is connected to its own source.

7. The switching chip according to claim 1, characterized in that, The anti-reverse current module includes a second PMOS transistor, whose gate is connected to the source pin, whose source serves as the input terminal of the anti-reverse current module, whose drain serves as the output terminal of the anti-reverse current module, and whose substrate is connected to the terminal with the highest voltage between its own source and its own drain.

8. The switching chip according to claim 1, characterized in that, The difference between the power supply voltage and the high level of the switch control signal is less than a second threshold, which is used to characterize the minimum operating voltage of the boost module.

9. A circuit system, characterized in that, Includes the switch chip according to any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the circuit system described in claim 9.

Images