Semiconductor device

Abstract

The semiconductor device includes a lower wiring structure extending within the lower interlayer insulating film; the lower wiring structure includes a lower barrier film and a lower filling film. There is provided an upper interlayer insulating film extending over the lower interlayer insulating film; the upper interlayer insulating film has an upper wiring trench therein. An upper wiring structure extending within the upper wiring trench and electrically connected to the lower wiring structure is provided; the upper wiring structure includes an upper barrier film, an upper filling film, and an upper capping film extending over the upper filling film. The upper fill film extends on and in contact with the upper barrier film, the upper barrier film includes a sidewall portion extending along a sidewall of the upper wiring trench, and the sidewall portion of the upper barrier film includes tantalum nitride doped with manganese (Mn).

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit device, and more particularly, to an integrated circuit device having a wiring structure formed during a back-end-of-line (BEOL) process therein. Background Art

[0002] Due to the development of electronic technology, the size reduction of integrated circuit devices has been rapidly progressing, and thus higher integration and lower power consumption within an integrated circuit chip are required. To meet the demands for higher integration and lower power consumption, the feature size of semiconductor devices within an integrated circuit continues to decrease; as the feature size of semiconductor devices decreases, various studies are being conducted on a stable electrical connection scheme between wirings within an integrated circuit. Summary of the Invention

[0003] An object of the present disclosure is to provide an integrated circuit device having improved element performance, reliability, and connectivity with semiconductor devices therein.

[0004] The object according to the present disclosure is not limited to the above-mentioned object. Other objects and advantages not mentioned according to the present disclosure can be understood based on the following description, and can be more clearly understood based on embodiments according to the present disclosure. In addition, it will be readily understood that the objects and advantages according to the present disclosure can be achieved using the devices shown in the claims or combinations thereof.

[0005] According to one aspect of the present disclosure, there is provided a semiconductor device having a lower wiring structure therein, the lower wiring structure being disposed within a lower interlayer insulating film and including a lower barrier film and a lower filling film. An upper interlayer insulating film is provided, the upper interlayer insulating film extending over the lower interlayer insulating film and including an upper wiring trench and an upper wiring structure extending within the upper wiring trench and electrically connected to the lower wiring structure. The upper wiring structure includes an upper barrier film, an upper filling film, and an upper capping film extending over the upper filling film. The upper filling film extends over the upper barrier film and is in electrical contact with the upper barrier film; the upper barrier film includes a sidewall portion extending along the sidewalls of the upper wiring trench, and the sidewall portion of the upper barrier film includes tantalum nitride doped with manganese (Mn).

[0006] According to one aspect of the present disclosure, there is provided a semiconductor device including a lower wiring structure extending within a lower interlayer insulating film and including a lower barrier film and a lower filling film. An upper interlayer insulating film is disposed over the lower interlayer insulating film and includes an upper wiring trench and an upper wiring structure extending within the upper wiring trench and electrically connected to the lower wiring structure. The upper wiring structure includes an upper barrier film, an upper filling film, and an upper liner between the upper barrier film and the upper filling film. The upper barrier film may include tantalum nitride, and the upper liner may extend along the sidewalls of the upper wiring trench without extending along the lower surface of the upper wiring trench. In some embodiments, the upper liner may include manganese (Mn).

[0007] According to another aspect of the present disclosure, a semiconductor device is provided, which includes a lower wiring structure extending in a lower interlayer insulating film and including a lower barrier film, a lower filling film, and a lower capping film. The lower filling film is in contact with the lower barrier film and the lower capping film. An upper interlayer insulating film extends on the lower interlayer insulating film and includes an upper wiring trench and an upper wiring structure extending in the upper wiring trench and electrically connected to the lower wiring structure. The upper wiring structure may include an upper barrier film, an upper filling film, and an upper capping film extending on the upper filling film. The upper filling film extends on the upper barrier film and is in contact with the upper barrier film and the upper capping film. The upper barrier film includes a sidewall portion and a bottom, the sidewall portion extends along the sidewall of the upper wiring trench, and the bottom extends along the lower surface of the upper wiring trench. Each of the sidewall portion of the upper barrier film and the lower barrier film includes tantalum nitride doped with manganese (Mn). In addition, the bottom of the upper barrier film may include manganese. According to another embodiment, each of the upper capping film and the lower capping film includes cobalt (Co), wherein each of the upper filling film and the lower filling film includes copper (Cu).

[0008] Specific details of other embodiments are included in the detailed description and the drawings. However, aspects of the present disclosure are not limited to those set forth herein. By referring to the following detailed description of the present disclosure, the above and other aspects of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains. Description of the Drawings

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing in detail some embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figure 1 is an exemplary layout diagram for showing a semiconductor device according to some embodiments.

[0011] Figure 2 is along Figure 1 in the line A-A of

[0012] Figure 3 is along Figure 1 in the line B-B of

[0013] Figure 4 is Figure 2 an enlarged view of the P portion of

[0014] Figure 5 is Figure 3 an enlarged view of the Q portion of

[0015] Figure 6 is for describing that it can be in Figure 4Table of metals detected in LINE1 and LINE2 in

[0016] Figure 7 and Figure 8 are diagrams for showing semiconductor devices according to some embodiments.

[0017] Figure 9 are diagrams for showing semiconductor devices according to some embodiments.

[0018] Figure 10 and Figure 11 are diagrams for showing semiconductor devices according to some embodiments.

[0019] Figure 12 and Figure 13 are diagrams for showing semiconductor devices according to some embodiments.

[0020] Figure 14 and Figure 15 are diagrams for showing semiconductor devices according to some embodiments.

[0021] Figures 16 to 19 are diagrams for showing semiconductor devices according to some embodiments.

[0022] Figure 20 and Figure 21 are diagrams for showing semiconductor devices according to some embodiments.

[0023] Figure 22 and Figure 23 are diagrams for showing semiconductor devices according to some embodiments.

[0024] Figure 24 and Figure 25 are diagrams for showing semiconductor devices according to some embodiments.

[0025] Figure 26 are diagrams for showing semiconductor devices according to some embodiments.

[0026] Figure 27 are diagrams for showing semiconductor devices according to some embodiments.

[0027] Figures 28 to 30 are diagrams for showing semiconductor devices according to some embodiments.

[0028] Figures 31 to 36 are diagrams for showing intermediate structures corresponding to intermediate steps of a method for manufacturing a semiconductor device according to some embodiments.

[0029] Figure 37 and Figure 38It is a diagram showing an intermediate structure corresponding to an intermediate step of a method for manufacturing a semiconductor device according to some embodiments. Detailed Description

[0030] With reference to the embodiments and the drawings described in detail later, the advantages and features of the present disclosure and the methods for achieving the advantages and features will become apparent. However, the embodiments of the present disclosure are not limited to the embodiments disclosed below, but can be implemented in various different forms. Therefore, these embodiments are described only to make the present disclosure complete and to fully inform those of ordinary skill in the art to which the present disclosure pertains of the scope of the present disclosure, and the present disclosure is defined only by the scope of the claims.

[0031] For simplicity and clarity of illustration, the elements in the drawings are not necessarily drawn to scale. The same reference numerals in different drawings represent the same or similar elements and perform similar functions. In addition, for simplicity of description, the description and details of well-known steps and elements are omitted. Further, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure. Examples of various embodiments are further illustrated and described below. It will be understood that the description herein is not intended to limit the claims to the specific embodiments described. Instead, the present invention is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the present disclosure as defined by the appended claims.

[0032] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings for illustrating the embodiments of the present disclosure are illustrative, and the embodiments of the present disclosure are not limited thereto.

[0033] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "an" are intended to also include the plural forms. It will also be understood that the terms "comprises" and "comprising," when used in this specification, specify the presence of the stated features, integers, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and / or portions thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When an expression such as "at least one of" is after a list of elements, it can modify the entire list of elements and may not modify a single element of the list. In the interpretation of numerical values, even when not explicitly described, errors or tolerances may occur therein.

[0034] It will also be understood that when a first element or layer is said to be "on" a second element or layer, the first element can be directly disposed on the second element, or can be indirectly disposed on the second element with a third element or layer disposed between the first element or layer and the second element or layer. It will also be understood that when a first element or layer is said to be "under" a second element or layer, the first element can be directly disposed under the second element, or can be indirectly disposed under the second element with a third element or layer disposed between the first element or layer and the second element or layer.

[0035] It will be understood that when an element or layer is said to be "connected to" or "coupled to" another element or layer, the element or layer can be directly connected to or coupled to the said another element or layer, or there can be one or more intermediate elements or layers therebetween. Further, it will be understood that when an element or layer is said to be "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there can also be one or more intermediate elements or layers therebetween.

[0036] In addition, as used herein, when a layer, film, region, plate, etc. is disposed "on" another layer, film, region, plate, etc. or "on top of" another layer, film, region, plate, etc., the former can directly contact the latter, or another layer, film, region, plate, etc. can be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is directly disposed "on" another layer, film, region, plate, etc. or "on top of" another layer, film, region, plate, etc., the former directly contacts the latter and no another layer, film, region, plate, etc. is disposed between the former and the latter. In addition, as used herein, when a layer, film, region, plate, etc. is disposed "under" or "beneath" another layer, film, region, plate, etc., the former can directly contact the latter, or another layer, film, region, plate, etc. can be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is directly disposed "under" or "beneath" another layer, film, region, plate, etc., the former directly contacts the latter and no another layer, film, region, plate, etc. is disposed between the former and the latter.

[0037] In the description of temporal relationships (e.g., the temporal precedence relationship between two events such as "after", "subsequent to", "before", etc.), unless it is indicated "directly after", "directly subsequent to", "directly before", another event may occur therebetween.

[0038] When a particular embodiment can be implemented differently, the functions or operations specified in a particular block can occur in an order different from the order specified in the flowchart. For example, two consecutive blocks can actually be executed substantially concurrently, or the two blocks can be executed in the reverse order depending on the functions or operations involved.

[0039] It will be understood that although the terms “first,” “second,” “third,” etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section described below may be referred to as a second element, component, region, layer, or section without departing from the spirit and scope of the present disclosure.

[0040] For ease of explanation, spatially relative terms such as “beneath,” “below,” “under,” “underneath,” “above,” “upper,” etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, when the device in the figures can be flipped, an element described as “beneath” or “below” or “underneath” another element or feature will then be oriented “above” the other element or feature. Thus, the example terms “below” and “underneath” can include both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0041] The features of the various embodiments of the present disclosure may be partially or fully combined with each other and may be technically related to each other or operate with each other. The embodiments may be implemented independently of each other and may be implemented together in an associated relationship. When interpreting a numerical value, unless there is a separate and explicit description, the value is interpreted to include the error range.

[0042] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will also be understood that terms such as those defined in a general dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0043] As used herein, “embodiment,” “example,” “aspect,” etc. should not be construed so as to make any aspect or design described as such superior to or better than other aspects or designs. Additionally, the term “or” means “inclusive or” rather than “exclusive or.” That is, unless otherwise stated or clear from the context, the statement “x uses a or b” means any of the natural inclusive arrangements.

[0044] The terms used in the following description are selected to be common and widespread in the relevant technical field. However, depending on the development and / or changes in technology, conventions, preferences of those skilled in the art, etc., there may be other terms besides these terms. Therefore, the terms used in the following description should not be construed as limiting the technical idea, but should be understood as examples of terms for illustrating embodiments.

[0045] In addition, in specific cases, the terms can be arbitrarily selected by the applicant, and in such cases, their detailed meanings will be described in the corresponding description part. Therefore, the terms used in the following description should not be understood only based on the name of the terms, but should be understood based on the meanings of the terms and the content throughout the specific implementation.

[0046] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0047] In the drawings of semiconductor devices according to some embodiments, fin field-effect transistors (FinFETs) including channel regions in the shape of fin patterns, transistors including nanowires or nanosheets, multi-bridge channel field-effect transistors (MBCFET TM ) or vertical transistors (vertical FETs) are shown by way of example. However, the embodiments of the present disclosure are not limited thereto. In another example, a semiconductor device according to some embodiments may include a tunnel transistor (tunnel FET) or a three-dimensional (3D) transistor. In yet another example, a semiconductor device according to some embodiments may include a planar transistor. In addition, the technical idea of the present disclosure can be applied to transistors based on 2D materials (2D material-based FETs) and their heterostructures. In addition, a semiconductor device according to some embodiments may include bipolar junction transistors, laterally diffused MOS (LDMOS), etc.

[0048] Figure 1 is an example layout diagram for showing a semiconductor device according to some embodiments. Figure 2 is along Figure 1 An illustrative cross-sectional view taken along line A-A in Figure 3 is along Figure 1 An illustrative cross-sectional view taken along line B-B in Figure 4 is Figure 2 An enlarged view of the P part of

[0049] Figure 5 is Figure 3 An enlarged view of the Q part of Figure 6 is for describing Figure 4 A table of metals that can be detected in LINE1 and LINE2 in

[0050] Referring to Figures 1 to 6, A semiconductor device according to some embodiments may include a lower wiring structure 110 and an upper wiring structure 210. The lower wiring structure 110 may be disposed within the first interlayer insulating film 150 and may extend in an elongated manner in a first direction D1. The lower wiring structure 110 may have a linear shape extending in the first direction D1. For example, the first direction D1 may be the length direction of the lower wiring structure 110, and the second direction D2 may be the width direction of the lower wiring structure 110. In this regard, the first direction D1 intersects the second direction D2 and the third direction D3. The second direction D2 intersects the third direction D3.

[0051] The first interlayer insulating film 150 may cover the gate electrodes and source / drain electrodes of transistors formed in a front-end-of-line (FEOL) process. Alternatively, the first interlayer insulating film 150 may be an interlayer insulating film formed in a back-end-of-line (BEOL) process. In other words, in one example, the lower wiring structure 110 may be a contact or contact wiring formed in a middle-of-line (MOL) process. In another example, the lower wiring structure 110 may be a connection wiring formed in a back-end-of-line (BEOL) process. In the following description, an example in which the lower wiring structure 110 is a connection wiring formed in a BEOL process is described.

[0052] For example, the first interlayer insulating film 150 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material. The low-k dielectric material may be, for example, silicon oxide having a moderately high content of carbon and hydrogen, such as SiCOH. When carbon is included in the insulating material, the dielectric constant of the insulating material may be reduced. However, in order to further reduce the dielectric constant of the insulating material, the insulating material may include pores, such as gas-filled or air-filled cavities.

[0053] The low-k dielectric material may include, for example, tetraethyl orthosilicate fluoride (FTEOS), hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditert-butylsilane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Toagosei silazane), FSG (fluoride silicate glass), polyimide nanofoam such as polypropylene oxide, CDO (carbon-doped silicon oxide), OSG (organic silicon glass), SiLK, amorphous fluorocarbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof. However, the spirit of the embodiments of the present disclosure is not limited thereto.

[0054] The lower wiring structure 110 may be disposed at a first metal level. The first interlayer insulating film 150 may include lower wiring trenches 110t extending in an elongated manner in a first direction D1. The lower wiring structure 110 may be disposed within the first interlayer insulating film 150. The lower wiring structure 110 may be disposed within the lower wiring trenches 110t. The lower wiring structure 110 fills the lower wiring trenches 110t.

[0055] The lower wiring structure 110 may include a lower barrier film 111, a lower liner 112, a lower filling film 113, and a lower capping film 114. The lower barrier film 111 may extend along sidewalls and a lower surface of the lower wiring trenches 110t. The lower liner 112 may be disposed on the lower barrier film 111. The lower liner 112 may extend along sidewalls and a lower surface of the lower wiring trenches 110t while being disposed on the lower barrier film 111. The lower filling film 113 is disposed on the lower liner 112. The lower filling film 113 may fill the remaining portion of the lower wiring trenches 110t. The lower capping film 114 may be disposed on an upper surface 113US of the lower filling film. The lower capping film 114 may extend along the upper surface 113US of the lower filling film. The lower capping film 114 may be disposed on an upper surface of the lower liner 112. Different from that shown, the lower capping film 114 does not need to cover the upper surface of the lower liner 112.

[0056] The lower capping film 114 may include an upper surface 114US and a lower surface 114BS opposite to each other in a third direction D3. The lower surface 114BS of the lower capping film faces the upper surface 113US of the lower filling film. The lower surface 114BS of the lower capping film may contact the upper surface 113US of the lower filling film.

[0057] The upper surface 113US of the lower filling film may include a first region 113US_R1 and a second region 113US_R2. The first region 113US_R1 of the upper surface of the lower filling film is a region covered by the lower capping film 114. The first region 113US_R1 of the upper surface of the lower filling film may contact the lower capping film 114.

[0058] The second region 113US_R2 of the upper surface of the lower filling film is a region not covered by the lower capping film 114. The second region 113US_R2 of the upper surface of the lower filling film may not contact the lower capping film 114.

[0059] In other words, the lower capping film 114 may include a capping opening 114_OP exposing a part of the upper surface 113US of the lower filling film. The second region 113US_R2 of the upper surface of the lower filling film may be exposed through the capping opening 114_OP.

[0060] When the lower liner 112 and the lower capping film 114 are made of the same material, the upper surface of the lower liner 112 may not be distinguishable at the interface between the lower liner 112 and the lower capping film 114. The lower capping film 114 may not cover the upper surface of the lower barrier film 111. Different from that shown, the lower capping film 114 may cover at least a part of the upper surface of the lower barrier film 111.

[0061] The upper surface of the lower liner 112 is shown to be coplanar with the upper surface 113US of the lower fill film and the upper surface of the lower barrier film 111. However, embodiments of the present disclosure are not limited thereto. In this regard, the upper surface of the lower liner 112 may represent the uppermost surface of the portion of the lower liner 112 that extends along the sidewall of the lower wiring trench 110t. The lower barrier film 111 may include a conductive material such as a metal nitride. The lower barrier film 111 may include at least one of, for example, tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), zirconium nitride (ZrN), vanadium nitride (VN), and niobium nitride (NbN). In one example, the lower barrier film 111 may include tantalum nitride (TaN). In another example, the lower barrier film 111 may include tantalum nitride doped with ruthenium (Ru). In a semiconductor device according to some embodiments, the lower barrier film 111 may not include manganese (Mn). The lower barrier film 111 may not include doped manganese (Mn).

[0062] The lower liner 112 may include a conductive material such as a metal. The lower liner 112 may include, for example, cobalt (Co) or ruthenium-doped cobalt.

[0063] In a semiconductor device according to some embodiments, the lower liner 112 may be made of cobalt (Co). For example, the lower liner 112 may be made of cobalt. In this regard, the "cobalt film" may be a film made only of cobalt or may be a film containing impurities introduced during the process of forming the cobalt film.

[0064] The lower fill film 113 may include a conductive material such as, for example, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), molybdenum (Mo), rhodium (Rh), iridium (Ir), RuAl, NiAl, NbB 2 , MoB 2 , TaB 2 , V 2 , AlC, and CrAlC. In a semiconductor device according to some embodiments, the lower fill film 113 may include copper (Cu).

[0065] The lower capping film 114 may include a conductive material such as a metal. The lower capping film 114 may include, for example, cobalt (Co). In a semiconductor device according to some embodiments, the lower capping film 114 may be made of cobalt (Co).

[0066] Different from what is shown, the lower wiring structure 110 may have a single-layer film structure. Although not shown, via patterns connecting conductive patterns disposed under the lower wiring structure 110 to each other may also be included in the semiconductor device. For example, a damascene method may be used to form the lower wiring structure 110. In Figure 2 it, the width of the lower wiring structure 110 in the second direction D2 is shown to be constant. However, embodiments of the present disclosure are not limited thereto. Different from what is shown, the width of the lower wiring structure 110 in the second direction D2 may decrease as the lower wiring structure 110 extends away from the upper surface 150US of the first interlayer insulating film.

[0067] The first etch stop film 155 may be disposed on the lower wiring structure 110 and the first interlayer insulating film 150. The first etch stop film 155 may contact the upper surface 150US of the first interlayer insulating film and the upper surface 114US of the lower capping film.

[0068] In a semiconductor device according to some embodiments, the lower capping film 114 may be partially undercut under the first etch stop film 155. In other words, the first etch stop film 155 may cover a part of the second region 113US_R2 of the upper surface of the lower filling film. The first etch stop film 155 may overlap with this part of the second region 113US_R2 of the upper surface of the lower filling film in the third direction D3.

[0069] For example, a capping air gap 114AG may be disposed in the region where the lower capping film 114 is undercut. The capping air gap 114AG may be disposed between the first etch stop film 155 and the lower filling film 113. Different from what is shown, in one example, at least a part of the region where the lower capping film 114 is undercut may be filled with an insulating material. In another example, the lower capping film 114 may not be undercut under the first etch stop film 155.

[0070] The second interlayer insulating film 160 may be disposed on the first etch stop film 155. The first etch stop film 155 may be disposed between the first interlayer insulating film 150 and the second interlayer insulating film 160. The second interlayer insulating film 160 may include upper wiring trenches 210t. The upper wiring trenches 210t may extend through the first etch stop film 155. The upper wiring trenches 210t expose a part of the lower wiring structure 110.

[0071] The upper wiring trench 210t may extend through the lower capping film 114. The upper wiring trench 210t may expose a portion of the upper surface 113US of the lower filling film. The upper wiring trench 210t may include an upper viaduct trench 210V_t and an upper wiring line trench 210L_t. The upper wiring line trench 210L_t may extend in an elongated manner in the second direction D2. The upper wiring line trench 210L_t may extend to the upper surface of the second interlayer insulating film 160. The upper viaduct trench 210V_t may be formed on the lower surface of the upper wiring line trench 210L_t.

[0072] For example, the lower surface of the upper wiring trench 210t may be the lower surface of the upper viaduct trench 210V_t. In a semiconductor device according to some embodiments, the lower surface of the upper wiring trench 210t may be defined by the upper surface 113US of the lower filling film. For example, the lower surface of the upper wiring trench 210t may be defined by at least a portion of the second region 113US_R2 of the upper surface of the lower filling film.

[0073] The sidewalls of the upper wiring trench 210t may include the sidewalls and the lower surface of the upper wiring line trench 210L_t and the sidewalls of the upper viaduct trench 210V_t. The sidewalls and the lower surface of the upper wiring line trench 210L_t may be defined by the second interlayer insulating film 160. The sidewalls of the upper viaduct trench 210V_t may be defined by the second interlayer insulating film 160 and the first etch stop film 155. The second interlayer insulating film 160 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0074] The first etch stop film 155 may include a material having an etch selectivity with respect to the material of the second interlayer insulating film 160. The first etch stop film 155 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxycarbide (AlOC), and combinations thereof. The first etch stop film 155 is shown as a single film. However, this is only for convenience of illustration, and the embodiments of the present disclosure are not limited thereto. In another example, different from that shown, the first etch stop film 155 may include a plurality of insulating films sequentially stacked on the first interlayer insulating film 150.

[0075] The upper wiring structure 210 may be disposed within the upper wiring trench 210t. The upper wiring structure 210 may fill the upper wiring trench 210t. The upper wiring structure 210 may be disposed within the second interlayer insulating film 160.

[0076] The upper wiring structure 210 is disposed on the lower wiring structure 110. The upper wiring structure 210 is connected to the lower wiring structure 110. The upper wiring structure 210 is in contact with the lower wiring structure 110. In a semiconductor device according to some embodiments, the upper wiring structure 210 may contact the lower fill film 113. For example, the upper wiring structure 210 may contact the second region 113US_R2 of the upper surface of the lower fill film.

[0077] The upper wiring structure 210 includes an upper wiring line 210L and an upper via 210V. The upper via 210V connects the upper wiring line 210L and the lower wiring structure 110 to each other. The upper via 210V may contact the lower fill film 113. The upper via 210V may contact the second region 113US_R2 of the upper surface of the lower fill film. The upper via 210V may extend through the cap opening 114_OP and contact the lower fill film 113.

[0078] When a portion of the lower cap film 114 is etched to expose the second region 113US_R2 of the upper surface of the lower fill film, the lower fill film 113 may not be removed by the etching process. The first region 113US_R1 of the upper surface of the lower fill film may be coplanar with the second region 113US_R2 of the upper surface of the lower fill film. In Figure 3 the cross-sectional view, the upper surface 113US of the lower fill film in contact with the upper wiring structure 210 may be flat.

[0079] Different from that shown, the upper surface 113US of the lower fill film in contact with the upper wiring structure 210 may have a concave curved shape. At least a portion of the second region 113US_R2 of the upper surface of the lower fill film may have a concave curved shape. The upper wiring structure 210 fills the upper via trench 210V_t and the upper wiring line trench 210L_t. The upper wiring line 210L is disposed in the upper wiring line trench 210L_t. The upper via 210V is disposed in the upper via trench 210V_t. The upper wiring line 210L is disposed at a second metal level different from the first metal level. The upper wiring line 210L is disposed at a second metal level higher than the first metal level. The upper wiring structure 210 may include an upper barrier film 211, an upper fill film 213, and an upper cap film 214.

[0080] The upper barrier film 211 may extend along the sidewalls and the lower surface of the upper wiring trench 210t. The upper barrier film 211 may extend along the sidewalls and the lower surface of the upper wiring line trench 210L_t and the sidewalls and the lower surface of the upper via trench 210V_t. The upper barrier film 211 may include a sidewall portion 211S and a bottom 211B. The sidewall portion 211S of the upper barrier film may extend along the sidewalls of the upper wiring trench 210t. The bottom 211B of the upper barrier film may extend along the lower surface of the upper wiring trench 210t.

[0081] The sidewall portion 211S of the upper barrier film can extend along the sidewalls and the lower surface of the upper wiring line trench 210L_t and the sidewalls of the upper vias trench 210V_t. The bottom 211B of the upper barrier film can extend along the lower surface of the upper vias trench 210V_t. For example, the bottom 211B of the upper barrier film can contact the upper surface 113US of the lower fill film that defines the lower surface of the upper vias trench 210V_t. The upper barrier film 211 may not cover the entire portion of the lower wiring structure 110 exposed through the upper vias trench 210V_t. In a cross-sectional view, the bottom 211B of the upper barrier film may not contact the entire second region 113US_R2 of the upper surface of the lower fill film. Different from that shown, in a cross-sectional view, the bottom 211B of the upper barrier film may cover the entire second region 113US_R2 of the upper surface of the lower fill film.

[0082] The thicknesses t21 and t22 of the sidewall portion 211S of the upper barrier film can be equal to the thickness t1 of the bottom 211B of the upper barrier film. The thickness t21 of the portion of the sidewall portion 211S of the upper barrier film located on the sidewall of the upper vias trench 210V_t can be equal to the thickness t1 of the portion of the sidewall portion 211S of the upper barrier film located on the lower surface of the upper vias trench 210V_t. The thickness t21 of the portion of the sidewall portion 211S of the upper barrier film located on the sidewall of the upper vias trench 210V_t can be equal to the thickness t22 of the portion of the sidewall portion 211S of the upper barrier film located on the lower surface of the upper wiring line trench 210L_t.

[0083] The upper barrier film 211 can include a conductive material such as a metal nitride. In a semiconductor device according to some embodiments, the upper barrier film 211 can include tantalum nitride (TaN) doped with manganese (Mn). For example, a portion of the upper barrier film 211 can include tantalum nitride (TaN) doped with manganese (Mn), and the remaining portion of the upper barrier film 211 can include tantalum nitride (TaN) without manganese (Mn) doping.

[0084] In Figures 4 to 6 it, the sidewall portion 211S of the upper barrier film can include manganese-doped tantalum nitride (TaN). The sidewall portion 211S of the upper barrier film can include tantalum nitride (TaN) and manganese (Mn)-doped tantalum nitride (TaN). The bottom 211B of the upper barrier film can include tantalum nitride (TaN). The bottom 211B of the upper barrier film may not include manganese (Mn). Manganese (Mn) may not be doped into the bottom 211B of the upper barrier film. The bottom 211B of the upper barrier film may not include manganese-doped tantalum nitride (TaN). The sidewall portion 211S of the upper barrier film may not include tantalum nitride without manganese doping.

[0085] In one example (in Figure 6In (1) among them, each of the side wall portion 211S and the bottom portion 211B of the upper barrier film may not contain doped ruthenium (Ru). For example, the side wall portion 211S of the upper barrier film may be made of tantalum nitride (TaN) doped with manganese. The bottom portion 211B of the upper barrier film may be made of tantalum nitride (TaN).

[0086] In another example (in Figure 6 In (2) among them), the side wall portion 211S of the upper barrier film may further include doped ruthenium (Ru). The side wall portion 211S of the upper barrier film may include tantalum nitride (TaN) doped with manganese (Mn) and ruthenium (Ru). For example, the side wall portion 211S of the upper barrier film may be made of tantalum nitride (TaN) doped with manganese (Mn) and ruthenium (Ru). The bottom portion 211B of the upper barrier film may not contain doped ruthenium (Ru). For example, the bottom portion 211B of the upper barrier film may be made of tantalum nitride (TaN).

[0087] In yet another example (in Figure 6 In (3) among them), the side wall portion 211S and the bottom portion 211B of the upper barrier film may further include doped ruthenium (Ru). The side wall portion 211S of the upper barrier film may include tantalum nitride (TaN) doped with manganese (Mn) and ruthenium (Ru). The bottom portion 211B of the upper barrier film may include tantalum nitride (TaN) doped with ruthenium (Ru). For example, the side wall portion 211S of the upper barrier film may be made of tantalum nitride (TaN) doped with manganese (Mn) and ruthenium (Ru). The bottom portion 211B of the upper barrier film may be made of tantalum nitride (TaN) doped with ruthenium (Ru).

[0088] The upper filling film 213 may be disposed on the upper barrier film 211. For example, the upper filling film 213 may contact the upper barrier film 211. The upper filling film 213 may fill the remaining portion of the upper wiring trench 210t. Since the upper barrier film 211 is disposed between the upper filling film 213 and the lower wiring structure 110, the upper filling film 213 may not contact the lower wiring structure 110. The upper filling film 213 may contain a conductive material such as copper (Cu).

[0089] The upper capping film 214 may be disposed on the upper fill film 213. The upper capping film 214 may extend along the upper surface of the upper fill film 213. The upper capping film 214 may contact the upper surface of the upper fill film 213. The upper capping film 214 may not be disposed on the upper surface of the upper barrier film 211. Different from that shown, the upper capping film 214 may cover the upper surface of the upper barrier film 211. The upper capping film 214 may include a conductive material such as metal. The upper capping film 214 may include, for example, cobalt (Co). In a semiconductor device according to some embodiments, the upper capping film 214 may be made of cobalt (Co). Tantalum nitride (TaN) doped with manganese (Mn) may be present along the sidewalls of the upper wiring trench 210t, and thus may prevent copper included in the upper fill film 213 from diffusing into the second interlayer insulating film 160. In addition, the upper capping film 214 may be formed on the upper surface of the upper fill film 213, and thus may prevent copper included in the upper fill film 213 from diffusing along the upper surface of the second interlayer insulating film 160. Accordingly, the performance and reliability of the semiconductor device may be improved.

[0090] Figure 7 and Figure 8 is a view for illustrating a semiconductor device according to some embodiments. Figure 9 is a view for illustrating a semiconductor device according to some embodiments. Figure 10 and Figure 11 is a view for illustrating a semiconductor device according to some embodiments. Figure 12 and Figure 13 is a view for illustrating a semiconductor device according to some embodiments. Figure 14 and Figure 15 is a view for illustrating a semiconductor device according to some embodiments. For ease of description, differences from those already described above with reference to Figures 1 to 6 will be described.

[0091] As a reference, Figure 7 is Figure 2 an enlarged view of the P portion of Figure 8 is Figure 3 an enlarged view of the Q portion of Figure 7 and Figure 8 , in a semiconductor device according to some embodiments, the sidewall portion 211S of the upper barrier film may include a first portion 211S_A and a second portion 211S_B.

[0092] The first portion 211S_A of the sidewall of the upper barrier film may include tantalum nitride (TaN) doped with manganese. For example, the first portion 211S_A of the sidewall of the upper barrier film may be made of manganese-doped tantalum nitride (TaN). The second portion 211S_B of the sidewall of the upper barrier film may not contain manganese. The second portion 211S_B of the sidewall of the upper barrier film may include tantalum nitride (TaN) that is not doped with manganese. For example, the second portion 211S_B of the sidewall of the upper barrier film may be made of tantalum nitride (TaN) that is not doped with manganese. The first portion 211S_A of the sidewall of the upper barrier film is disposed on the second portion 211S_B of the sidewall of the upper barrier film. The first portion 211S_A of the sidewall of the upper barrier film may overlap the second interlayer insulating film 160 in the first direction D1 and / or the second direction D2.

[0093] Referring to Figure 9 , in a semiconductor device according to some embodiments, the thickness t22 of the portion of the sidewall portion 211S of the upper barrier film that is located on the lower surface of the upper wiring line trench 210L_t may be greater than the thickness t21 of the portion of the sidewall portion 211S of the upper barrier film that is located on the sidewall of the upper via trench 210V_t. The thickness t22 of the portion of the sidewall portion 211S of the upper barrier film that is located on the lower surface of the upper wiring line trench 210L_t may be greater than the thickness t1 of the portion of the sidewall portion 211S of the upper barrier film that is located on the lower surface of the upper via trench 210V_t. The thickness t21 of the portion of the sidewall portion 211S of the upper barrier film that is located on the sidewall of the upper via trench 210V_t may be equal to the thickness t1 of the portion of the sidewall portion 211S of the upper barrier film that is located on the lower surface of the upper via trench 210V_t. The thicknesses t21 and t22 of the sidewall portion 211S of the upper barrier film may be equal to or greater than the thickness t1 of the bottom 211B of the upper barrier film.

[0094] Referring to Figure 10 and Figure 11 , in a semiconductor device according to some embodiments, the upper barrier film 211 may include the sidewall portion 211S of the upper barrier film and may not include the bottom 211B of the upper barrier film. The upper barrier film 211 may not be disposed between the upper filling film 213 and the lower wiring structure 110. The upper filling film 213 may contact the lower wiring structure 110. For example, the upper filling film 213 may contact the upper surface 113US of the lower filling film.

[0095] Referring to Figure 12 and Figure 13 , in a semiconductor device according to some embodiments, the upper barrier film 211 may include a portion that extends along the upper surface 114US of the lower capping film. The bottom of the upper barrier film ( Figure 4The 211B) in can extend along the upper surface 114US of the lower capping film. The upper barrier film 211 can contact the upper surface 114US of the lower capping film. Since a part of the lower capping film 114 is disposed between the upper barrier film 211 and the lower filling film 113, the upper barrier film 211 may not contact the upper surface 113US of the lower filling film.

[0096] Referring to Figure 14 and Figure 15 , in a semiconductor device according to some embodiments, the lower wiring structure 110 may not include a lower liner ( Figure 2 and Figure 3 the 112) in. The lower barrier film 111 may contact the lower filling film 113. The lower barrier film 111 may contain doped manganese (Mn). In one example, the lower barrier film 111 may include tantalum nitride (TaN) doped with manganese (Mn). In another example, the lower barrier film 111 may include tantalum nitride doped with manganese (Mn) and ruthenium (Ru).

[0097] Figures 16 to 19 is a diagram for showing a semiconductor device according to some embodiments. For ease of description, differences from those already described above with reference to Figures 1 to 6 will be described. As a reference Figure 18 is Figure 16 an enlarged view of the P part of. Figure 19 is Figure 17 an enlarged view of the Q part of. Referring to Figures 16 to 19 , in a semiconductor device according to some embodiments, the upper wiring structure 210 may further include an upper liner 212 disposed between the upper barrier film 211 and the upper filling film 213.

[0098] The upper liner 212 may extend along the sidewalls of the upper wiring trench 210t. The upper liner 212 may not extend along the lower surface of the upper wiring trench 210t. The upper liner 212 may extend along the sidewalls and the lower surface of the upper wiring line trench 210L_t and the sidewalls of the upper viaduct trench 210V_t. The upper liner 212 may not extend along the lower surface of the upper viaduct trench 210V_t. The upper liner 212 may contact the upper barrier film 211 and the upper filling film 213. The upper liner 212 may include, for example, manganese (Mn). In one example, the upper liner 212 may include manganese oxide. The upper liner 212 may include a manganese oxide film. In another example, the upper liner 212 may include a manganese film made of manganese. The upper barrier film 211 may include tantalum nitride (TaN).

[0099] In one example, the upper barrier film 211 may not contain manganese. Manganese may not be doped in the upper barrier film 211. Each of the sidewall portion 211S and the bottom 211B of the upper barrier film may not contain doped ruthenium (Ru). For example, each of the sidewall portion 211S and the bottom 211B of the upper barrier film may be made of tantalum nitride (TaN).

[0100] The sidewall portion 211S of the upper barrier film may contain doped ruthenium (Ru). The sidewall portion 211S of the upper barrier film may include ruthenium-doped tantalum nitride (TaN). The bottom 211B of the upper barrier film may not contain doped ruthenium (Ru). For example, the sidewall portion 211S of the upper barrier film may be made of tantalum nitride (TaN) doped with ruthenium (Ru). The bottom 211B of the upper barrier film may be made of tantalum nitride (TaN) that does not contain ruthenium (Ru).

[0101] Each of the sidewall portion 211S and the bottom 211B of the upper barrier film may contain doped ruthenium (Ru). Each of the sidewall portion 211S and the bottom 211B of the upper barrier film may include ruthenium-doped tantalum nitride (TaN). For example, each of the sidewall portion 211S and the bottom 211B of the upper barrier film may be made of tantalum nitride (TaN) doped with ruthenium (Ru).

[0102] In another example, the upper barrier film 211 may contain manganese. A portion of the upper barrier film 211 may contain doped manganese. The sidewall portion 211S of the upper barrier film may include tantalum nitride (TaN) doped with manganese. The bottom 211B of the upper barrier film may include tantalum nitride (TaN). The bottom 211B of the upper barrier film may not contain manganese (Mn).

[0103] When the upper barrier film 211 contains manganese, whether each of the sidewall portion 211S and the bottom 211B of the upper barrier film contains doped ruthenium (Ru) may be substantially the same as that used Figure 6 described.

[0104] The thicknesses t21 and t22 of the sidewall portion 211S of the upper barrier film may be equal to the thickness t1 of the bottom 211B of the upper barrier film. Different from that shown, as used Figure 9 described, the thicknesses t21 and t22 of the sidewall portion 211S of the upper barrier film may be equal to or greater than the thickness t1 of the bottom 211B of the upper barrier film.

[0105] Figure 20 and Figure 21 are diagrams for showing a semiconductor device according to some embodiments. Figure 22 and Figure 23 are diagrams for showing a semiconductor device according to some embodiments.Figure 24 and Figure 25 is a diagram for showing a semiconductor device according to some embodiments. For ease of description, differences from those already described with reference to Figures 16 to 19 will be described.

[0106] Referring to Figure 20 and Figure 21 , in a semiconductor device according to some embodiments, the upper barrier film 211 may include a portion extending along the upper surface 114US of the lower capping film. The upper barrier film 211 may contact the upper surface 114US of the lower capping film. Since a portion of the lower capping film 114 is disposed between the upper barrier film 211 and the lower filling film 113, the upper barrier film 211 may not contact the upper surface 113US of the lower filling film.

[0107] Referring to Figure 22 and Figure 23 , in a semiconductor device according to some embodiments, the upper barrier film 211 may not be disposed between the upper filling film 213 and the lower wiring structure 110. The upper filling film 213 may contact the lower wiring structure 110. For example, the upper filling film 213 may contact the upper surface 113US of the lower filling film. The upper liner 212 may extend along a portion of the sidewall of the upper barrier film ( Figure 18 and Figure 19 211S in). Different from what is shown, the upper liner 212 may extend to the upper surface 113US of the lower filling film.

[0108] Referring to Figure 24 and Figure 25 , in a semiconductor device according to some embodiments, the lower liner 112 may include manganese (Mn). In one example, the lower liner 112 may include manganese oxide. The lower liner 112 may include a manganese oxide film. In another example, the lower liner 112 may include a manganese film made of manganese. In one example, the lower barrier film 111 may not contain manganese. Manganese may not be doped in the lower barrier film 111. The lower barrier film 111 may include tantalum nitride (TaN) without doped manganese. In another example, the lower barrier film 111 may include tantalum nitride (TaN) doped with manganese (Mn). In yet another example, the lower barrier film 111 may include tantalum nitride (TaN) doped with manganese (Mn) and ruthenium (Ru).

[0109] Figure 26 is a diagram for showing a semiconductor device according to some embodiments. For ease of description, differences from those already described with reference to Figures 1 to 6 will be described. As a reference, Figure 26 shows an example of a cross-sectional view cut along the first gate electrode GE. In Figure 26In it, the fin pattern AF is shown as extending in a first direction D1, and the first gate electrode GE is shown as extending in a second direction D2. However, embodiments of the present disclosure are not limited thereto. Referring to Figure 26 , a semiconductor device according to some embodiments may include a transistor TR disposed between a substrate 10 and a lower wiring structure 110.

[0110] The substrate 10 may be a silicon substrate or silicon-on-insulator (SOI). Alternatively, the substrate 10 may include, but is not limited to, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The transistor TR may include a fin pattern AF, a first gate electrode GE on the fin pattern AF, and a first gate insulating film GI between the fin pattern AF and the first gate electrode GE.

[0111] Although not shown, the transistor TR may include source / drain patterns respectively disposed on two opposite sides of the first gate electrode GE. The fin pattern AF may protrude from the substrate 10. The fin pattern AF may extend in an elongated manner in the first direction D1. The fin pattern AF may be a part of the substrate 10 or may include an epitaxial layer grown from the substrate 10. The fin pattern AF may include, for example, silicon or germanium as an elemental semiconductor material. In addition, the fin pattern AF may include a compound semiconductor, for example, a group-IV-IV compound semiconductor or a group-III-V compound semiconductor.

[0112] The group-IV-IV compound semiconductor may include, for example, a binary compound containing two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), a ternary compound containing three of them, or a compound obtained by doping a group-IV element therein. The group-III-V compound semiconductor may include, for example, a binary compound obtained by combining one of aluminum (Al), gallium (Ga), and indium (In) as a group-III element with one of phosphorus (P), arsenic (As), and antimony (Sb) as a group-V element, a ternary compound obtained by combining two of aluminum (Al), gallium (Ga), and indium (In) as a group-III element with one of phosphorus (P), arsenic (As), and antimony (Sb) as a group-V element, or a quaternary compound obtained by combining three of aluminum (Al), gallium (Ga), and indium (In) as a group-III element with one of phosphorus (P), arsenic (As), and antimony (Sb) as a group-V element.

[0113] The field insulating film 15 may be formed on a part of the sidewall of the fin pattern AF. The fin pattern AF may protrude upward beyond the upper surface of the field insulating film 15. The field insulating film 15 may include, for example, an oxide film, a nitride film, a nitrogen oxide film, or a combination thereof.

[0114] The first gate electrode GE may be disposed on the fin pattern AF. The first gate electrode GE may extend in the second direction D2. The first gate electrode GE may intersect the fin pattern AF.

[0115] The first gate electrode GE may include at least one of, for example, a metal, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, and a conductive metal oxide. The first gate insulating film GI may be disposed between the first gate electrode GE and the fin pattern AF and between the first gate electrode GE and the field insulating film 15. The first gate insulating film GI may include, for example, silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material may include at least one of, for example, boron nitride, a metal oxide, and a metal oxysilicate.

[0116] A semiconductor device according to some embodiments may include an NC (negative capacitance) FET using a negative capacitor. For example, the first gate insulating film GI may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties. The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, when two or more capacitors may be connected in series with each other and the capacitance of each of the capacitors has a positive value, the total capacitance is less than the capacitance of each individual capacitor. In contrast, when at least one of the capacitances of two or more capacitors connected in series with each other has a negative value, the total capacitance may have a positive value and be greater than the absolute value of each individual capacitance.

[0117] When the ferroelectric material film having a negative capacitance and the paraelectric material film having a positive capacitance are connected in series with each other, the total capacitance value of the ferroelectric material film and the paraelectric material film connected in series with each other may increase. By using the increase in the total capacitance value, a transistor including the ferroelectric material film may have a subthreshold swing (SS) of less than about 60 mV / decade at room temperature.

[0118] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanate. In this regard, in one example, hafnium zirconium oxide may refer to a material obtained by doping hafnium oxide with zirconium (Zr). In another example, hafnium zirconium oxide may refer to a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0119] The ferroelectric material film may also include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film may vary according to the type of ferroelectric material included in the ferroelectric material film.

[0120] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include at least one of, for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0121] When the dopant is aluminum (Al), the ferroelectric material film may contain from about 3 at% (atomic percent) to about 8 at% of aluminum. In this regard, the content of the dopant may be the content of aluminum based on the sum of hafnium and aluminum.

[0122] When the dopant is silicon (Si), the ferroelectric material film may contain from about 2 at% to about 10 at% of silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain from about 2 at% to about 10 at% of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain from about 1 at% to about 7 at% of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain from about 50 at% to about 80 at% of zirconium.

[0123] The paraelectric material film may have paraelectric properties. The paraelectric material film may include at least one of, for example, silicon oxide and metal oxides having a high dielectric constant. Although the metal oxides included in the paraelectric material film may include at least one of, for example, hafnium oxide, zirconium oxide, and aluminum oxide. However, the embodiments of the present disclosure are not limited thereto.

[0124] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film may have ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, when each of the ferroelectric material film and the paraelectric material film includes hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0125] The ferroelectric material film may have a thickness dimension that exhibits ferroelectric properties. Although the thickness of the ferroelectric material film may be, for example, in the range of about 0.5 nm to about 10 nm, the embodiments of the present disclosure are not limited thereto. Since the critical thickness for exhibiting ferroelectric properties may vary based on the type of ferroelectric material, the thickness of the ferroelectric material film may vary according to the type of ferroelectric material.

[0126] In one example, the first gate insulating film GI may include a ferroelectric material film. In another example, the first gate insulating film GI may include a plurality of ferroelectric material films spaced apart from each other. The first gate insulating film GI may have a stacked structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0127] A gate capping pattern GE_CAP may be disposed on the first gate electrode GE. A lower wiring structure 110 may be disposed on the first gate electrode GE. The lower wiring structure 110 is shown as not being connected to the first gate electrode GE. However, embodiments of the present disclosure are not limited thereto.

[0128] Figure 27 is a diagram for showing a semiconductor device according to some embodiments. For ease of description, the following description is mainly based on the differences from the description set forth above Figure 26 presented. Referring to Figure 27 , in a semiconductor device according to some embodiments, a transistor TR may include a nanosheet NS, a first gate electrode GE surrounding the nanosheet NS, and a first gate insulating film GI between the first gate electrode GE and the nanosheet NS.

[0129] The nanosheet NS may be disposed on a lower fin pattern BAF. The nanosheet NS may be spaced apart from the lower fin pattern BAF in a third direction D3. The transistor TR is shown as including three nanosheets NS spaced apart from each other in the third direction D3. However, embodiments of the present disclosure are not limited thereto. In another example, the number of nanosheets NS arranged and disposed on the lower fin pattern BAF in the third direction D3 may be greater than 3 or less than 3.

[0130] Each of the lower fin pattern BAF and the nanosheet NS may include, for example, silicon or germanium as an elemental semiconductor material. Each of the lower fin pattern BAF and the nanosheet NS may include a compound semiconductor, for example, a group-IV-IV compound semiconductor or a group-III-V compound semiconductor. The lower fin pattern BAF and the nanosheet NS may include the same material or may include different materials.

[0131] Figures 28 to 30 is a diagram for showing a semiconductor device according to some embodiments. By way of reference, Figure 28 is a plan view for showing a semiconductor device according to some embodiments. Figure 29 is along Figure 28 sectional views cut along line C-C and D-D in Figure 30 is along Figure 28 sectional view cut along line E-E of Figures 28 to 30, the logic cell LC can be disposed on the substrate 10. The logic cell LC can refer to a logic element that performs a specific function (e.g., an inverter, a flip-flop, etc.). The logic cell LC can include vertical transistors (vertical FETs) that constitute the logic element and wirings that connect the vertical transistors to each other.

[0132] The logic cell LC on the substrate 10 can include a first active region RX1 and a second active region RX2. For example, the first active region RX1 can be a PMOSFET region, and the second active region RX2 can be an NMOSFET region. The first active region RX1 and the second active region RX2 can be defined by a trench T_CH defined in the upper portion of the substrate 10. The first active region RX1 and the second active region RX2 can be spaced apart from each other in a first direction D1.

[0133] A first lower epitaxial pattern SPO1 can be disposed on the first active region RX1, and a second lower epitaxial pattern SPO2 can be disposed on the second active region RX2. In a plan view, the first lower epitaxial pattern SPO1 can overlap with the first active region RX1, and the second lower epitaxial pattern SPO2 can overlap with the second active region RX2. The first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2 can be epitaxial patterns formed by a selective epitaxial growth process. The first lower epitaxial pattern SPO1 can be disposed within a first recessed region RS1 of the substrate 10, and the second lower epitaxial pattern SPO2 can be disposed within a second recessed region RS2 of the substrate 10.

[0134] A first active pattern AP1 can be disposed on the first active region RX1, and a second active pattern AP2 can be disposed on the second active region RX2. Each of the first active pattern AP1 and the second active pattern AP2 can have a fin shape that protrudes vertically. In a plan view, each of the first active pattern AP1 and the second active pattern AP2 can have a bar shape that extends in the first direction D1. The first active pattern AP1 can be arranged along a second direction D2, and the second active pattern AP2 can be arranged along the second direction D2.

[0135] Each of the first active pattern AP1 can include a first channel pattern CHP1 that protrudes vertically from the first lower epitaxial pattern SPO1 and a first upper epitaxial pattern DOP1 on the first channel pattern CHP1. Each of the second active pattern AP2 can include a second channel pattern CHP2 that protrudes vertically from the second lower epitaxial pattern SPO2 and a second upper epitaxial pattern DOP2 on the second channel pattern CHP2.

[0136] The element isolation film ST may be disposed on the substrate 10 to fill the trench T_CH. The element isolation film ST may cover the upper surfaces of the first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2. The first active pattern AP1 and the second active pattern AP2 may protrude upward beyond the element isolation film ST. On the element isolation film ST, a plurality of second gate electrodes 420 may be disposed in a parallel manner to each other and extending in the first direction D1. The second gate electrodes 420 may be arranged along the second direction D2. The second gate electrodes 420 may surround the first channel pattern CHP1 of the first active pattern AP1 and the second channel pattern CHP2 of the second active pattern AP2. For example, the first channel pattern CHP1 of the first active pattern AP1 may have first sidewalls SW1 to fourth sidewalls SW4. The first sidewall SW1 and the second sidewall SW2 may face each other in the second direction D2, and the third sidewall SW3 and the fourth sidewall SW4 may face each other in the first direction D1. The second gate electrodes 420 may be disposed on the first sidewalls SW1 to fourth sidewalls SW4. In other words, the second gate electrodes 420 may surround the first sidewalls SW1 to fourth sidewalls SW4.

[0137] The second gate insulating film 430 may be interposed between the second gate electrodes 420 and each of the first channel pattern CHP1 and the second channel pattern CHP2. The second gate insulating film 430 may cover the lower surface and the inner walls of the second gate electrodes 420. For example, the second gate insulating film 430 may directly cover the first sidewalls SW1 to fourth sidewalls SW4 of the first active pattern AP1.

[0138] The first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2 may protrude upward beyond the second gate electrodes 420. The vertical level of the upper surface of the second gate electrodes 420 may be lower than the vertical level of the lower surface of each of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. In other words, each of the first active pattern AP1 and the second active pattern AP2 may protrude vertically from the substrate 10 and extend through the second gate electrodes 420.

[0139] A semiconductor device according to some embodiments may include a vertical transistor in which carriers migrate in a third direction D3. For example, when a voltage is applied to the second gate electrode 420 to turn the transistor "on", carriers may migrate from the lower epitaxial patterns SOP1 and SOP2 through the channel patterns CHP1 and CHP2 to the upper epitaxial patterns DOP1 and DOP2. In a semiconductor device according to some embodiments, the second gate electrode 420 may completely surround sidewalls SW1 to SW4 of the channel patterns CHP1 and CHP2. The transistor according to the present disclosure may be implemented as a three-dimensional field effect transistor (e.g., VFET) having a gate-all-around structure. Since the gate surrounds the channel, the semiconductor device according to some embodiments may have excellent electrical characteristics.

[0140] On the element isolation film ST, spacers 440 may be provided to cover the second gate electrode 420 and the first active pattern AP1 and the second active pattern AP2. The spacers 440 may include a silicon nitride film or a silicon oxynitride film. The spacers 440 may include a lower spacer 440LS, an upper spacer 440US, and a gate spacer 440GS between the lower spacer 440LS and the upper spacer 440US.

[0141] The lower spacer 440LS may directly cover the upper surface of the element isolation film ST. The second gate electrode 420 may be spaced apart from the element isolation film ST in the third direction D3 through the lower spacer 440LS. The gate spacer 440GS may cover the upper surface and outer walls of each of the second gate electrodes 420. The upper spacer 440US may cover the outer walls of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. However, the upper spacer 440US may not cover the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2, such that the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2 are exposed.

[0142] A first portion 190BP of the lower interlayer insulating film may be disposed on the spacers 440. The upper surface of the first portion 190BP of the lower interlayer insulating film may be substantially coplanar with the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. A second portion 190UP of the lower interlayer insulating film, and the first interlayer insulating film 150 and the second interlayer insulating film 160 may be sequentially stacked on the first portion 190BP of the lower interlayer insulating film. The first portion 190BP and the second portion 190UP of the lower interlayer insulating film may be included in the lower interlayer insulating film 190. The second portion 190UP of the lower interlayer insulating film may cover the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2.

[0143] A second portion 190UP extending through the interlayer insulating film may be provided to contact at least one first source / drain contact 470 of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. A second source / drain contact 570 sequentially extending through the interlayer insulating film 190, the lower spacer 440LS, and the element isolation film ST to contact at least one of the first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2 may be provided.

[0144] A second etch stop film 156 may be additionally provided between the second portion 190UP of the interlayer insulating film and the first interlayer insulating film 150. The first etch stop film 155 may be provided between the first interlayer insulating film 150 and the second interlayer insulating film 160.

[0145] The lower wiring structure 110 may be provided in the first interlayer insulating film 150. The upper wiring structure 210 may be provided in the second interlayer insulating film 160. The detailed description of the lower wiring structure 110 and the upper wiring structure 210 may be substantially the same as the description used above Figures 1 to 25 described.

[0146] Figures 31 to 36 is a diagram showing an intermediate structure corresponding to an intermediate step of a method for manufacturing a semiconductor device according to some embodiments. Referring to Figure 31 , in the first interlayer insulating film 150, a lower wiring structure 110 is formed. A lower wiring trench 110t is formed in the first interlayer insulating film 150. In the lower wiring trench 110t, the lower wiring structure 110 is formed. The lower wiring structure 110 may include a lower barrier film 111, a lower liner 112, a lower filling film 113, and a lower capping film 114. Subsequently, a first etch stop film 155 may be formed on the first interlayer insulating film 150 and the lower wiring structure 110. On the first etch stop film 155, the second interlayer insulating film 160 may be formed.

[0147] Referring to Figure 32, an upper wiring trench 210t can be formed within the second interlayer insulating film 160. The second interlayer insulating film 160 can include the upper wiring trench 210t. The upper wiring trench 210t includes an upper via trench 210V_t and an upper wiring line trench 210L_t. The upper wiring trench 210t can extend through the first etch stop film 155. After the first etch stop film 155 has been removed, an exposed portion of the lower capping film 114 can be removed. A portion of the lower capping film 114 disposed between the first etch stop film 155 and the lower fill film 113 can be removed. Although not shown, the lower capping film 114 can be partially undercut beneath the first etch stop film 155. The upper wiring trench 210t can expose a portion of the upper surface 113US of the lower fill film. Different from what is shown, the lower capping film 114 may not be removed while forming the upper wiring trench 210t.

[0148] Referring to Figure 33 , a pre-upper barrier film 211P can be formed along the sidewalls and the lower surface of the upper wiring trench 210t. The pre-upper barrier film 211P can be formed along the upper surface of the second interlayer insulating film 160. In one example, atomic layer deposition (ALD) can be used to form the pre-upper barrier film 211P.

[0149] In another example, atomic layer deposition can be used to form a portion of the pre-upper barrier film 211P. A portion of the pre-upper barrier film 211P can be formed along the sidewalls and the lower surface of the upper wiring trench 210t. Thereafter, physical vapor deposition (PVF) can be used to form the remaining portion of the pre-upper barrier film 211P on a portion of the pre-upper barrier film 211P.

[0150] The pre-upper barrier film 211P is shown as a single film. However, this is only for ease of illustration and embodiments of the present disclosure are not limited thereto. In one example, the pre-upper barrier film 211P can include a tantalum nitride film. In another example, the pre-upper barrier film 211P can be formed as a stack of multiple films in which a first tantalum nitride film, a ruthenium film, and a second tantalum nitride film are sequentially stacked. During the manufacturing process, ruthenium (Ru) included in the ruthenium film can diffuse into the tantalum nitride film, thereby forming ruthenium (Ru)-doped tantalum nitride (TaN).

[0151] Referring to Figure 33 and Figure 34, a pre-fill film can be formed on the pre-barrier film 211P. For example, the pre-fill film can include manganese-doped copper. A plating scheme can be used to form the pre-fill film, for example. However, embodiments of the present disclosure are not limited thereto. The pre-fill film can be formed on the upper surface of the second interlayer insulating film 160. The pre-barrier film 211P provided on the upper surface of the second interlayer insulating film 160 and the pre-fill film provided on the pre-barrier film 211P can be partially removed. Accordingly, the upper barrier film 211 and the upper fill film 213 can be formed in the upper wiring trench 210t. The upper fill film 213 can include copper doped with manganese. Subsequently, an upper capping film 214 can be formed on the upper surface of the upper fill film 213. The upper capping film 214 can extend along the upper surface of the upper fill film 213. Accordingly, an upper wiring structure 210 including an upper wiring line 210L and an upper via 210V can be formed in the upper wiring trench 210t.

[0152] Referring to Figures 34 to 36 , a heat treatment process 50 can be performed. Accordingly, the upper wiring structure 210 can be heat-treated. In one example, in Figure 35 , while the heat treatment process 50 is being performed, manganese (Mn) included in the upper fill film 213 can diffuse into the upper barrier film 211 extending along the sidewalls of the upper wiring trench 210t. Manganese (Mn) included in the upper fill film 213 may not diffuse into the upper barrier film 211 extending along the lower surface of the upper wiring trench 210t. Manganese (Mn) included in the upper fill film 213 can diffuse toward the second interlayer insulating film 160. Manganese (Mn) included in the upper fill film 213 diffuses into the upper barrier film 211 such that the upper barrier film 211 can include tantalum nitride (TaN) doped with manganese (Mn).

[0153] In another example, in Figure 36 , while the heat treatment process 50 is being performed, an upper liner 212 can be formed. The upper liner 212 can be formed by diffusing manganese (Mn) included in the upper fill film 213 toward the upper barrier film 211. The upper liner 212 can be formed at the boundary between the upper barrier film 211 and the upper fill film 213. Different from what is shown, while the heat treatment process 50 is being performed, a lower barrier film including manganese-doped tantalum nitride (TaN) ( Figure 14 and Figure 15 in 111) can be formed. Alternatively, while the heat treatment process 50 is being performed, a lower liner including manganese ( Figure 24 and Figure 25 in 112) can be formed.

[0154] Figure 37 and Figure 38 are diagrams showing intermediate structures corresponding to intermediate steps of a method for manufacturing a semiconductor device according to some embodiments.Figure 37 It can be a process after Figure 32 . Referring to Figure 37 , a selective inhibition film 170 is formed on a portion of the lower wiring structure 110 exposed through the upper wiring trench 210t. The selective inhibition film 170 can be formed on a conductive material. The selective inhibition film 170 is not formed on an insulating material.

[0155] The selective inhibition film 170 can be formed on the upper surface 113US of the underfill film, the upper surface of the lower liner 112, and the upper surface of the lower barrier film 111. Different from what is shown, the selective inhibition film 170 may not be formed on the upper surface of the lower barrier film 111 and / or the upper surface of the lower liner 112. The selective inhibition film 170 includes an organic material. The selective inhibition film 170 can prevent a conductive material from being deposited on a surface on which the selective inhibition film 170 has been formed.

[0156] Referring to Figure 37 and Figure 38 , in a state where the selective inhibition film 170 has been formed, a pre-upper barrier film 211P can be formed along the sidewall of the upper wiring trench 210t. The pre-upper barrier film 211P can be formed along the upper surface of the second interlayer insulating film 160. The pre-upper barrier film 211P is not formed on a portion of the lower wiring structure 110 on which the selective inhibition film 170 has been formed. The pre-upper barrier film 211P may not be formed along the lower surface of the upper wiring trench 210t. The pre-upper barrier film 211P can be formed on the entire sidewall of the upper wiring trench 210t.

[0157] Different from what is shown, the pre-upper barrier film 211P can include a stack of multiple films. In this case, a ruthenium film and a second tantalum nitride film among the films included in the pre-upper barrier film 211P can be formed along the lower surface of the upper wiring trench 210t. The first tantalum nitride film, which is the first formed among the films, is not formed along the lower surface of the upper wiring trench 210t.

[0158] Subsequently, the selective inhibition film 170 can be removed to expose the lower wiring structure 110. The selective inhibition film 170 can be removed by, for example, plasma treatment. However, the embodiments of the present disclosure are not limited thereto. After removing the selective inhibition film 170, a manufacturing process as described using Figures 34 to 36 can be performed.

[0159] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments but can be implemented in various different forms. Those skilled in the art can understand that the present disclosure can be practiced in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects rather than restrictive.

[0160] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the preferred embodiments of the present disclosure are used in a general and descriptive sense only and not for purposes of limitation.

Claims

1. A semiconductor device comprising: a lower wiring structure including a lower barrier film and a lower filling film and disposed within the lower interlayer insulating film; an upper interlayer insulating film disposed on the lower interlayer insulating film, the upper interlayer insulating film having an upper wiring groove therein; as well as an upper wiring structure disposed in the upper wiring trench and electrically connected to the lower wiring structure, the upper wiring structure comprising an upper barrier film, an upper filling film, and an upper capping film disposed on the upper filling film; wherein the upper filling film is disposed on the upper barrier film and contacts the upper barrier film; wherein the upper barrier film includes a sidewall portion extending along a sidewall of the upper wiring trench; and Wherein, the sidewall portion of the upper barrier film comprises tantalum nitride doped with manganese.

2. The semiconductor device according to claim 1, wherein The upper barrier film further includes a bottom portion made of tantalum nitride and extending along a lower surface of the upper wiring trench.

3. The semiconductor device according to claim 2, wherein: A thickness of a sidewall portion of the upper barrier film is equal to or greater than a thickness of a bottom portion of the upper barrier film.

4. The semiconductor device according to claim 1, wherein The sidewall portion of the upper barrier film further includes ruthenium as a dopant.

5. The semiconductor device according to claim 4, wherein: The upper barrier film further includes a bottom portion made of tantalum nitride and extending along a lower surface of the upper wiring trench.

6. The semiconductor device according to claim 4, wherein: The upper barrier film further includes a bottom portion made of ruthenium-doped tantalum nitride and extending along a lower surface of the upper wiring trench.

7. The semiconductor device according to claim 1, wherein The upper filling film contacts the lower wiring structure.

8. The semiconductor device according to claim 1, wherein The lower barrier film includes manganese-doped tantalum nitride and is in contact with the lower fill film.

9. The semiconductor device according to claim 1, wherein: The lower wiring structure further includes a lower liner disposed between the lower barrier film and the lower filling film; wherein the lower barrier film includes manganese; and wherein the lower liner includes cobalt.

10. A semiconductor device comprising: a lower wiring structure including a lower barrier film and a lower filling film and disposed within the lower interlayer insulating film; an upper interlayer insulating film disposed on the lower interlayer insulating film, the upper interlayer insulating film having an upper wiring groove therein; as well as an upper wiring structure disposed in the upper wiring trench and electrically connected to the lower wiring structure, the upper wiring structure comprising an upper barrier film, an upper filling film, and an upper pad extending between the upper barrier film and the upper filling film; Wherein, the upper barrier film comprises tantalum nitride; The upper liner includes manganese and extends along a sidewall of the upper wiring trench but not along a lower surface of the upper wiring trench.

11. The semiconductor device according to claim 10, wherein The upper barrier film includes a sidewall portion extending along a sidewall of the upper wiring trench and a bottom portion extending along a lower surface of the upper wiring trench.

12. The semiconductor device according to claim 11, wherein Each of a sidewall portion of the upper barrier film and a bottom portion of the upper barrier film is made of tantalum nitride.

13. The semiconductor device according to claim 11, wherein A sidewall portion of the upper barrier film is made of tantalum nitride doped with ruthenium, and a bottom portion of the upper barrier film is made of tantalum nitride not containing ruthenium.

14. The semiconductor device according to claim 11, wherein Each of a sidewall portion of the upper barrier film and a bottom portion of the upper barrier film is made of ruthenium-doped tantalum nitride.

15. The semiconductor device according to claim 11, wherein A thickness of a sidewall portion of the upper barrier film is equal to or greater than a thickness of a bottom portion of the upper barrier film.

16. The semiconductor device according to claim 11, wherein The lower wiring structure further includes a lower capping film in contact with an upper surface of the lower filling film; And wherein the upper barrier film is in contact with an upper surface of the lower filling film.

17. The semiconductor device according to claim 10, wherein: The upper barrier film extends along the sidewalls of the upper wiring trench but does not extend along the lower surface of the upper wiring trench; and wherein the upper fill film contacts the upper surface of the lower fill film.

18. The semiconductor device according to claim 10, wherein The upper liner includes manganese oxide.

19. A semiconductor device comprising: a lower wiring structure disposed in a lower interlayer insulating film, the lower wiring structure comprising a lower barrier film, a lower capping film, and a lower filling film in contact with the lower barrier film and the lower capping film; an upper interlayer insulating film disposed on the lower interlayer insulating film and including an upper wiring trench therein; as well as an upper wiring structure disposed in the upper wiring trench and electrically connected to the lower wiring structure, the upper wiring structure comprising an upper barrier film, an upper filling film, and an upper capping film disposed on the upper filling film; wherein the upper filling film is disposed on the upper barrier film and is in contact with the upper barrier film and the upper covering film; Wherein, the upper barrier film includes a sidewall portion and a bottom portion, the sidewall portion extends along the sidewall of the upper wiring trench, and the bottom portion extends along the lower surface of the upper wiring trench; wherein each of the sidewall portion of the upper barrier film and the lower barrier film comprises tantalum nitride doped with manganese; wherein the bottom of the upper barrier film comprises manganese; wherein each of the upper capping film and the lower capping film comprises cobalt; and Wherein, each of the upper filling film and the lower filling film includes copper.

20. The semiconductor device according to claim 19, wherein A sidewall portion of the upper barrier film includes manganese and ruthenium doped tantalum nitride.

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