Overcurrent protection circuit and method
By designing an overcurrent protection circuit including DSP, detection and delay circuit and shutdown timing guarantee circuit, the problem of overcurrent protection point changing with temperature in the prior art is solved, and more reliable overcurrent protection is achieved, and the driver is accidentally turned off when the current peaks of the LLC circuit.
Patent Information
- Application Number
- CN202510133780.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-06
- Publication Date
- 2025-05-30
AI Technical Summary
The overcurrent protection circuit of the existing LLC circuit has caused the protection point to change with the temperature change due to the temperature drift problem of the transistor. It may trigger protection when the power is turned on or not trigger protection during short circuit, causing damage.
An overcurrent protection circuit including a digital signal processor DSP, a detection and delay circuit and a shutdown timing guarantee circuit are designed. The first PWM and the second PWM are output by DSP, the detection and delay circuit detect the LLC circuit current and output the first voltage, and the shutdown timing guarantee circuit determines the second voltage based on the first PWM, the second PWM and the first voltage, and jointly outputs the first signal to control whether to turn off the driving.
The first voltage and the second voltage jointly realize the blocking of the drive, which avoids direct control of the drive by the first voltage output by the overcurrent detection circuit, significantly improves the reliability of overcurrent protection, and prevents the drive from being accidentally turned off when the current peaks of the LLC circuit.
Smart Images
Figure CN120073603A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of circuit protection, and in particular to an overcurrent protection circuit and method. Background Art
[0002] Currently, the switching frequency in an LLC circuit generally reaches 100 - 300 kHz, and an overcurrent protection circuit is usually required to perform protection actions when an overcurrent occurs in the LLC circuit.
[0003] In the past, overcurrent protection was achieved by using a turn - on triode to pull down the chip enable pin to turn off the chip. The temperature drift of the triode is very large, resulting in the overcurrent protection point changing with temperature. Therefore, the past overcurrent protection may trigger protection during startup (the LLC current is larger during startup than during normal operation), or may not trigger protection during a short - circuit and the circuit may be damaged. Summary of the Invention
[0004] To solve the above - mentioned technical problems, the present application provides an overcurrent protection circuit and method.
[0005] The overcurrent protection circuit provided by the present application includes: a digital signal processor DSP, a detection and delay circuit, and a turn - off timing guarantee circuit; wherein,
[0006] The DSP is configured to output a first PWM and a second PWM to the turn - off timing guarantee circuit;
[0007] The detection and delay circuit is configured to detect the current of the resonant circuit LLC circuit, output a first voltage according to the detection result of the LLC circuit current; and input the first voltage to the turn - off timing guarantee circuit;
[0008] The turn - off timing guarantee circuit is configured to determine a second voltage according to the first PWM and the second PWM, output a first signal according to the first voltage and the second voltage, the first signal is used to determine the output signal of the overcurrent protection circuit, and the output signal is used to control whether to turn off the drive.
[0009] The overcurrent protection method provided by the present application is applied to the foregoing overcurrent protection circuit, and the method includes:
[0010] Detect the LLC circuit current, obtain the peak value of the LLC circuit current, and determine a first voltage according to the peak value of the LLC circuit current;
[0011] Determine a second voltage according to the first PWM and the second PWM; the first PWM and the second PWM are output by the DSP;
[0012] Determine a first signal based on a first voltage and a second voltage, determine an output signal of an overcurrent protection circuit based on the first signal, the first PWM, and the second PWM, and the output signal is used to control whether to block the drive.
[0013] In the technical solution of this application, the overcurrent protection circuit includes: a digital signal processor DSP, a detection and delay circuit, and a turn-off timing guarantee circuit; wherein, the DSP is used to output the first PWM and the second PWM to the turn-off timing guarantee circuit; the detection and delay circuit is used to detect the current of the resonant circuit LLC circuit, output a first voltage according to the detection result of the LLC circuit current, and input the first voltage to the turn-off timing guarantee circuit; the turn-off timing guarantee circuit is used to determine a second voltage according to the first PWM and the second PWM, output a first signal according to the first voltage and the second voltage, the first signal is used to determine the output signal of the overcurrent protection circuit, and the output signal is used to control whether to turn off the drive. In this way, the blocking of the drive is realized jointly by the first voltage and the second voltage, avoiding the direct control of the drive by the first voltage output by the overcurrent detection circuit, and effectively improving the reliability of overcurrent protection. Description of the Drawings
[0014] Figure 1 is a schematic diagram of the overcurrent protection circuit provided by an embodiment of this application Figure 1 ;
[0015] Figure 2 is a schematic flow chart of the overcurrent protection method provided by an embodiment of this application;
[0016] Figure 3 is a schematic diagram of the overcurrent protection circuit provided by an embodiment of this application Figure 2 。 Detailed Embodiments
[0017] Next, the technical solutions in the embodiments of this application will be described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of this application without creative efforts shall fall within the protection scope of this application.
[0018] In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0019] It should also be noted that the terms "first", "second", and "third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that, where permitted, "first", "second", and "third" can be interchanged in a specific order or sequence so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.
[0020] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after. It should also be understood that the "indication" mentioned in the embodiments of the present application can be a direct indication, an indirect indication, or a representation of an association relationship. For example, A indicates B, which can mean that A directly indicates B. For example, B can be obtained through A; it can also mean that A indirectly indicates B. For example, A indicates C, and B can be obtained through C; it can also mean that there is an association relationship between A and B. It should also be understood that the "correspondence" mentioned in the embodiments of the present application can represent a direct or indirect correspondence relationship between the two, can also represent an association relationship between the two, or can be an indication and being indicated, configuration and being configured, etc.
[0021] How to improve the reliability of the overcurrent protection circuit is an issue that needs to be considered. For this reason, the following technical solutions of the embodiments of the present application are proposed.
[0022] To facilitate understanding of the technical solutions of the embodiments of the present application, the technical solutions of the present application are described in detail below through specific embodiments. The above related technologies can be arbitrarily combined with the technical solutions of the embodiments of the present application as optional solutions, and they all fall within the protection scope of the embodiments of the present application. The embodiments of the present application include at least some of the following contents.
[0023] Figure 1 is a schematic diagram of the overcurrent protection circuit provided by the embodiments of the present application Figure 1 , such as Figure 1 shown, the overcurrent protection circuit 100 includes: a digital signal processor DSP101, a detection and delay circuit 102, and a turn-off timing guarantee circuit 103; wherein,
[0024] DSP101 is used to output a first PWM and a second PWM to the turn-off timing guarantee circuit 103;
[0025] The detection and delay circuit 102 is used to detect the current of the resonant circuit LLC circuit, output a first voltage V1 according to the detection result of the LLC circuit current; and input the first voltage V1 to the turn-off timing guarantee circuit 103;
[0026] The turn-off timing guarantee circuit 103 is used to determine the second voltage V2 according to the first PWM and the second PWM, output the first signal X1 according to the first voltage V1 and the second voltage V2, and the first signal X1 is used to determine the output signal Xn of the overcurrent protection circuit 100, and the output signal Xn is used to control whether to turn off the drive.
[0027] In some embodiments, the overcurrent protection circuit jointly determines the first signal through the first voltage and the second voltage to achieve the control of the drive.
[0028] In some embodiments, the input end of the detection and delay circuit 102 is connected to the LLC circuit, which is used to detect the current of the LLC circuit, and determine the level of the output first voltage according to the magnitude of the LLC circuit current. Exemplarily, when the LLC circuit current exceeds a certain threshold, the detection and delay circuit 102 outputs the first voltage V1 as a low level.
[0029] In some embodiments, the detection and delay circuit 102 includes a first detection circuit 1021 and a first delay circuit 1022.
[0030] In some embodiments, the first detection circuit 1021 is used to detect the LLC circuit current and output the third voltage V3 according to the detection result of the LLC circuit current.
[0031] In some embodiments, the first detection circuit 1021 includes a comparator 10211; wherein, the comparator 10211 is used to compare the peak current of the LLC circuit current with the first current threshold and output the third voltage V3 according to the comparison result.
[0032] In some embodiments, one input end of the comparator 10211 is connected to the LLC circuit to detect the LLC circuit current. When the peak value of the LLC circuit current is greater than the first current threshold, the third voltage V3 outputs a low level. Among them, the setting of the first current threshold can be determined according to the actual situation, and the present application does not make specific limitations on this.
[0033] In some embodiments, the first delay circuit 1022 is used to delay the high and low level conversion time of the third voltage V3 and output the first voltage V1.
[0034] In some embodiments, the input end of the first delay circuit 1022 is the third voltage V3, and the output end is the first voltage V1.
[0035] In some embodiments, the first delay circuit 1022 is an RC circuit. The RC circuit includes a resistor and a capacitor and is used to extend the conversion time of the high and low levels of the third voltage V3. Exemplarily, when the current of the LLC circuit exceeds the first current threshold, the third voltage V3 is at a low level. After passing through the first delay circuit 1022, the time for the low level of the third voltage V3 to turn to a high level is delayed, that is, the first voltage V1 output by the first delay circuit 1022 remains at a low level. The first voltage V1 is input into the turn-off timing guarantee circuit 103, and the turn-off timing guarantee circuit 103 determines the first signal X1 according to the first voltage V1 and the second voltage V2, and is used to determine the output signal Xn of the overcurrent protection circuit. The output signal Xn is used to control whether to turn off the drive.
[0036] In some embodiments, when the output signal Xn is at a low level, the drive is turned off, and when the output signal Xn is at a high level, the drive is not blocked.
[0037] In some embodiments, the turn-off timing guarantee circuit 103 includes a first OR gate 1031, a second delay circuit 1032, and a second OR gate 1033.
[0038] In some embodiments, the inputs of the first OR gate 1031 are the first PWM and the second PWM, and are used to output the fourth voltage V4 according to the first PWM and the second PWM.
[0039] In some embodiments, the two input terminals of the first OR gate 1031 are respectively the first PWM and the second PWM output by the DSP, and the fourth voltage V4 is determined according to the first PWM and the second PWM. Exemplarily, when both the first PWM and the second PWM output by the DSP are at a high level, the fourth voltage V4 is at a high level, and when the first PWM and the second PWM are both in the drive dead zone, the fourth voltage V4 is at a low level. When the first PWM and the second PWM are both in the drive dead zone, at this time, the DSP output signal ensures a complete drive cycle.
[0040] In some embodiments, the second delay circuit 1032 is used to delay the conversion time of the high and low levels of the fourth voltage V4 and output the second voltage V2.
[0041] In some embodiments, the input terminal of the second delay circuit 1032 is the fourth voltage V4, and the output terminal is the second voltage V2.
[0042] In some embodiments, the second delay circuit 1032 is an RC circuit. The RC circuit includes a resistor and a capacitor and is used to extend the transition time of the high and low levels of the fourth voltage V4. Exemplarily, when both the first PWM and the second PWM are at low level, the fourth voltage V4 is at low level. After passing through the second delay circuit 1032, the transition time of the low level of the fourth voltage V4 to high level is delayed, that is, the second voltage V2 output by the second delay circuit 1032 remains at low level.
[0043] In some embodiments, the turn-off timing guarantee circuit 103 includes a second OR gate 1033. The inputs of the second OR gate 1033 are the first voltage V1 and the second voltage V2. The second OR gate determines the first signal X1 according to the first voltage V1 and the second voltage V2.
[0044] In some embodiments, the overcurrent protection circuit further includes a first AND gate 104 and a second AND gate 105. The input of the first AND gate 104 is the first PWM and the first signal X1, and the output is the second signal to drive A. The input of the second AND gate 105 is the second PWM and the first signal X1, and the output is the third signal to drive B. When the first PWM is at low level or the first signal X1 is at low level, the second signal is at low level, and at this time, drive A is blocked. When the second PWM is at low level or the third signal is at low level, the third signal is at low level, and at this time, drive B is blocked.
[0045] Specifically, when both the first voltage V1 and the second voltage V2 are at low level, that is, the first PWM and the second PWM are at low level, and an overcurrent situation is detected. At this time, the first PWM, the second PWM, and the first signal X1 are all at low level, and at this time, drive A and drive B are blocked. When the first voltage V1 is at low level and the second voltage V2 is still at high level, that is, the first PWM and / or the second PWM is at high level. At this time, the first signal X1 is still at high level, and the blocking of the drive depends on the first PWM and the second PWM at this time. When the first PWM is at low level and the second PWM is at high level, drive A is blocked and drive B is not blocked. When the first PWM is at high level and the second PWM is at low level, drive B is blocked and drive A is not blocked. When the first voltage V1 is at high level and the second voltage V2 is at low level, at this time, no overcurrent in the LLC circuit is detected. At this time, the first signal X1 is at high level, and at this time, the drive is still controlled by the first PWM and the second PWM. In this way, it is ensured that when an overcurrent in the LLC circuit is detected, the drive is not directly blocked, but when a complete driving cycle of the output signal of the DSP is completed, when both the first PWM and the second PWM are at low level, that is, when the second voltage V2 is at low level, the drive is blocked, avoiding turning off the drive at the current peak of the LLC circuit, that is, avoiding directly controlling the turn-off of the drive by the first voltage V1, and improving the reliability of the LLC overcurrent protection.
[0046] In some embodiments, the DSP101 is further configured to detect the first voltage V1 and control the first PWM and the second PWM according to the first voltage V1.
[0047] In some embodiments, the first delay circuit and the second delay circuit are provided to ensure that there is sufficient delay time for the DSP to detect the hardware overcurrent after a single current spike triggers the drive to turn off, and then the DSP controls the output signal.
[0048] In some embodiments, when the DSP detects that V1 is at a low level, that is, the peak value of the LLC circuit current exceeds the first current threshold, that is, an LLC overcurrent phenomenon occurs, the DSP controls the first PWM and the second PWM to become low level within a certain time. At this time, the second voltage V2 is also at a low level, and at this time, the drive is blocked. Then the DSP controls the first PWM and the second PWM to output a high level and continue to drive.
[0049] In some embodiments, when the DSP detects multiple LLC overcurrent phenomena within a certain time, the DSP controls the first PWM and the second PWM to continuously output a low level to achieve complete blocking of the drive. The specific number of overcurrent phenomena detected and the detection period can be determined according to the actual situation, and the present application does not make specific limitations in this regard.
[0050] In some embodiments, when the DSP detects multiple overcurrent phenomena within a certain time and the DSP controls the first PWM and the second PWM to always output a low level, the output second signal of the first AND gate 104 is always at a low level to achieve complete blocking of drive A, and the output third signal of the second AND gate 105 is always at a low level to achieve complete blocking of drive B. The specific number N of overcurrent phenomena detected by the DSP and the time when the overcurrent phenomena reach N are not specifically limited in the present application and can be set according to the actual situation.
[0051] The technical solution of the embodiment of the present application is an overcurrent protection circuit, which is characterized in that the overcurrent protection circuit includes: a digital signal processor DSP, a detection and delay circuit, and a turn-off timing guarantee circuit; wherein, the DSP is configured to output the first PWM and the second PWM to the turn-off timing guarantee circuit; the detection and delay circuit is configured to detect the current of the resonant circuit LLC circuit, output a first voltage according to the detection result of the LLC circuit current; input the first voltage to the turn-off timing guarantee circuit; the turn-off timing guarantee circuit is configured to determine a second voltage according to the first PWM and the second PWM, output a first signal according to the first voltage and the second voltage, the first signal is used to determine the output signal of the overcurrent protection circuit, and the output signal is used to control whether to turn off the drive. In this way, the drive is blocked jointly by the first voltage and the second voltage, avoiding the direct control of the drive by the first voltage output by the overcurrent detection circuit, and effectively improving the reliability of overcurrent protection.
[0052] Figure 2 is a schematic flowchart of the overcurrent protection method provided by an embodiment of the present application. As Figure 2 shown, the method includes the following steps: Applied to any of the above overcurrent protection circuits, the method includes:
[0053] Step 201: Detect the LLC circuit current, obtain the peak value of the LLC circuit current, and determine the first voltage according to the peak value of the LLC circuit current.
[0054] Step 202: Determine the second voltage according to the first PWM and the second PWM; the first PWM and the second PWM are output by the DSP.
[0055] Step 203: Determine the first signal according to the first voltage and the second voltage, and determine the output signal of the overcurrent protection circuit according to the first signal, the first PWM, and the second PWM. The output signal is used to control whether to block the drive.
[0056] In some embodiments, the overcurrent protection circuit includes a DSP, a turn-off timing guarantee circuit, and an overcurrent detection and delay circuit. Among them, the DSP outputs the first PWM and the second PWM to the turn-off timing guarantee circuit. The turn-off timing guarantee circuit determines the second voltage according to the first PWM and the second PWM. The overcurrent detection and delay circuit is used to detect the LLC circuit current, obtain the peak value of the LLC circuit current, determine the first voltage according to the peak value of the LLC circuit current, input the first voltage to the turn-off timing guarantee circuit, and the turn-off timing guarantee circuit determines the first signal according to the first voltage and the second voltage, determines the output signal of the overcurrent circuit according to the first signal, and determines whether to block the drive according to the output signal.
[0057] In some embodiments, determining the first voltage according to the peak value of the LLC circuit current includes: when the peak value of the LLC circuit current is greater than the first current threshold, determining the first voltage as a low level;
[0058] Determining the second voltage according to the first PWM and the second PWM includes: when both the first PWM and the second PWM are at a low level, determining the second voltage as a low level;
[0059] Correspondingly, determining the first signal according to the first voltage and the second voltage includes: when both the first voltage and the second voltage are at a low level, determining the first signal as a low level. When the first signal is at a low level, it is used to block the drive.
[0060] In some embodiments, when the first signal is at a low level, the output signal of the overcurrent circuit is at a low level to implement the blocking of the drive.
[0061] In some embodiments, the overcurrent detection and delay circuit includes an overcurrent detection circuit and a first delay circuit. The overcurrent detection circuit is used to detect the LLC circuit current. When the peak value of the LLC circuit current is greater than the first current threshold, the third voltage output by the overcurrent detection circuit is at a low level, and the third level is input to the first delay circuit. The first delay circuit delays the time for the third voltage to transition from a low level to a high level, so that the first voltage output by the first delay circuit is at a low level.
[0062] In some embodiments, the overcurrent detection circuit includes a comparator. The comparator compares the peak value of the LLC circuit current and the first current threshold and outputs the third voltage. The setting of the first current threshold can be determined according to the actual situation, and the present application does not make specific limitations on this.
[0063] In some embodiments, the turn-off timing detection circuit includes a first OR gate and a second delay circuit. The DSP inputs the first PWM and the second PWM to the first OR gate. When both the first PWM and the second PWM are at a low level, the output fourth voltage of the first OR gate is at a low level, and the fourth voltage is input to the second delay circuit. The second delay circuit delays the time for the fourth voltage to transition from a low level to a high level, so that the second voltage output by the second delay circuit is at a low level.
[0064] In some embodiments, when both the first PWM and the second PWM are in the driving dead zone, that is, both the first PWM and the second PWM are at a low level. At this time, when the second voltage is at a low level, it is used to block the drive. In this way, it is to ensure the integrity of a driving cycle, that is, when a driving cycle ends, the second voltage is low.
[0065] In some embodiments, the turn-off timing detection circuit further includes a second OR gate. The first voltage and the second voltage are inputs to the second OR gate. When both the first voltage and the second voltage are at a low level, the output of the second OR gate is at a low level, that is, the first signal is at a low level. According to the first signal, it is determined that the output signal of this circuit is at a low level, and the drive is blocked.
[0066] In some embodiments, the overcurrent protection circuit further includes a first AND gate and a second AND gate. The input of the first AND gate is the first PWM and the first signal, and the output second signal is sent to drive A. The input of the second AND gate is the second PWM and the first signal, and the output third signal is sent to drive B. When the first PWM is at a low level or the first signal is at a low level, the second signal is at a low level, and at this time, drive A is blocked. When the second PWM is at a low level or the first signal is at a low level, the third signal is at a low level, and at this time, drive B is blocked.
[0067] Specifically, when both the first voltage and the second voltage are at low levels, that is, the first PWM and the second PWM are at low levels, and an overcurrent situation is detected. At this time, the first PWM, the second PWM, and the first signal are all at low levels, and at this time, the driving of Driver A and Driver B is blocked. When the first voltage is at a low level and the second voltage remains at a high level, that is, the first PWM and / or the second PWM is at a high level. At this time, the first signal remains at a high level, and the blocking of the driving depends on the first PWM and the second PWM. When the first PWM is at a low level and the second PWM is at a high level, the driving of Driver A is blocked and the driving of Driver B is not blocked; when the first PWM is at a high level and the second PWM is at a low level, the driving of Driver B is blocked and the driving of Driver A is not blocked. When the first voltage is at a high level and the second voltage is at a low level, at this time, no overcurrent in the LLC circuit is detected, and at this time, the first signal is at a high level. At this time, the driving is still controlled by the first PWM and the second PWM. In this way, it is ensured that when an overcurrent in the LLC circuit is detected, the driving is not directly blocked, but when a complete driving cycle of the output signal of the DSP is completed, when both the first PWM and the second PWM are at low levels, that is, when the second voltage is at a low level, the driving is blocked, avoiding turning off the driving at the current peak of the LLC circuit, that is, avoiding the direct control of the driving shutdown by the first voltage, and improving the reliability of the LLC overcurrent protection.
[0068] In some embodiments, the method further includes: when the first voltage is detected to be at a low level N times within a certain time, controlling the first PWM and the second PWM to output low levels, where when both the first PWM and the second PWM are at low levels, it is used to directly block the driving, and N is a positive integer.
[0069] In some embodiments, the first delay circuit and the second delay circuit are to ensure that after a single current spike triggers the driving to turn off, there is enough delay time for the DSP to detect the hardware overcurrent, and then the DSP controls the output signal.
[0070] In some embodiments, when the DSP detects that the first voltage is at a low level, that is, the peak value of the LLC circuit current exceeds the first current threshold, that is, an LLC overcurrent phenomenon occurs, the DSP controls the first PWM and the second PWM to become low levels. At this time, the second voltage is also at a low level, and at this time, the driving is blocked. Then the DSP controls the first PWM and the second PWM to output high levels and continues to drive.
[0071] In some embodiments, when the DSP detects that the first voltage is at a low level N times within a certain time, that is, when the DSP detects multiple LLC overcurrent phenomena within a certain time, the DSP controls the first PWM and the second PWM to both output low levels to achieve complete blocking of the driving, where the setting of N can be determined according to the actual situation, and the present application does not make specific limitations in this regard. The specific detection period can be determined according to the actual situation, and the present application does not make specific limitations in this regard.
[0072] In some embodiments, when the DSP detects multiple overcurrent phenomena within a certain period of time, the DSP controls the first PWM and the second PWM to always output low levels. Then, the second signal output by the first AND gate is at a low level, completely blocking the drive A. The third signal output by the second AND gate is at a low level, achieving complete blocking of the drive B.
[0073] In the technical solution of the embodiment of the present application, the overcurrent protection circuit detects the LLC circuit current, obtains the peak value of the LLC circuit current, determines the first voltage according to the peak value of the LLC circuit current; determines the second voltage according to the first PWM and the second PWM; the first PWM and the second PWM are output by the DSP; determines the first signal according to the first voltage and the second voltage, and determines the output signal of the overcurrent protection circuit according to the first signal, the first PWM and the second PWM. The output signal is used to control whether to block the drive. In this way, the blocking of the drive is jointly realized by the first PWM, the second PWM and the first signal, avoiding direct control of the drive by the first voltage, and effectively improving the reliability of overcurrent protection.
[0074] The following takes a specific application example to illustrate the technical solution of the embodiment of the present application.
[0075] Figure 3 is a schematic diagram of the overcurrent protection circuit provided by the embodiment of the present application Figure 2 , such as Figure 3As shown, the overcurrent protection circuit includes a DSP, a turn-off timing guarantee circuit, a hardware overcurrent detection and delay circuit, and a software and hardware protection circuit. Among them, the hardware overcurrent detection and delay circuit includes a comparator IC3. The 8th pin of the comparator IC3 is connected to the LLC circuit to detect the LLC circuit current. The output end of the comparator IC3 is connected to a first delay circuit. The first delay circuit is an RC circuit composed of a resistor R13 and a capacitor C2, which extends the time for the low level to turn to high level. The output voltage of the first delay circuit is a first voltage, and the first voltage is output to the turn-off timing protection circuit. The turn-off timing guarantee circuit includes an OR gate IC2A (equivalent to the aforementioned first OR gate) and an OR gate IC2B (equivalent to the aforementioned second OR gate). The signals PWMA (equivalent to the aforementioned first PWM) and PWMB (equivalent to the aforementioned second PWM) output by the DSP are input to the input end of the OR gate IC2A. The OR gate IC2A is connected to a second delay circuit. The second delay circuit is an RC circuit composed of a resistor R4 and a capacitor C3, which extends the time for the low level to turn to high level. Before the DSP acts, both PWMB and PWMA output normal signals, with high and low levels. D2, R4, and C3 ensure that when both PWMB and PWMA output low, they output low quickly, but when PWMA or PWMA turns to high, they output high with a delay. In this way, the output of IC2B can be kept low for a longer time to increase the detection time for the DSP. The output voltage of the second delay circuit is a second voltage, and the first voltage and the second voltage are connected to the input of the OR gate IC2B. The output of the OR gate IC2B is connected to the software and hardware protection circuit. The software and hardware protection circuit includes an AND gate IC1A. The first signal output by the DSP is connected to one input end of the AND gate IC1A through a resistor R15. The output of the turn-off timing guarantee circuit is connected to the other input end of the AND gate IC1A. The current protection circuit also includes an AND gate IC1B (equivalent to the aforementioned first AND gate) and an AND gate IC1C (equivalent to the aforementioned second AND gate). One input end of the AND gate IC1B is connected to PWMA, and the other input end is connected to the output end of the software and hardware protection circuit. One output end of the AND gate IC1C is connected to PWMB, and the other input end is connected to the output end of the software and hardware protection circuit. The output end of the AND gate IC1B is connected to the driver DR-A through a resistor R1. The output end of the AND gate IC1C is connected to the driver DR-B through a resistor R6. One port of the DSP is connected to the output end of the hardware overcurrent detection and delay circuit through a resistor R8 to detect the first voltage. Among them, the DSP is connected to the AND gate IC1A through a resistor R15. This signal is initially at a high level to protect the circuit. When overcurrent is triggered within multiple fixed time periods, this signal becomes low level. As shown in the figure, point A is the voltage on the anode side of D1, and point B is the voltage of pin 4 of the OR gate IC2B.
[0076] When the peak value of the LLC current is greater than the preset protection current value (equivalent to the aforementioned first current threshold), the comparator IC3 operates, and the voltage at point A rapidly drops. Specifically, point A is the output of the comparator. When the voltage value detected at pin 8 of IC3 is greater than the reference voltage, the voltage at point A drops, that is, point A becomes low level. At this time, drive blocking is not performed yet. Here, the drive refers to DR-A and DR-B. When an LLC overcurrent phenomenon occurs, the voltage at point A drops. At this time, if PWMA and PWMB are still in a drive cycle, that is, if PWMA or PWMB is high level, then the voltage at point B is also high level. At this time, point B has not dropped. At this time, the drive is a complementary high-frequency switch with dead time according to the DSP output. When the two signals of the upper and lower arms both go low, point B drops, and at this time, the drive is blocked. Among them, the upper and lower arms refer to the two power transistors connected in parallel to the bus after the full-bridge or half-bridge is connected in series. They refer to DR-A and DR-B. The upper and lower two drives are PWMA and PWMB. The two drives go low simultaneously during the dead time and protection. During protection, that is, when the DSP detects an overcurrent in the LLC circuit, it controls PWMA and PWMB to go low. Point B goes low and then blocks the drive to ensure that the drive is turned off only after it is normally closed, avoiding turning off the drive at the current peak. That is, only when the hardware current limiting can act during the drive dead time, that is, it is necessary to ensure that a drive cycle is completed before the drive can be blocked. The delay at point A is an RC circuit composed of R13 and C2, that is, it extends the time for the low level to turn to high level; the delay at point B is an RC circuit composed of R4 and C3, which also extends the time for the low level to turn to high level. The delay circuits at point A and point B are to ensure that there is enough delay time for the DSP to detect the hardware overcurrent after a single current spike triggers the drive to turn off. The hardware triggers the low level and feedbacks to the DSP through R8. The DSP controls to re-perform frequency soft-start output. If overcurrent occurs multiple times within a certain period, the drive is blocked again. That is, when overcurrent occurs once, point A drops. When R8 feedbacks to the DSP and detects the low level, point B will also go low, and then high-frequency drive is output again. If overcurrent occurs multiple times within a certain period, the DSP will no longer output the drive, that is, both PWMA and PWMB go low to achieve complete drive blocking.
[0077] Exemplarily, when both PWMA and PWMB are low at this time, the corresponding drivers DR-A and DR-B are both blocked. Due to D2, R4, and C3, point B quickly goes low. At this time, if no overcurrent is detected, the signal at point A is high, and the output of IC2B remains high. When PWMA or PWMB transitions from low to high, at this time, DR-A or DR-B depends on the signal at pin 5 of IC1B or the signal at pin 10 of IC1C. When an overcurrent occurs, the voltage at point A is low at this time. Because of D2, R4, and C3, point B remains low. At this time, both A and B are low, the signals at pin 5 of IC1B and pin 10 of IC1C are both low, and the drive remains blocked. At the same time, after the DSP detects that the voltage at point A is low, the DSP controls a re-start of the frequency soft start output. After multiple overcurrents occur, the signal from the DSP connected to the AND gate IC1A through the resistor R15 goes low, completely blocking the drivers DR-A and DR-B. When PWMA is high and PWMB is low, at this time, the driver DR-B is blocked, and the driver DR-A depends on the signal at pin 5 of IC1B. At this time, if no overcurrent is detected, point A is high, and point B is at a high voltage. At this time, the signal at pin 5 of IC1B is high, and the driver DR-A is not blocked. When an overcurrent is detected, point A is low. When PWMA goes low, point B is low. D2, R4, and C3 ensure that both PWMB and PWMA go low quickly when both are low, but are delayed in going high when PWMB or PWMA transitions to high. After the DSP detects an overcurrent, the DSP controls a re-start of the frequency soft start output. After multiple overcurrents occur, the signal from the DSP connected to the AND gate IC1A through the resistor R15 goes low, completely blocking the drivers DR-A and DR-B. In this way, when the PWMA and PWMB signals are inconsistent, the drive is blocked.
[0078] In a conventional overcurrent protection circuit, after detecting an overcurrent directly at point A, it is connected to IC1A to directly control the drive. In this way, the drive will be turned off at the current peak and also during the non-drive period. If DR-A and DR-B are directly controlled by PWMA and PWMB, only the DSP detects the voltage at point A. Because the LLC switching frequency is relatively high and due to the problem of the DSP software detection speed, it takes several or even dozens of switching cycles of overcurrent to be detected, and the LLC overcurrent cannot be protected in a timely manner. However, the overcurrent protection circuit of the present application controls the drive jointly through PWMA, PWMB, and the voltage at point A. The delay circuit also ensures that after a single current spike triggers the drive to turn off, there is sufficient delay time for the DSP to detect the hardware overcurrent, protecting the overcurrent circuit in a timely manner and improving the reliability of overcurrent protection.
[0079] As described above, it is only the specific implementation manner of the present application. However, the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. An overcurrent protection circuit, characterized in that: The overcurrent protection circuit includes: a digital signal processor DSP, a detection and delay circuit and a shutdown timing guarantee circuit; wherein, The DSP is used to output the first PWM and the second PWM to the shutdown timing guarantee circuit; The detection and delay circuit is used to detect the LLC circuit current of the resonant circuit, output a first voltage according to the detection result of the LLC circuit current; and input the first voltage to the shutdown timing guarantee circuit; The shutdown timing guarantee circuit is used to determine the second voltage according to the first PWM and the second PWM, and output a first signal according to the first voltage and the second voltage, the first signal is used to determine the output signal of the overcurrent protection circuit, and the output signal is used to control whether to turn off the drive.
2. The overcurrent protection circuit according to claim 1, characterized in that: The detection and delay circuit includes a first detection circuit and a first delay circuit; wherein, The first detection circuit is used to detect the LLC circuit current and output a third voltage according to the detection result of the LLC circuit current; The first delay circuit is used to delay the high-low level conversion time of the third voltage and output the first voltage.
3. The overcurrent protection circuit according to claim 2, characterized in that: The first detection circuit includes a comparator; wherein, The comparator is used to compare the peak current of the LLC circuit current with the first current threshold, and output the third voltage according to the comparison result.
4. The overcurrent protection circuit according to claim 1, characterized in that: The shutdown timing guarantee circuit includes a first OR gate, a second delay circuit and a second OR gate; wherein, The input of the first OR gate is the first PWM and the second PWM, and is used to output a fourth voltage according to the first PWM and the second PWM; The second delay circuit is used to delay the high-low level conversion time of the fourth voltage and output the second voltage; The input of the second OR gate is the first voltage and the second voltage, and the first signal is determined according to the first voltage and the second voltage.
5. The overcurrent protection circuit according to any one of claims 1 to 4, characterized in that: The DSP is further configured to detect the first voltage, and control the first PWM and the second PWM according to the first voltage.
6. An overcurrent protection method, characterized in that: Applied to the overcurrent protection circuit of any one of claims 1 to 5, the method comprising: Detecting an LLC circuit current, obtaining a peak value of the LLC circuit current, and determining a first voltage according to the peak value of the LLC circuit current; Determine a second voltage according to a first PWM and a second PWM; the first PWM and the second PWM are output by a DSP; A first signal is determined according to the first voltage and the second voltage, and an output signal of the overcurrent protection circuit is determined according to the first signal, the first PWM and the second PWM, and the output signal is used to control whether to block the drive.
7. The method according to claim 6, characterized in that The determining of the first voltage according to the peak value of the LLC circuit current comprises: When the peak value of the LLC circuit current is greater than a first current threshold, determining that the first voltage is a low level; The determining the second voltage according to the first PWM and the second PWM comprises: When both the first PWM and the second PWM are at low levels, determining that the second voltage is at a low level; Correspondingly, determining a first signal according to the first voltage and the second voltage includes: When the first voltage and the second voltage are both at low levels, the first signal is determined to be at a low level, wherein the first signal is used to block driving when it is at a low level.
8. The method according to claim 7, characterized in that The method further comprises: When the first voltage is detected to be at a low level N times within a certain period of time, the first PWM and the second PWM are controlled to output a low level, wherein when the first PWM and the second PWM are both at a low level, the drive is directly blocked, and N is a positive integer.