Clamping circuit
By designing a clamping circuit including main GaN transistors, Miller GaN transistors and capacitor circuits in a bridge driver, combined with a protection circuit of resistors, capacitors and diodes, the Miller wave tip problem caused by instantaneous changes in large voltages is solved, ensuring the normal operation of the transistor and ESD protection.
Patent Information
- Application Number
- CN202410107792.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-30
- Filing Date
- 2024-01-25
- Publication Date
- 2025-05-30
AI Technical Summary
In a bridge driver, when one transistor is turned off and the other transistor is turned on, a transient change of large voltage may occur, causing the gate-drain parasitic capacitor to cause the Miller tip to misdirect the transistor that should be in the off state.
A clamping circuit is designed, including major gallium nitride (GaN) transistors, Miller GaN transistors, and capacitance circuits. A protection mechanism is formed by coupling the capacitor circuit between the main drain and the second node, and introducing resistors, capacitors and diodes into the protection circuit to prevent the occurrence of Miller Pole.
Effectively prevents abnormal operation of the main GaN transistors due to Miller tips, ensures the normal working state of the transistor, and provides protection for ESD events to prevent transistor damage.
Smart Images
Figure CN120074199A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a clamping circuit, and more particularly to an active Miller clamping circuit with a protection mechanism. Background Art
[0002] Generally, a bridge driver includes a transistor in the upper half-bridge and a transistor in the lower half-bridge. Under normal operation, these two transistors do not conduct simultaneously. However, in the case where one of the two transistors conducts while the other transistor is off, when the off transistor instantaneously suffers from a large voltage generated by the conducting transistor (i.e., when the off transistor is affected by a high dV / dt caused by the conducting transistor), a Miller spike is induced at the gate of the off transistor through the gate-drain parasitic capacitance of the off transistor, which may erroneously turn on the transistor that should be in the off state. Summary of the Invention
[0003] In view of this, the present invention provides a clamping circuit. The clamping circuit includes a main gallium nitride (GaN) transistor, a Miller GaN transistor, and a capacitor circuit. The main GaN transistor includes a main gate, a main drain, and a main source coupled to a first node. The Miller GaN transistor includes a Miller gate coupled to a second node, a Miller drain coupled to the main gate, and a Miller source coupled to the first node. The capacitor circuit is coupled between the main drain and the second node. Brief Description of the Drawings
[0004] Figure 1 Shows a clamping circuit according to an embodiment of the present invention.
[0005] Figure 2 Shows a clamping circuit according to another embodiment of the present invention.
[0006] Figure 3 Shows a clamping circuit according to another embodiment of the present invention.
[0007] Figure 4 Shows a clamping circuit according to another embodiment of the present invention.
[0008] Figure 5 Shows a clamping circuit according to another embodiment of the present invention.
[0009] Figure 6 Shows a clamping circuit according to yet another embodiment of the present invention.
[0010] Wherein, the reference numerals are described as follows:
[0011] 1: Clamping circuit
[0012] 1A: Clamping circuit
[0013] 1B: Clamping Circuit
[0014] 1C: Clamping Circuit
[0015] 1D: Clamping Circuit
[0016] 1E: Clamping Circuit
[0017] 3: Detection Circuit
[0018] 10: Main GaN Transistor
[0019] 10A: Main Gate
[0020] 10B: Main Drain
[0021] 10C: Main Source
[0022] 11: Miller GaN Transistor
[0023] 11A: Miller Gate
[0024] 11B: Miller Drain
[0025] 11C: Miller Source
[0026] 12: Capacitance Circuit
[0027] 13: Protection Circuit
[0028] 20: Resistor
[0029] 20A: First Terminal
[0030] 20B: Second Terminal
[0031] 21: Capacitor
[0032] 21A: First Terminal
[0033] 21B: Second Terminal
[0034] 22: Diode
[0035] 22A: Anode
[0036] 22B: Cathode
[0037] 23: Diode
[0038] 23A: Anode
[0039] 23B: Cathode
[0040] 30: Capacitor
[0041] 30A: First Terminal
[0042] 30B: Second Terminal
[0043] 31: Resistor
[0044] 31A: First terminal
[0045] 31B: Second terminal
[0046] 50: ESD protection circuit
[0047] 51: Diode
[0048] 51A: Anode
[0049] 51B: Cathode
[0050] 52: Diode
[0051] 52A: Anode
[0052] 52B: Cathode
[0053] 53: Detection circuit
[0054] 54: Discharge circuit
[0055] 120: Capacitive GaN transistor
[0056] 120A: Capacitive gate
[0057] 120B: Capacitive drain
[0058] 120C: Capacitive source
[0059] 530: Capacitor
[0060] 530A: First terminal
[0061] 530B: Second terminal
[0062] 531: Resistor
[0063] 531A: First terminal
[0064] 531B: Second terminal
[0065] 540: First transistor
[0066] 540A: First gate
[0067] 540B: First drain
[0068] 540C: First source
[0069] N10: First node
[0070] N11: Second node
[0071] S30: Detection signal
[0072] S50: Detection signal Detailed Embodiment
[0073] To make the above objects, features, and advantages of the present invention more apparent and understandable, a preferred embodiment is specifically given below and described in detail in conjunction with the accompanying drawings as follows.
[0074] Figure 1 It shows a clamping circuit according to an embodiment of the present invention. Refer to Figure 1 , the clamping circuit 1 includes a main gallium nitride (GaN) transistor 10, a miller GaN transistor 11, a capacitor circuit 12, and a protection circuit 13. In this embodiment, the main GaN transistor 10 and the miller GaN transistor 11 are N-type transistors. The main GaN transistor 10 includes a main gate 10A, a main drain 10B, and a main source 10C, and the miller GaN transistor 11 includes a miller gate 11A, a miller drain 11B, and a miller source 11C. The main source 10C of the main GaN transistor 10 is coupled to the first node N10, and the first node N10 is coupled to a relatively low potential or ground. The miller gate 11A of the miller GaN transistor 11 is coupled to the second node N11, its miller drain 11B is coupled to the main gate 10A of the main GaN transistor 10, and its miller source 11C is coupled to the first node N10.
[0075] The capacitor circuit 12 is coupled between the main drain 10B of the main GaN transistor 10 and the second node N11 to provide capacitance. In one embodiment, as Figure 1 , the capacitor circuit 12 includes a capacitor GaN transistor 120. In this embodiment, the capacitor GaN transistor 120 is an N-type transistor. The capacitor GaN transistor 120 includes a capacitor gate 120A, a capacitor drain 120B, and a capacitor source 120C. The capacitor source 120C of the capacitor GaN transistor 120 is coupled to the second node N11, its capacitor gate 120A is coupled to the capacitor source 120C, and its capacitor drain 120B is coupled to the main drain 10B of the main GaN transistor 10. Based on the connection architecture of the capacitor GaN transistor 120, the capacitor GaN transistor 120 is provided as a capacitor.
[0076] The protection circuit 13 is coupled between the second node N11 and the first node N10. The protection circuit 13 operates to provide protection to the miller GaN transistor 11 by controlling or determining the voltage at the second node N11 (i.e., the voltage at the miller gate 11A of the miller GaN transistor 11), which avoids the miller GaN transistor from being damaged due to a large voltage occurring at the second node N11.
[0077] The operation of the clamping circuit 1 will be described in detail in the following paragraphs.
[0078] Based on the architecture of the clamping circuit 1, when a voltage is provided to the main drain 10B of the main GaN transistor 10, the voltage at the second node N11 is determined by the voltage at the main drain 10B, the capacitive circuit 12, and the parasitic capacitance formed by the Miller gate 11A and the Miller source 11C of the Miller GaN transistor 11. Specifically, the voltage at the second node N11 is determined by the ratio between the voltage at the main drain 10B and the Miller gate 11A and the capacitance value of the capacitive circuit 12 and the capacitance value of the gate-source capacitance of the Miller GaN transistor 11.
[0079] In the case where the main GaN transistor 10 is turned off (i.e., in the off state), when the voltage of the main drain 10B of the main GaN transistor 10 instantaneously increases, according to the ratio between the capacitance value of the capacitive circuit 12 and the capacitance value of the gate-source capacitance of the Miller GaN transistor 11, the voltage at the second node N11 increases to a relatively high level to turn on the Miller GaN transistor 11. In this way, a discharge path through the Miller GaN transistor 11 is formed between the main gate 10A and the first node N10, such that the charge at the main gate 10A is conducted to the main source 10C through this discharge path, which will maintain the off state of the main GaN transistor 10. According to this embodiment, the Miller spike that may be caused at the main gate 10A due to the parasitic capacitance between the main gate 10A and the main drain 10B of the main GaN transistor 10 when a large voltage is provided to the main drain 10B can be eliminated, which prevents the abnormal operation of the main GaN transistor 10.
[0080] The present invention provides different embodiments of the protection circuit. Refer to Figure 2 , in the clamping circuit 1A, the protection circuit 13 includes a resistor 20, a capacitor 21, and diodes 22 and 23. The resistor 20 includes a first end 20A and a second end 20B. The first end 20A of the resistor 20 is coupled to the second node N11, and its second end 20B is coupled to the first node N10. The capacitor 21 includes a first end 21A and a second end 21B. The first end 21A of the capacitor 21 is coupled to the second node N11, and its second end 21B is coupled to the first node N10. The anode 22A of the diode 22 is coupled to the second node N11, the cathode 22B of the diode 22 is coupled to the cathode 23B of the diode 23, and the anode 23A of the diode 22 is coupled to the first node N10. In the clamping circuit 1A, the operations, architectures, and connections of the main GaN transistor 10, the Miller GaN transistor 11, and the capacitive circuit 12 are similar to those described in the Figure 1 embodiment, and the related descriptions are omitted herein.
[0081] Refer to Figure 2, resistor 20 is coupled between the second node N11 and the first node N10. Resistor 20 provides a discharging path for the second node N11. After the voltage at the second node N11 increases based on the ratio between the capacitance value of the capacitive circuit 12 and the capacitance value of the gate-source capacitance of the Miller GaN transistor 11 as the voltage at the main drain 10B increases, the charge at the second node N11 (i.e., the Miller gate 11A) is conducted to the main source 10C via resistor 20. The discharging speed of the charge at the second node N11 is determined by the resistance value of resistor 20.
[0082] Capacitor 21 is provided with a set capacitance value to supplement the capacitance value of the gate-source capacitance of the Miller GaN transistor 11. When the capacitance value of the gate-source capacitance of the Miller GaN transistor 11 is suitable for obtaining a predetermined ratio between the capacitance value of the capacitive circuit 12 and the capacitance value of the gate-source capacitance of the Miller GaN transistor 11, capacitor 21 can be removed.
[0083] Diodes 22 and 23 are coupled together in opposite directions between the second node N11 and the first node N10, so that the voltage at the second node N11 is protected from the large voltage at the first node N10. Therefore, the Miller GaN transistor 11 will not be damaged by the large voltage at the first node N10.
[0084] Figure 3 is a clamping circuit according to another embodiment of the present invention. Refer to Figure 3 , the clamping circuit 1B includes a detection circuit 3, but does not include Figure 1 and Figure 2 the protection circuit 13 shown. In the clamping circuit 1B, the operations, architectures, and connections of the main GaN transistor 10, the Miller GaN transistor 11, and the capacitive circuit 12 are similar to those described in the Figure 1 and Figure 2 embodiments, and the related descriptions are omitted here. As Figure 3 shown, the detection circuit 3 is coupled between the main gate 10A of the main GaN transistor 10 and the first node N10. The detection circuit 3 detects whether an electrostatic discharge (ESD) event occurs at the main gate 10A to generate a detection signal S30. When the detection circuit 3 detects an ESD event at the main gate 10A, the Miller GaN transistor 11 is turned on according to the detection signal S30 to provide a discharging path between the main gate 10A and the first node N10.
[0085] Refer to Figure 3, the detection circuit 3 includes a capacitor 30 and a resistor 31. The capacitor 30 includes a first terminal 30A and a second terminal 30B. The first terminal 30A of the capacitor 30 is coupled to the main gate 10A, and its second terminal 30B is coupled to the second node N11. The resistor 31 includes a first terminal 31A and a second terminal 31B. The first terminal 31A of the resistor 31 is coupled to the second node N11, and its second terminal 31B is coupled to the first node N10.
[0086] When an ESD event occurs at the main gate 10A, the voltage at the main gate 10A instantaneously increases in response to the ESD event. At this time, based on the component characteristics of the capacitor 30, the detection signal S30 at the second node N11 has a relatively high voltage level in response to the increased voltage at the main gate 10A, that is, the second node N11 has a relatively high voltage. The relatively high voltage at the second node N11 turns on the Miller GaN transistor 11 to provide a discharge path between the main gate 10A and the first node N10, so that the static charge at the main gate 10A is conducted to the first node N10 through the discharge path. Therefore, the main GaN transistor 10 will not be damaged by the ESD event. According to the above operation, the Miller GaN transistor 11, the capacitor 30, and the resistor 31 form an ESD protection circuit.
[0087] Figure 4 Denotes a clamping circuit according to another embodiment of the present invention. Refer to Figure 1 , the clamping circuit 1C includes Figure 1 and Figure 2 the protection circuit 13 shown in Figure 3 and the detection circuit 3 of Figures 1 to 3 . In the clamping circuit 1C, the operations, architectures, and connections of the main GaN transistor 10, the Miller GaN transistor 11, the capacitor circuit 12, the protection circuit 13, and the detection circuit 3 are similar to those described in Figure 4 , and the related descriptions are omitted here. Based on the circuit architecture shown in
[0088] Another embodiment of the protection circuit 13 is as shown in Figure 5 . Refer to Figure 5 , the protection circuit 13 includes an ESD protection circuit 50 and diodes 51 and 52. The ESD protection circuit 50 is coupled between the second node N11 and the first node N10. The anode 51A of the diode 51 is coupled to the second node N11, the cathode 51B of the diode 51 is coupled to the cathode 52B of the diode 52, and the anode 52A of the diode 52 is coupled to the first node N10. In the clamping circuit 1D, the operations, architectures, and connections of the main GaN transistor 10, the Miller GaN transistor 11, and the capacitor circuit 12 are the same as those inFigure 1 Similar to that described in the embodiments, the related description is omitted here.
[0089] Refer to Figure 5 , diodes 51 and 52 are coupled together in opposite directions between the second node N11 and the first node N10, so that the voltage at the second node N11 is protected from the large voltage at the first node N10. Therefore, the Miller GaN transistor 11 will not be damaged by the large voltage at the first node N10.
[0090] When an ESD event occurs at the second node N11 (i.e., the Miller gate 11A of the Miller GaN transistor 11), the ESD protection circuit 50 operates to provide a discharge path between the second node N11 and the first node N10. Refer to Figure 5 , the ESD protection circuit 50 includes a detection circuit 53 and a discharge circuit 54. The detection circuit 53 is coupled between the second node N11 and the first node N10. The detection circuit 53 detects whether an ESD event occurs at the second node N11 or the main drain 10B to generate a detection signal S50. When the detection circuit 53 detects an ESD event at the second node N11 or the main drain 10B, the discharge circuit 54 is enabled according to the detection signal S50 to provide a discharge path between the second node N11 and the first node N10.
[0091] As Figure 5 shown, the detection circuit 53 includes a capacitor 530 and a resistor 531. The capacitor 530 includes a first terminal 530A and a second terminal 530B. The first terminal 530A of the capacitor 530 is coupled to the second node N11, and its second terminal 530B is coupled to the third node N50. The resistor 531 includes a first terminal 531A and a second terminal 531B. The first terminal 531A of the resistor 531 is coupled to the third node N50, and its second terminal 531B is coupled to the first node N10. The discharge circuit 54 includes a first transistor 540. In this embodiment, the first transistor is implemented by a GaN transistor. The first transistor 540 is an N-type transistor. The first transistor 540 includes a first gate 540A, a first drain 540B, and a first source 540C. The first gate 540A of the first transistor 540 is coupled to the third node N50 between the capacitor 530 and the resistor 531, its first drain 540B is coupled to the second node N11, and its first source 540C is coupled to the first node N10.
[0092] When an ESD event occurs at the second node N11 or at the main drain 10B, the voltage at the second node N11 instantaneously increases in response to the ESD event at the second node N11 or in response to the ESD event at the main drain 10B based on the component characteristics of the capacitive circuit 12. At this time, based on the component characteristics of the capacitor 530, the detection signal S50 at the third node N50 has a relatively high voltage level in response to the increased voltage at the second node N11, that is, the third node N50 has a relatively high voltage. The relatively high voltage at the third node N50 turns on the first transistor 540 to provide a discharge path between the second node N11 and the first node N10, so that the static charge at the second node N11 is conducted to the first node N10 through the discharge path. Therefore, the first transistor 540 will not be damaged due to the ESD event.
[0093] Figure 6 It represents a clamping circuit according to another embodiment of the present invention. Refer to Figure 6 , the clamping circuit 1E includes Figure 5 the protection circuit 13 shown in Figure 3 and the detection circuit 3 shown in Figure 3 and Figure 4 The operations, architectures, and connections of the main GaN transistor 10, the Miller GaN transistor 11, the capacitive circuit 12, the protection circuit 13, and the detection circuit 3 are similar to those described in Figure 6 , and the related descriptions are omitted here. Based on Figure 6 the circuit architecture shown, the clamping circuit 1E is arranged to provide protection for the main GaN transistor 10 (including ESD protection), and also provide protection for the Miller GaN transistor 11 (including ESD protection).
[0094] Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the defined by the appended claims.
Claims
1. A clamping circuit, comprising: a main gallium nitride (GaN) transistor including a main gate, a main drain, and a main source coupled to a first node; A Miller GaN transistor comprising a Miller gate coupled to a second node, a Miller drain coupled to the main gate, and a Miller source coupled to the first node; as well as A capacitor circuit is coupled between the main drain and the second node.
2. The clamping circuit as claimed in claim 1, wherein: The capacitor circuit includes: A capacitor gallium nitride transistor includes a capacitor source coupled to the second node, a capacitor gate coupled to the capacitor source, and a capacitor drain coupled to the main drain.
3. The clamping circuit as claimed in claim 1, further comprising a protection circuit coupled to the second node and the first node, wherein: The protection circuit includes: a first resistor, comprising a first end coupled to the second node and a second end coupled to the first node; a first capacitor, comprising a first terminal coupled to the second node and a second terminal coupled to the first node; a first diode including a first anode coupled to the second node and a first cathode; and A second diode includes a second anode coupled to the first node and a second cathode coupled to the first cathode.
4. The clamping circuit as claimed in claim 3, further comprising: a detection circuit coupled between the main gate of the main GaN transistor and the first node, The detection circuit detects whether an electrostatic discharge event occurs at the main gate to generate a detection signal, and In response to the detection circuit detecting the electrostatic discharge event occurring at the main gate, the Miller GaN transistor is turned on according to the detection signal.
5. The clamping circuit as claimed in claim 4, wherein: The detection circuit includes: a second capacitor including a first terminal coupled to the main gate and a second terminal coupled to the second node; and a second resistor, comprising a first end coupled to the second node and a second end coupled to the first node, Wherein, the detection signal is generated at the second node.
6. The clamping circuit of claim 1, further comprising: a detection circuit coupled between the main gate of the main GaN transistor and the first node, The detection circuit detects whether an electrostatic discharge event occurs at the main gate to generate a detection signal, and In response to the detection circuit detecting the electrostatic discharge event occurring at the main gate, the Miller GaN transistor is turned on according to the detection signal.
7. The clamping circuit as claimed in claim 6, wherein: The detection circuit includes: a capacitor including a first terminal coupled to the main gate and a second terminal coupled to the second node; and a resistor, comprising a first end coupled to the second node and a second end coupled to the first node, Wherein, the detection signal is generated at the second node.
8. The clamping circuit as claimed in claim 1, further comprising a protection circuit coupled to the second node and the first node, wherein: The protection circuit includes: a first diode including a first anode coupled to the second node and a first cathode; a second diode including a second anode coupled to the first node and a second cathode coupled to the first cathode; and an electrostatic discharge protection circuit coupled between the second node and the first node, In response to a first electrostatic discharge event occurring at the second node or at the main drain, the electrostatic discharge protection circuit provides a discharge path between the second node and the first node.
9. The clamping circuit as claimed in claim 8, wherein: The electrostatic discharge protection circuit comprises: a detection circuit coupled between the second node and the first node, wherein the detection circuit detects whether the first electrostatic discharge event occurs at the second node or the main drain to generate a detection signal; and a discharge circuit, receiving the detection signal, In response to the detection circuit detecting the first electrostatic discharge event occurring at the second node or the main drain, the discharge circuit provides the discharge path between the second node and the first node according to the detection signal.
10. The clamping circuit of claim 9, wherein: The detection circuit includes: a capacitor including a first end coupled to the second node and a second end coupled to a third node; and A resistor includes a first end coupled to the third node and a second end coupled to the first node.
11. The clamping circuit of claim 10, wherein: The discharge circuit includes: a first transistor, comprising a first gate coupled to the detection circuit to receive the detection signal, a first drain coupled to the second node, and a first source coupled to the first node, In response to the detection circuit detecting the first electrostatic discharge event occurring at the second node or the main drain, the detection circuit generates the detection signal at the third node, and the first transistor is turned on according to the detection signal.
12. The clamping circuit of claim 11, wherein: The first transistor is implemented as a gallium nitride transistor.
13. The clamping circuit of claim 8, further comprising: a detection circuit coupled between the main gate of the main GaN transistor and the first node, The detection circuit detects whether a second electrostatic discharge event occurs at the main gate to generate a detection signal, and In response to the detection circuit detecting the second electrostatic discharge event occurring at the main gate, the Miller GaN transistor is turned on according to the detection signal.
14. The clamping circuit of claim 13, wherein: The detection circuit includes: a capacitor including a first terminal coupled to the main gate and a second terminal coupled to the second node; and a resistor, comprising a first end coupled to the second node and a second end coupled to the first node, Wherein, the detection signal is generated at the second node.