Power circuit, direct current converter and power management system

Abstract

The invention relates to the technical field of direct-current converters, in particular to a power circuit, a direct-current converter and a power management system. According to the scheme, after the control signal is received, the half-bridge switch module controls the charging and discharging state of the inductor according to the control signal, and meanwhile, the single-capacitor switch module reduces the current of the inductor under the control of the control signal, so that the direct-current resistance loss of the inductor is reduced, and the power density of the power circuit is systematically improved.

Description

Technical Field

[0001] The present invention relates to the technical field of DC converters, and specifically relates to a power circuit, a DC converter, and a power management system. Background Art

[0002] With the rapid development of AI computing technology, DC-DC converters under the 12V bus architecture are facing many higher requirements and severe challenges. In an AI computing system, from data center servers to AI acceleration chips widely distributed at the edge and endowing various devices with intelligent features, stable and efficient power supply is the foundation for their normal operation. For DC-DC converters under the 12V bus architecture, the first and foremost is the problem of climbing power density. When the AI chip is operating, the power consumption shows a drastic fluctuation, and instantaneous high-power demands emerge frequently. This forces the converter to achieve a higher level of power conversion efficiency within an extremely limited package size range and minimize energy loss to the greatest extent.

[0003] Affected by both the volume and the DC resistance on the conversion efficiency, the existing converters are not only difficult to achieve a considerable volume compression, but also frequently suffer from high-voltage impacts in the hard-switching operation mode, resulting in a rapid increase in the switching loss of the switching tube, thereby limiting the overall efficiency of the converter. Summary of the Invention

[0004] A power circuit, a DC converter, and a power management system provided by the present invention effectively solve the problem that the existing converter has large losses on switching devices under high voltage and large current conditions, thereby reducing the power conversion efficiency.

[0005] According to a first aspect, in one embodiment, a power circuit is provided, including: a half-bridge switch module, an inductor, and a single-capacitor switch module;

[0006] The input end of the half-bridge switch module is connected to the power input end, and the output end of the half-bridge switch module is connected to the first end of the inductor;

[0007] The second end of the inductor is connected to the input end of the single-capacitor switch module, and the output end of the single-capacitor switch module is connected to the power output end;

[0008] The half-bridge switch module is used to control the charging and discharging of the inductor according to a control signal; the single-capacitor switch module is used to reduce the current of the inductor under the control of the control signal to reduce the DCR loss of the inductor.

[0009] In an implementable embodiment, the half-bridge switch module includes a first switch unit and a second switch unit, and the single-capacitor switch module includes a third switch unit, a fourth switch unit, a fifth switch unit, and a flying capacitor;

[0010] The first end of the inductor is connected to the power input terminal through the first switching unit, and the second end of the inductor is connected to the power output terminal through the third switching unit; the first end of the second switching unit is connected to the first end of the inductor, and the second end of the second switching unit is grounded;

[0011] The first end of the flying capacitor is connected to the second end of the inductor, the second end of the flying capacitor is grounded through the fifth switching unit, and the second end of the flying capacitor is also connected to the power output terminal through the fourth switching unit.

[0012] In an implementable embodiment, under the control of the first control signal group, the first switching unit, the third switching unit, and the fifth switching unit are turned on, and the second switching unit and the fourth switching unit are turned off to enter the first operating state;

[0013] Under the control of the second control signal group, the second switching unit and the fourth switching unit are turned on, and the first switching unit, the third switching unit, and the fifth switching unit are turned off to enter the second operating state;

[0014] Under the control of the third control signal group, the first switching unit and the fourth switching unit are turned on, and the second switching unit, the third switching unit, and the fifth switching unit are turned off to enter the third operating state;

[0015] Under the control of the fourth control signal group, the second switching unit, the third switching unit, and the fifth switching unit are turned on, and the first switching unit and the fourth switching unit are turned off to enter the fourth operating state.

[0016] In an implementable embodiment, the power circuit has one or more of the first operating mode, the second operating mode, the third operating mode, and the fourth operating mode;

[0017] When the power circuit alternately receives the first control signal group and the second control signal group, it operates in the first operating mode and alternately enters the first operating state and the second operating state;

[0018] When the power circuit alternately receives the first control signal group and the third control signal group, it operates in the second operating mode and alternately enters the first operating state and the third operating state;

[0019] When the power circuit alternately receives the first control signal group and the fourth control signal group, it operates in the third operating mode and alternately enters the first operating state and the fourth operating state;

[0020] When the power circuit alternately receives the third control signal group and the fourth control signal group and operates in the fourth operating mode, it alternately enters the third operating state and the fourth operating state.

[0021] In an implementable embodiment, the power circuit further includes an output capacitor. The first end of the output capacitor is connected to the second end of the third switch unit, and the second end of the output capacitor is grounded.

[0022] According to a second aspect, an embodiment provides a DC converter, including the above-mentioned power circuit, and further including: a voltage division sampling module, a reconstruction mode selection module, a pulse modulation control module, and an adjustable dead-time clock generator;

[0023] The voltage division sampling module is used to sample the input voltage and the output voltage;

[0024] The reconstruction mode selection module is used to control the output of the corresponding operating mode according to the voltage transformation ratio of the sampled input voltage and output voltage;

[0025] The pulse modulation control module is used to perform real-time linear regulation and load regulation on the output voltage, and then output a clock signal;

[0026] The adjustable dead-time clock generator is used to generate a control signal according to the clock signal, the operating mode, and a preset bit signal and output it to the power circuit; the preset bit signal is used to modulate the dead-time width of the adjustable dead-time clock generator.

[0027] In an implementable embodiment, the DC converter has one or more of the first operating mode, the second operating mode, the third operating mode, and the fourth operating mode;

[0028] When the DC converter operates in the first operating mode, the adjustable dead-time clock generator alternately outputs the first control signal group and the second control signal group to the power circuit, so that the power circuit alternately enters the first operating state and the second operating state;

[0029] When the DC converter operates in the second operating mode, the adjustable dead-time clock generator alternately outputs the first control signal group and the third control signal group to the power circuit, so that the power circuit alternately enters the first operating state and the third operating state;

[0030] When the DC converter operates in the third operating mode, the adjustable dead-time clock generator alternately outputs the first control signal group and the fourth control signal group to the power circuit, so that the power circuit alternately enters the first operating state and the fourth operating state;

[0031] When the DC converter operates in the fourth operating mode, the adjustable dead-time clock generator alternately outputs a third control signal group and a fourth control signal group to the power circuit, causing the power circuit to alternately enter a third operating state and a fourth operating state.

[0032] In an implementable embodiment, when 0 < M ≤ 0.3, the DC converter operates in the first operating mode; when 0.3 < M ≤ 0.48, the DC converter operates in the fourth operating mode; when 0.48 < M ≤ 0.52, the DC converter operates in the first operating mode; when 0.52 < M < 1, the DC converter operates in the second operating mode; where M is the voltage transformation ratio of the DC converter.

[0033] In an implementable embodiment, the pulse modulation control module includes: an error amplifier, a comparator, and a triangular wave generator;

[0034] The negative input terminal of the error amplifier is connected to the output voltage of the voltage dividing and sampling module, the positive input terminal of the error amplifier is connected to a preset reference voltage, and the output terminal of the error amplifier is connected to the positive input terminal of the comparator;

[0035] The output terminal of the triangular wave generator is connected to the negative input terminal of the comparator, and the input terminal of the triangular wave generator is used to input the maximum and minimum values of the triangular wave signal; the output terminal of the comparator is connected to the adjustable dead-time clock generator.

[0036] In an implementable embodiment, the voltage dividing and sampling module includes an input voltage sampling sub-module and an output voltage sampling sub-module;

[0037] The input voltage sampling sub-module includes a first voltage dividing resistor and a second voltage dividing resistor. The first end of the first voltage dividing resistor is connected to the power input terminal, the second end of the first voltage dividing resistor is connected to the first end of the second voltage dividing resistor, and the second end of the second voltage dividing resistor is grounded; the input terminal of the reconstruction mode selection module is connected to the second end of the first voltage dividing resistor;

[0038] The output voltage sampling sub-module includes a third voltage dividing resistor and a fourth voltage dividing resistor. The first end of the third voltage dividing resistor is connected to the power output terminal, the second end of the third voltage dividing resistor is connected to the first end of the fourth voltage dividing resistor, and the second end of the fourth voltage dividing resistor is grounded; the negative input terminal of the error amplifier is connected to the second end of the third voltage dividing resistor.

[0039] According to a third aspect, an embodiment provides a power management system including the DC converter as described above.

[0040] A power circuit, a DC converter, and a power management system according to the above embodiments. After receiving a control signal, the half-bridge switch module controls the charging and discharging state of the inductor according to the control signal. At the same time, the single-capacitor switch module reduces the current of the inductor under the control of the control signal to reduce the DC resistance loss of the inductor, thereby systematically improving the power density of the power circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a schematic structural diagram of the power circuit provided in this embodiment;

[0042] Figure 2 is a circuit structure diagram of the first operating mode provided in this embodiment, where (A) is the circuit structure diagram of the first operating state and (B) is the circuit structure diagram of the second operating state;

[0043] Figure 3 is a circuit structure diagram of the second operating mode provided in this embodiment, where (A) is the circuit structure diagram of the first operating state and (C) is the circuit structure diagram of the third operating state;

[0044] Figure 4 is a circuit structure diagram of the third operating mode provided in this embodiment, where (A) is the circuit structure diagram of the first operating state and (D) is the circuit structure diagram of the fourth operating state;

[0045] Figure 5 is a circuit structure diagram of the fourth operating mode provided in this embodiment, where (C) is the circuit structure diagram of the third operating state and (D) is the circuit structure diagram of the fourth operating state;

[0046] Figure 6 is a structure diagram of the switch body diode and its conduction principle in the dead time state provided in this embodiment. Among them, (a) is the circuit structure diagram of the switch unit as the body diode, and (b) is the conduction principle structure diagram of the body diode in the dead time state;

[0047] Figure 7 is an analysis curve graph of the inductor current and the voltage of the internal node corresponding to the dead time in the hard switching mode and the soft switching mode provided in this embodiment;

[0048] Figure 8 is an effect diagram of the conversion efficiency in different operating modes provided in this embodiment;

[0049] Figure 9 is an effect diagram of the conduction loss in different operating modes provided in this embodiment;

[0050] Figure 10 is a circuit structure diagram of the DC converter provided in this embodiment.

[0051] Reference numerals: 10, power circuit; 11, half-bridge switch module; 12, inductor; 13, single-capacitor switch module; 20, voltage division and sampling module; 21, input voltage sampling sub-module; 22, output voltage sampling sub-module; 30, reconstruction mode selection module; 40, pulse modulation control module; 50, adjustable dead-time clock generator. Detailed implementation manners

[0052] The present invention will be further described in detail below in conjunction with the accompanying drawings through specific implementation manners. Similar elements in different implementation manners are labeled with related similar element numbers. In the following implementation manners, many detailed descriptions are provided to enable a better understanding of the present application. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification to avoid overwhelming the core part of the present application with excessive descriptions. For those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations based on the descriptions in the specification and the general technical knowledge in the art.

[0053] In addition, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various implementation manners. At the same time, the steps or actions in the method description can also be reordered or adjusted in a manner obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for clearly describing a certain embodiment and do not mean that they are the necessary sequences, unless it is stated that a certain sequence must be followed.

[0054] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meanings. The terms "connection" and "coupling" used in the present application, unless otherwise specified, both include direct and indirect connections (couplings).

[0055] As AI devices continue to move towards miniaturization and integration, the limitations on the physical size of converters are becoming increasingly stringent. Among them, inductive components have become a thorny bottleneck, which is mainly reflected in the dual impact of volume and DC resistance (DCR) on conversion efficiency. In terms of volume, due to congenital design factors such as the inherent characteristics of the magnetic core material and the fixed mode of the coil winding, it is difficult for traditional inductors to achieve a significant volume reduction. In addition, in the case of large load currents required by AI computing, the size of the DCR of the inductor determines the overall power supply efficiency. Moreover, in the hard-switching operating mode, the switching transistor needs to instantaneously switch between conduction and cutoff under high voltage and large current conditions. This process will inevitably cause voltage and current overlap, causing the switch to instantaneously withstand extremely high voltage stress. To ensure the reliability of the hard-switching in high-frequency switching operations, in the existing technology, it is necessary to select switching devices with a breakdown voltage rating far exceeding the conventional design standard, which undoubtedly greatly increases the implementation cost of the DC-DC converter. At the same time, the switching losses of the switching transistor increase rapidly due to frequent high-voltage impacts, limiting the overall efficiency of the converter.

[0056] Although the existing buck converter (quasi-resonant soft-switching technology) uses the parasitic capacitance / output capacitance as the resonant capacitance and the inductor to achieve the resonant process during the dead time, enabling the voltage or current of the switching transistor to return to zero, and can achieve the state of zero-voltage turn-on or zero-current turn-off. However, this converter requires a higher operating frequency, which will bring high switching losses and reliability problems in high-frequency switching. In addition, the large inductor current requirement will result in a large inductor volume.

[0057] The solution proposed in this application is to use a capacitor with lower cost and smaller volume to significantly reduce the inductor current, so as to improve the power density of the converter; and, without adding components, the structure can be reconstructed to achieve the optimal performance scheme within different ranges; at the same time, soft-switching technology is used to eliminate the diode conduction loss during the dead time and relieve the voltage stress of the switch to ensure reliability. The specific implementation scheme is as follows.

[0058] As Figure 1 shown, a power circuit 10 provided in this embodiment includes: a half-bridge switch module 11, an inductor 12, and a single-capacitor switch module 13; the input end of the half-bridge switch module 11 is connected to the power input end, and the output end of the half-bridge switch module 11 is connected to the first end of the inductor 12; the second end of the inductor 12 is connected to the input end of the single-capacitor switch module 13, and the output end of the single-capacitor switch module 13 is connected to the power output end; the half-bridge switch module 11 is used to control the charging and discharging of the inductor 12 according to the control signal; the single-capacitor switch module 13 is used to reduce the current of the inductor 12 under the control of the control signal, so as to reduce the DCR loss of the inductor 12.

[0059] Specifically, the half-bridge switching module 11 includes a first switching unit S1 and a second switching unit S2, and the single-capacitor switching module 13 includes a third switching unit S3, a fourth switching unit S4, a fifth switching unit S5, and a flying capacitor CF. The first end of the inductor 12 is connected to the power input terminal through the first switching unit S1, and the second end of the inductor 12 is connected to the power output terminal through the third switching unit S3. The first end of the second switching unit S2 is connected to the first end of the inductor 12, and the second end of the second switching unit S2 is grounded. The first end of the flying capacitor CF is connected to the second end of the inductor 12, the second end of the flying capacitor CF is grounded through the fifth switching unit S5, and the second end of the flying capacitor CF is also connected to the power output terminal through the fourth switching unit S4.

[0060] In order to ensure reliability, this embodiment selects low-voltage switches with more performance advantages. Without adding the soft-switching control technology of an additional resonant inductor 12, the resonant effect is only applied near the dead time, effectively eliminating potential switch transient overvoltage problems, expanding the switch steady-state operating voltage range, and also eliminating the diode conduction loss within the dead time. At the same time, the hard-switching loss is reduced by means of zero-voltage switching operation, achieving performance improvement in aspects such as the output voltage range, switch loss, and conduction loss from the topology control level.

[0061] The solution of this embodiment mainly uses a flying capacitor CF and an inductor 12 to achieve a step-down ratio of 0-1. Moreover, the half-bridge switching module 11 is composed of two high-voltage switches, and the single-capacitor switching module 13 is composed of three low-voltage switches. The structural inductor 12 part (half-bridge switching module 11) is placed in front of the input terminal, and the SC structure part (single-capacitor switching module 13) plays the role of the main current output. This makes the topology structure of this application have the following characteristics: 1) The inductor 12 is located at the input terminal, and the steady-state current of the inductor 12 is less than the output current. Therefore, the influence of DCR (direct current resistance) on the conduction loss is reduced; 2) The third switching unit S3, the fourth switching unit S4, and the fifth switching unit S5 only need to withstand a voltage equal to V OUT , and low-voltage devices with higher quality factors can be used under the condition of a lower output voltage to reduce switch conduction and parasitic losses; 3) The first switching unit S1 and the second switching unit S2 at the left end of the inductor 12 pass through a current equal to the current of the inductor 12, that is, less than the load current. Compared with the buck structure, the resistance of S1 and S2 as high-voltage switches accounts for a lower proportion in the overall conduction loss. Therefore, the component area is correspondingly reduced, reducing the switch parasitic influence.

[0062] In practical applications, by analyzing different switch state combinations, the structure can be reconstructed to achieve different theoretical conversion ranges. Combining Figure 8 and Figure 9, in this embodiment, through corresponding theoretical analysis and modeling and simulation, the advantages of different structures in reducing losses are utilized to achieve the optimal performance solutions within different ranges.

[0063] Among them, Figures 2 - 4 four switching operation states (A), (B), (C), and (D) are given. Theoretically, six different combination methods can be obtained based on the four operation states. However, in the B-C combination, the flying capacitor CF is always in the charging state; in the B-D combination, the inductor L2 is always in the discharging state, and these two combinations cannot achieve the normal operation of the converter. Therefore, after excluding these two unreasonable combinations, the remaining state combinations are respectively as Figures 2 - 5 shown in the A-B combination, A-C combination, A-D combination, and C-D combination. These four combinations can form four different topological structures with different characteristics such as voltage transformation ratio range, conduction loss, and steady-state current of the inductor L2. Since the number of components, component types, switch withstand voltage characteristics, and switch drive voltages in the four structures are exactly the same, the power circuit 10 of the present application can achieve the reconstruction of the power stage topology with the lowest hardware and circuit design costs to achieve the purpose of efficiency optimization at different voltage transformation ratios.

[0064] The different combination states are started under the control of different control signals. Specifically, the power circuit 10 has one or more of the first operation mode, the second operation mode, the third operation mode, and the fourth operation mode. When the power circuit 10 alternately receives the first control signal group and the second control signal group, it operates in the first operation mode and alternately enters the first operation state and the second operation state; when the power circuit 10 alternately receives the first control signal group and the third control signal group, it operates in the second operation mode and alternately enters the first operation state and the third operation state; when the power circuit 10 alternately receives the first control signal group and the fourth control signal group, it operates in the third operation mode and alternately enters the first operation state and the fourth operation state; when the power circuit 10 alternately receives the third control signal group and the fourth control signal group and operates in the fourth operation mode, it alternately enters the third operation state and the fourth operation state.

[0065] Among them, further, under the control of the first control signal group, the first switch unit S1, the third switch unit S3, and the fifth switch unit S5 of the power circuit 10 are turned on, and the second switch unit S2 and the fourth switch unit S4 are turned off to enter the first operating state; under the control of the second control signal group, the second switch unit S2 and the fourth switch unit S4 of the power circuit 10 are turned on, and the first switch unit S1, the third switch unit S3, and the fifth switch unit S5 are turned off to enter the second operating state; under the control of the third control signal group, the first switch unit S1 and the fourth switch unit S4 of the power circuit 10 are turned on, and the second switch unit S2, the third switch unit S3, and the fifth switch unit S5 are turned off to enter the third operating state; under the control of the fourth control signal group, the second switch unit S2, the third switch unit S3, and the fifth switch unit S5 of the power circuit 10 are turned on, and the first switch unit S1 and the fourth switch unit S4 are turned off to enter the fourth operating state.

[0066] Combined with Figure 2 、 Figure 6 and Figure 7 shown, taking the first operating mode as an example for illustration, Figure 2 In it, from the Ф1: DT cycle steady-state analysis of the first operating state (A), it can be seen that the DC voltage on the flying capacitor CF is equal to the output voltage of the power stage, that is, V CF = V OUT . This characteristic reflects that the structure of this application itself has the characteristic of dynamic stability of the voltage of the flying capacitor CF. Compared with the 3-level structure (a circuit with 3 voltage levels), the voltage of the flying capacitor CF in the topology of this application will not be offset by dynamic influence, ensuring better stability of the power stage. For the hard charging phenomenon between the flying capacitor CF and the output capacitor C OUT in the Ф1 state, it can be reduced by selecting appropriate capacitance values. In addition, when the V OUT voltage is low, the withstand voltage across the flying capacitor CF is also correspondingly low. For common multi-layer ceramic capacitor (MLCC) components, it is beneficial to obtain a higher capacitance density. According to Figure 6 (a) and Figure 6 (b), it can be intuitively analyzed that the steady-state withstand voltages of each switch in the Ф1 and Ф2 states are:

[0067]

[0068] Analyze the turns ratio. According to Figure 2 (A), combined with the 12 volt-second balance of the inductor, the expression of the turns ratio can be deduced as:

[0069]

[0070] Analyze the current of inductor 12, and the passing charge quantity Q of the flying capacitor CF under different switching states CF =(1 - D)TI L,DC , the steady-state current of inductor 12 can be obtained as follows:

[0071]

[0072] In the above formula, V SW1,2 is the voltage of the first switching unit S1 and the second switching unit S2, V IN is the input voltage, V SW3,4,5 is the voltage of the third switching unit S3, the fourth switching unit S4 and the fifth switching unit S5, V OUT is the output voltage, M is the turns ratio, D is the duty cycle, T is the period, I L,DC is the DC current of inductor 12, I OUT is the output current.

[0073] It can be obtained from the above formula that when the buck ratio multiple is relatively high, I L,DC approaches 0.5I OUT . Therefore, when using the same inductor 12 component, the DCR loss of inductor 12 in the power circuit 10 of the present application under the same load current is only about 25% of that of the ordinary buck and 3-level converters. The expression of the inductor 12 ripple current is as follows:

[0074]

[0075] In the formula, Δi L is the inductor current ripple, L is the inductance value of the inductor, f S is the switching operating frequency of the DC converter.

[0076] It can be seen that the change of the inductor 12 current in the circuit of the present application is greater than that of the buck structure. However, since the ripple current accounts for a relatively low proportion in the root mean square (rms) current value, the corresponding DCR loss of the inductor 12 is mainly determined by the DC part. Therefore, the topology of the present application still has an obvious inductor 12 loss advantage compared with the buck structure.

[0077] Combined with Figures 2 - 5 , by analyzing the voltages at both ends of the inductor 12 under different states, the turns ratio expressions for different state combinations can be obtained according to the volt-second balance relationship as follows:

[0078] A - B combination:

[0079] A - C combination:

[0080] A - D combination: M = D, D = M(0 < M < 1);

[0081] C-D combination:

[0082] Based on the above expressions, the A-B and A-D combinations can achieve a turns ratio range of 0 to 1; while the A-C and C-D combinations can only achieve a partial range of voltage transformation. Among them, the A-D combination is equivalent to the buck structure in terms of structure, and there is a series conduction path of switches, which will increase additional losses. For the other three states, due to different current distributions, the conduction losses within their voltage transformation ranges will vary. Under the conditions of the same input, output, and component usage, the voltage conversion efficiency and conduction losses of the four state combinations are modeled and analyzed, and the relevant simulation results are as shown in Figure 8 and Figure 9 shown.

[0083] Here, this embodiment takes the A-B combination state (i.e., the first operating mode) as an example for illustration. Referring to Figure 6 and Figure 7 , the amplitude of the inductor 12 current change in the ZVS state (i.e., the zero voltage switching state) is greater than that in the conventional hard switching mode, and Figure 7 (b) there is a current polarity reversal before and after the dead time t dd2 . The ZVS switch control principle utilized by this solution is as follows: In the first operating state Ф1, as shown in Figure 7 (a), within the dead time t dd1 , the positive inductor 12 current i L charges the parasitic capacitance of the node between the upper and lower plates of the flying capacitor CF, so that the voltage V D3 rises from V OUT at Ф1 to 2V OUT . At this time, by timely switching the switch state (i.e., the first operating state Ф1 → the second operating state Ф2), before V D3 continues to rise to 2V OUT +V dio , the conduction of the second switch unit S2 and the fourth switch unit S4 is completed, which can effectively avoid the forward biasing of the body diodes of switches S2 and S4, thereby eliminating the problem of increased switch withstand voltage within the t dd1 time. For the conversion process from the second operating state Ф2 → the first operating state Ф1, as shown in Figure 7 (b), before the converter enters the dead state, the direction of the current i L may have reversed. At this time, the inductor 12 current discharges the parasitic capacitance of the node between the upper and lower plates of the flying capacitor CF. Correspondingly, the node voltage V D3 starts to drop from 2V OUT . By accurately controlling the switch timing, the converter is made to end before V D3 drops to V OUT -V dio before tdd2 In this state, the overvoltage risk of S4 caused by the forward biasing of the body diodes of S3 and S5 can be avoided. During the switching process of the above two switch states, zero-voltage turn-on of all switches is achieved, thus solving the problem of hard-switching loss.

[0084] Furthermore, the power circuit 10 of this embodiment further includes an output capacitor C OUT , and the output capacitor C OUT 's first end is connected to the second end of the third switch unit S3, and the second end of the output capacitor C OUT is grounded. Specifically, the output capacitor C OUT smooths the output voltage through the charging and discharging process. When there are ripples or fluctuations in the input voltage, the output capacitor C OUT will absorb or release energy, thereby reducing the instantaneous change of the output voltage and making it more stable. Also, the switching action generates high-frequency noise, and the output capacitor C OUT used in conjunction with the inductor 12 can filter out these high-frequency components and improve the purity of the output signal.

[0085] Refer to Figure 10 , a DC converter provided in this embodiment includes the power circuit 10 of the above embodiment, and further includes: a voltage division and sampling module 20, a reconstruction mode selection module 30, a pulse modulation control module 40, and an adjustable dead-time clock generator 50. Among them, the voltage division and sampling module 20 is used to sample the input voltage and the output voltage; the reconstruction mode selection module 30 is used to control the output corresponding operating mode according to the voltage transformation ratio of the sampled input voltage and output voltage; the pulse modulation control module 40 is used to perform real-time linear regulation and load regulation on the output voltage and then output a clock signal; the adjustable dead-time clock generator 50 is used to generate a control signal according to the clock signal, the operating mode, and a preset bit signal and output it to the power circuit 10; the preset bit signal is used to modulate the dead-time width of the adjustable dead-time clock generator 50. Among them, the preset bit signal is b Figure 10 as shown in 0 , b 1 , b 2 , b 3 , b 4 , b 5 .

[0086] In practical applications, the adjustable dead-time clock generator 50 determines the operating mode of the DC converter based on the clock signal, the operating mode, and the preset bit signal. Specifically, the DC converter has one or more operating modes among the first operating mode, the second operating mode, the third operating mode, and the fourth operating mode. When the DC converter operates in the first operating mode, the adjustable dead-time clock generator 50 alternately outputs the first control signal group and the second control signal group to the power circuit 10, causing the power circuit 10 to alternately enter the first operating state and the second operating state; when the DC converter operates in the second operating mode, the adjustable dead-time clock generator 50 alternately outputs the first control signal group and the third control signal group to the power circuit 10, causing the power circuit 10 to alternately enter the first operating state and the third operating state; when the DC converter operates in the third operating mode, the adjustable dead-time clock generator 50 alternately outputs the first control signal group and the fourth control signal group to the power circuit 10, causing the power circuit 10 to alternately enter the first operating state and the fourth operating state; when the DC converter operates in the fourth operating mode, the adjustable dead-time clock generator 50 alternately outputs the third control signal group and the fourth control signal group to the power circuit 10, causing the power circuit 10 to alternately enter the third operating state and the fourth operating state.

[0087] Reference Figure 9 , when 0 < M ≤ 0.3, the DC converter operates in the first operating mode; when 0.3 < M ≤ 0.48, the DC converter operates in the fourth operating mode; when 0.48 < M ≤ 0.52, the DC converter operates in the first operating mode; when 0.52 < M < 1, the DC converter operates in the second operating mode; where M is the voltage conversion ratio of the DC converter. Among them, the voltage conversion ratio is calculated from the sampled output voltage and the input voltage, that is, M = V OUT / V IN .

[0088] In some embodiments, the pulse modulation control module 40 includes: an error amplifier, a comparator, and a triangular wave generator; the negative input terminal of the error amplifier is connected to the output voltage of the voltage division sampling module 20, and the positive input terminal of the error amplifier is connected to a preset reference voltage. The preset reference voltage provides a reference voltage signal, enabling the error amplifier to compare the output voltage signal with the reference voltage signal to obtain an error voltage signal, which is an analog signal. The output terminal of the error amplifier is connected to the positive input terminal of the comparator; the output terminal of the triangular wave generator is connected to the negative input terminal of the comparator, and the input terminal of the triangular wave generator is used to input the maximum and minimum values of the triangular wave signal. The triangular wave signal generator can generate a corresponding triangular wave signal based on the maximum and minimum values. The error amplifier can compare the error voltage signal with the generated triangular wave signal to obtain the reference clock signal of the DC converter, where the reference clock signal is a periodic signal with a specific duty cycle. The output terminal of the comparator is connected to the adjustable dead-time clock generator 50, and the output terminal of the adjustable dead-time clock generator 50 is electrically connected to the control terminals of the respective switching units in the power circuit 10. In the embodiments of the present application, in order to avoid short circuits, the adjustable dead-time clock generator 50 is a non-overlapping clock signal generator and can generate non-overlapping clock signals.

[0089] When the current of the electrical load changes, it will directly affect the output voltage, and the sampled voltage signal will change with the change of the output voltage. This change is compared with the reference voltage signal to obtain an error voltage signal, which can change the duty cycle of the clock signal and adjust the power circuit 10 in the form of negative feedback.

[0090] In some embodiments, the voltage division sampling module 20 includes an input voltage sampling sub-module 21 and an output voltage sampling sub-module 22; the input voltage sampling sub-module 21 includes a first voltage division resistor R1 and a second voltage division resistor R2. The first end of the first voltage division resistor R1 is connected to the power input terminal, the second end of the first voltage division resistor R1 is connected to the first end of the second voltage division resistor R2, and the second end of the second voltage division resistor R2 is grounded; the input terminal of the reconstruction mode selection module 30 is connected to the second end of the first voltage division resistor R1; the output voltage sampling sub-module 22 includes a third voltage division resistor Rf1 and a fourth voltage division resistor Rf2. The first end of the third voltage division resistor Rf1 is connected to the power output terminal, the second end of the third voltage division resistor Rf1 is connected to the first end of the fourth voltage division resistor Rf2, and the second end of the fourth voltage division resistor Rf2 is grounded; the negative input terminal of the error amplifier is connected to the second end of the third voltage division resistor Rf1.

[0091] In practical applications, according to the non-overlapping control signal group generated by the adjustable dead-time clock generator 50, the power circuit 10 in the DC converter has two operating states within one working cycle in different operating modes.

[0092] In the first operating mode, when the power circuit 10 is in the first operating state A (Ф1:DT), the first control signal group controls the first switch unit S1, the third switch unit S3, and the fifth switch unit S5 to conduct, and the second switch unit S2 and the fourth switch unit S4 are turned off; when the power circuit 10 is in the second operating state B (Ф2:(1-D)T), the second control signal group controls the second switch unit S2 and the fourth switch unit S4 to conduct, and the first switch unit S1, the third switch unit S3, and the fifth switch unit S5 are turned off.

[0093] In the second operating mode, when the power circuit 10 is in the first operating state A (Ф1:DT), the first control signal group controls the first switch unit S1, the third switch unit S3, and the fifth switch unit S5 to conduct, and the second switch unit S2 and the fourth switch unit S4 are turned off; when the power circuit 10 is in the third operating state C (Ф2:(1-D)T), the third control signal group controls the first switch unit S1 and the fourth switch unit S4 to conduct, and the second switch unit S2, the third switch unit S3, and the fifth switch unit S5 are turned off.

[0094] In the third operating mode, when the power circuit 10 is in the first operating state A (Ф1:DT), the first control signal group controls the first switch unit S1, the third switch unit S3, and the fifth switch unit S5 to conduct, and the second switch unit S2 and the fourth switch unit S4 are turned off; when the power circuit 10 is in the fourth operating state D (Ф2:(1-D)T), the fourth control signal group controls the second switch unit S2, the third switch unit S3, and the fifth switch unit S5 to conduct, and the first switch unit S1 and the fourth switch unit S4 are turned off.

[0095] In the fourth operating mode, when the power circuit 10 is in the third operating state C (Ф1:DT), the third control signal group controls the first switch unit S1 and the fourth switch unit S4 to conduct, and the second switch unit S2, the third switch unit S3, and the fifth switch unit S5 are turned off; when the power circuit 10 is in the fourth operating state D (Ф2:(1-D)T), the fourth control signal group controls the second switch unit S2, the third switch unit S3, and the fifth switch unit S5 to conduct, and the first switch unit S1 and the fourth switch unit S4 are turned off.

[0096] The DC converter proposed in this application is a two-path reconfigurable capacitor-inductor hybrid structure converter, which can achieve higher power density. At the same time, the switch state reconstruction technology can optimize the efficiency for voltage requirements under different working conditions. In addition, the converter switch control technology with quasi-resonant characteristics can further reduce the switching loss and improve the reliability of the switch, and can meet the power supply requirements of large load current, high efficiency, and accurate output voltage under different working conditions in the context of AI computing.

[0097] A power management system provided in this embodiment includes the DC converter as described above. Since the DC converter has been described in detail in the above embodiment, it will not be elaborated too much in this embodiment.

[0098] The above uses specific examples to elaborate on the present invention, which is only used to help understand the present invention and is not intended to limit the present invention. For those skilled in the technical field to which the present invention pertains, several simple deductions, deformations or substitutions can also be made according to the idea of the present invention.

Claims

1. A power circuit, characterized in that: include: Half-bridge switch modules, inductor and single capacitor switch modules; The input end of the half-bridge switch module is connected to the power input end, and the output end of the half-bridge switch module is connected to the first end of the inductor; The second end of the inductor is connected to the input end of the single capacitor switch module, and the output end of the single capacitor switch module is connected to the output end of the power supply; The half-bridge switch module is used to control the charging and discharging of the inductor according to a control signal; the single capacitor switch module is used to reduce the current of the inductor under the control of the control signal to reduce the DCR loss of the inductor.

2. The power circuit according to claim 1, characterized in that: The half-bridge switch module includes a first switch unit and a second switch unit, and the single capacitor switch module includes a third switch unit, a fourth switch unit, a fifth switch unit and a flying capacitor; The first end of the inductor is connected to the power input end through the first switch unit, and the second end of the inductor is connected to the power output end through the third switch unit; the first end of the second switch unit is connected to the first end of the inductor, and the second end of the second switch unit is grounded; The first end of the flying capacitor is connected to the second end of the inductor, the second end of the flying capacitor is grounded through the fifth switch unit, and the second end of the flying capacitor is also connected to the power output end through the fourth switch unit.

3. The power circuit according to claim 2, characterized in that: Under the control of the first control signal group, the first switch unit, the third switch unit and the fifth switch unit are turned on, and the second switch unit and the fourth switch unit are turned off, so as to enter the first operating state; Under the control of the second control signal group, the second switch unit and the fourth switch unit are turned on, and the first switch unit, the third switch unit and the fifth switch unit are turned off, so as to enter the second operation state; Under the control of the third control signal group, the first switch unit and the fourth switch unit are turned on, and the second switch unit, the third switch unit and the fifth switch unit are turned off, so as to enter the third operation state; Under the control of the fourth control signal group, the second switch unit, the third switch unit and the fifth switch unit are turned on, and the first switch unit and the fourth switch unit are turned off, so as to enter the fourth operation state.

4. The power circuit according to claim 3, characterized in that: The power circuit has one or more operating modes of a first operating mode, a second operating mode, a third operating mode and a fourth operating mode; When the power circuit receives the first control signal group and the second control signal group alternately, it operates in the first operation mode and alternately enters the first operation state and the second operation state; When the power circuit receives the first control signal group and the third control signal group alternately, it operates in the second operation mode and alternately enters the first operation state and the third operation state; When the power circuit receives the first control signal group and the fourth control signal group alternately, it operates in the third operation mode and alternately enters the first operation state and the fourth operation state; When the power circuit receives the third control signal group and the fourth control signal group alternately, it operates in the fourth operation mode and alternately enters the third operation state and the fourth operation state.

5. The power circuit according to claim 3, characterized in that: The power circuit further includes an output capacitor, a first end of the output capacitor is connected to the second end of the third switch unit, and a second end of the output capacitor is grounded.

6. A DC converter, characterized in that: The power circuit according to any one of claims 1 to 5, further comprising: a voltage division sampling module, a reconstruction mode selection module, a pulse modulation control module and an adjustable dead time clock generator; The voltage division sampling module is used to sample input voltage and output voltage; The reconstruction mode selection module is used to control the operation mode corresponding to the output according to the transformation ratio of the sampled input voltage and output voltage; The pulse modulation control module is used to output a clock signal after performing real-time linear regulation and load regulation on the output voltage; The adjustable dead time clock generator is used to generate a control signal according to the clock signal, the operation mode and the preset bit signal and output it to the power circuit; the preset bit signal is used to modulate the dead time width of the adjustable dead time clock generator.

7. The DC converter according to claim 6, characterized in that: The DC converter has one or more operating modes of a first operating mode, a second operating mode, a third operating mode and a fourth operating mode; When the DC converter operates in the first operating mode, the adjustable dead time clock generator alternately outputs a first control signal group and a second control signal group to the power circuit, so that the power circuit alternately enters a first operating state and a second operating state; When the DC converter operates in the second operation mode, the adjustable dead time clock generator alternately outputs the first control signal group and the third control signal group to the power circuit, so that the power circuit alternately enters the first operation state and the third operation state; When the DC converter operates in the third operation mode, the adjustable dead time clock generator alternately outputs the first control signal group and the fourth control signal group to the power circuit, so that the power circuit alternately enters the first operation state and the fourth operation state; When the DC converter operates in the fourth operating mode, the adjustable dead time clock generator alternately outputs the third control signal group and the fourth control signal group to the power circuit, so that the power circuit alternately enters the third operating state and the fourth operating state.

8. The DC converter according to claim 7, characterized in that: When 0<M≤0.3, the DC converter operates in the first operating mode; when 0.3<M≤0.48, the DC converter operates in the fourth operating mode; when 0.48<M≤0.52, the DC converter operates in the first operating mode; when 0.52<M<1, the DC converter operates in the second operating mode; wherein M is the transformation ratio of the DC converter.

9. The DC converter according to claim 7, characterized in that: The voltage division sampling module includes an input voltage sampling submodule and an output voltage sampling submodule; The input voltage sampling submodule comprises a first voltage-dividing resistor and a second voltage-dividing resistor, wherein the first end of the first voltage-dividing resistor is connected to the power input end, the second end of the first voltage-dividing resistor is connected to the first end of the second voltage-dividing resistor, and the second end of the second voltage-dividing resistor is grounded; the input end of the reconstruction mode selection module is connected to the second end of the first voltage-dividing resistor; The output voltage sampling submodule includes a third voltage-dividing resistor and a fourth voltage-dividing resistor, the first end of the third voltage-dividing resistor is connected to the power supply output end, the second end of the third voltage-dividing resistor is connected to the first end of the fourth voltage-dividing resistor, and the second end of the fourth voltage-dividing resistor is grounded; the negative input end of the error amplifier is connected to the second end of the third voltage-dividing resistor.

10. A power management system, characterized in that: Comprising a DC converter as claimed in any one of claims 6 to 9.

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