Boost control circuit

Abstract

The invention relates to the technical field of boost control, in particular to a boost control circuit which comprises a driving circuit and a power circuit, the driving circuit comprises a chip U1 and a chip U2, a pin 1 of the chip U1 is grounded through a voltage source V5, a pin 2 of the chip U1 is coupled with a resistor R2, the resistor R2 is grounded through a voltage source V3, a pin 4 of the chip U1 is grounded through a power supply V2, a pin 9 of the chip U1 is coupled with a pin 4 of the chip U2, and a pin 9 of the chip U2 is coupled with a pin 9 of the chip U2. Pins 12 and 16 of the chip U1 are coupled with pins 12 and 16 of the chip U2 and then are grounded through a voltage source V4, and a pin 15 of the chip U1 is coupled with an MOS tube M5; modeling simulation is carried out on the boost control circuit through PSPice software, feasibility and superiority of the scheme are proved, transient simulation analysis is carried out on an inductor in the circuit, the working state and current and voltage values of the inductor are verified, and the result shows that compared with a traditional boost circuit, the boost control circuit has the advantages of being simple in structure and convenient to use. The boost control circuit provided by the invention has better stability and higher control precision.

Description

Technical Field

[0001] The present invention relates to the technical field of boost control circuits, and particularly to a boost control circuit. Background Art

[0002] As a simple and efficient DC-DC converter, the boost circuit has a wide range of applications. For example, researchers at home and abroad have conducted extensive research on the soft-switching technology of DC-DC converters to solve the problem of switching losses. Among them, more use resonant soft switches as switching devices. The existing boost circuits mainly include the following categories:

[0003] 1. Soft-switching quadratic Boost high-gain converter. This type of Boost high-gain converter is based on an auxiliary network. The zero-voltage turn-on of all switching devices and the zero-current turn-off of output diodes are achieved by introducing a series auxiliary network unit to reduce the switching losses of switching devices. However, the circuit needs to operate in the current discontinuous mode, resulting in low efficiency.

[0004] 2. Coupled interleaved parallel Boost circuit, which can achieve zero-current turn-on within a wide input voltage range, but the circuit still has hard turn-off, and the efficiency improvement is not obvious.

[0005] 3. Resonant clamping auxiliary circuit, which introduces resonant elements on the basis of the interleaved parallel Boost circuit. Both the main circuit and the auxiliary circuit achieve zero-current switching. However, the circuit introduces too many auxiliary elements, the control is complex, and the conditions for realizing soft switching are relatively harsh.

[0006] Therefore, this application proposes a boost control circuit to solve the above problems. Summary of the Invention

[0007] Aiming at the deficiencies of the prior art, the present invention provides a boost control circuit to solve the technical problems in the prior art that "the existing boost circuits mainly include the following categories: soft-switching quadratic Boost high-gain converter. This type of Boost high-gain converter is based on an auxiliary network. The zero-voltage turn-on of all switching devices and the zero-current turn-off of output diodes are achieved by introducing a series auxiliary network unit to reduce the switching losses of switching devices. However, the circuit needs to operate in the current discontinuous mode, resulting in low efficiency. Coupled interleaved parallel Boost circuit, which can achieve zero-current turn-on within a wide input voltage range, but the circuit still has hard turn-off, and the efficiency improvement is not obvious. Resonant clamping auxiliary circuit, which introduces resonant elements on the basis of the interleaved parallel Boost circuit. Both the main circuit and the auxiliary circuit achieve zero-current switching. However, the circuit introduces too many auxiliary elements, the control is complex, and the conditions for realizing soft switching are relatively harsh".

[0008] To achieve the above objectives, the present invention is realized through the following technical solutions:

[0009] A boost control circuit, a drive circuit, and a power circuit

[0010] The drive circuit includes chips U1 and U2. Pin 1 of chip U1 is grounded through voltage source V5, pin 2 is coupled with resistor R2, resistor R2 is grounded through voltage source V3, and pin 4 is grounded through power supply V2;

[0011] Pin 9 of chip U1 is coupled with pin 4 of chip U2, and pins 12 and 16 of chip U1 are coupled with pins 12 and 16 of chip U2 and then grounded through voltage source V4;

[0012] Pin 15 of chip U1 is coupled with MOS transistor M5. The source of MOS transistor M5 is serially connected with capacitors C4, C3, and resistor R8 respectively, and capacitors C4, C3, and resistor R8 are connected in parallel and then grounded;

[0013] The drain of MOS transistor M5 is coupled with voltage source V5 through inductor L1;

[0014] Pin 1 of chip U2 is grounded through voltage source V1. Pin 2 of chip U2 is coupled with voltage source V3 through resistor R1 and then grounded. Pin 4 of chip U2 is coupled with voltage source V2 and then grounded;

[0015] Pin 15 of chip U2 is coupled with MOS transistor M4, and the drain of MOS transistor M4 is coupled with the drain of MOS transistor M5.

[0016] As a preferred technical solution of the present invention, the voltage difference between pin 4 and pin 9 of chip U2 is 3V

[0017] As a preferred technical solution of the present invention, the source of MOS transistor M4 is respectively coupled with capacitors C4, C3, and resistor R8 and then grounded.

[0018] As a preferred technical solution of the present invention, chips U1 and U2 are drive chips for MOS transistors M4 and M5.

[0019] As a preferred technical solution of the present invention, the drive circuit amplifies the PWM signal from the upper-level FPGA main controller through an external power supply to drive MOS transistors M4 and M5 to operate.

[0020] As a preferred technical solution of the present invention, the power circuit includes an inductor L, a capacitor C, NMOS transistors, PMOS transistors, and an auxiliary power supply circuit.

[0021] As a preferred technical solution of the present invention, the power circuit realizes the energy conversion between the input and the output through capacitor C, inductor L, and MOSFET switching transistors.

[0022] As a preferred technical solution of the present invention, the auxiliary power supply circuit is used to generate 7V and -3V voltages to supply power to the drive circuit.

[0023] The present invention provides a boost control circuit, which has the following beneficial effects:

[0024] 1. The boost control circuit of the present invention is modeled and simulated by using PSpice software, which proves the feasibility and superiority of the solution of the present invention. Then, the inductor in the circuit is analyzed by transient simulation to verify its working state and current and voltage values. The results show that, compared with the traditional boost circuit, the boost control circuit of the present application invention has better stability and higher control accuracy;

[0025] 2. In the invented boost control circuit, U1 and U2 are the drive chips of MOS transistors M4 and M5. The Spice model file is imported from the outside for modeling. According to its electrical parameters, +7V and -3V are used as the drive voltages. In the circuit, MOS switch transistors M4 and M5 are used to replace a rectifier diode to reduce the conduction loss, which can improve the efficiency of the boost circuit and eliminate the dead zone voltage caused by the Schottky barrier voltage existing in the traditional Schottky diode;

[0026] 3. The drive circuit in the boost circuit of the present invention is a power amplifier, which realizes the energy conversion between the input and the output through the capacitor C, inductor L, NMOS transistor and PMOS transistor, and the external power supply amplifies the PWM signal from the upper-level FPGA main controller to drive the operation of the NMOS transistor and PMOS transistor. Description of the Drawings

[0027] Figure 1 It is a working flow block diagram of a boost control circuit proposed by the present invention;

[0028] Figure 2 It is a circuit diagram of a boost control circuit proposed by the present invention;

[0029] Figure 3 It is a power circuit diagram in a boost control circuit proposed by the present invention;

[0030] Figure 4 It is a PWM drive signal waveform of MOS transistor M4 in a boost control circuit proposed by the present invention;

[0031] Figure 5 It is a PWM drive signal waveform of MOS transistor M5 in a boost control circuit proposed by the present invention;

[0032] Figure 6 It is a simulation diagram of the output voltage of a traditional boost circuit;

[0033] Figure 7The simulation diagram of the output voltage of a boost control circuit proposed by the present invention;

[0034] Figure 8 The transient simulation waveform diagram of the current of inductor L1 in a boost control circuit proposed by the present invention;

[0035] Figure 9 The transient simulation waveform diagram of the voltage of inductor L1 in a boost control circuit proposed by the present invention;

[0036] Figure 10 The transient simulation waveform diagram of the power of inductor L1 in a boost control circuit proposed by the present invention;

[0037] Figure 11 The waveform diagram of the load power in a boost control circuit proposed by the present invention. Detailed implementation manners

[0038] To facilitate the understanding of the present invention, the present invention will be described in more detail below in conjunction with the drawings and specific implementation manners. It should be noted that when an element is expressed as "coupled" to another element, it can be directly on the other element, or there can be one or more intermediate elements therebetween. When an element is expressed as "electrically connected" to another element, it can be directly connected to the other element, or there can be one or more intermediate elements therebetween. The terms "vertical", "horizontal", "left", "right" and similar expressions used in this specification are only for the purpose of illustration.

[0039] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in this specification in the description of the present invention are only for the purpose of describing specific implementation manners and are not used to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items.

[0040] The principle and structure of the present invention will be described in detail below in conjunction with the drawings and embodiments:

[0041] Embodiment:

[0042] Reference Figures 1-11 , a boost control circuit, including a drive circuit and a power circuit.

[0043] The drive circuit includes chip U1 and chip U2. Pin 1 of chip U1 is grounded through voltage source V5, pin 2 is coupled with resistor R2, resistor R2 is grounded through voltage source V3, pin 4 is grounded through power supply V2. The drive circuit amplifies the PWM signal from the upper-level FPGA main controller through an external power supply to drive MOS transistors M4 and M5 to operate;

[0044] The chips U1 and U2 are the driver chips of the MOS transistors M4 and M5. Pin 9 of chip U1 is coupled to pin 4 of chip U2. Pins 12 and 16 of chip U1 are coupled to pins 12 and 16 of chip U2 and then grounded through the voltage source V4. Pin 15 of chip U1 is coupled to the MOS transistor M5. The drain of the MOS transistor M5 is coupled to the voltage source V5 through the inductor L1. The source of the MOS transistor M5 is respectively connected in series with the capacitors C4, C3 and the resistor R8. The capacitors C4, C3 and the resistor R8 are connected in parallel and then grounded;

[0045] Pin 1 of chip U2 is grounded through the voltage source V1. Pin 2 of the chip U2 is grounded through the resistor R1 and then coupled to the voltage source V3. Pin 4 of the chip U2 is grounded after being coupled to the voltage source V2. Pin 15 of chip U2 is coupled to the MOS transistor M4. The drain of the MOS transistor M4 is coupled to the drain of the MOS transistor M5. The voltage difference between pin 4 and pin 9 of chip U2 is 3V. The source of the MOS transistor M4 is respectively coupled to the capacitors C4, C3 and the resistor R8 and then grounded.

[0046] The power circuit includes an inductor L, a capacitor C, an NMOS transistor, a PMOS transistor and an auxiliary power supply circuit. The power circuit realizes the energy conversion between the input and the output through the capacitor C, the inductor L and the MOSFET switch transistor. The auxiliary power supply circuit is used to generate 7V and -3V voltages to supply power to the drive circuit.

[0047] Specifically,

[0048] Refer to Figure 1 As shown, the boost circuit in the present invention is a DC-DC converter, which can realize the conversion from a low input voltage to a high output voltage. Its switching control can be achieved by two methods. One is based on the PWM technology, that is, the pulse period remains unchanged, and the output voltage value is regulated by changing the duty cycle of the switching time; the other is based on the PFM (Pulse frequency modulation) technology, that is, the switching time is kept as a fixed value, and the period of the pulse is regulated;

[0049] Refer to Figure 2 As shown, it is the boost control circuit diagram of the present invention. Among them, U1 and U2 are the driver chips of the MOS transistors M4 and M5. The Spice model file is imported from the outside for modeling. According to its electrical parameters, +7V and -3V are used as the drive voltages. In the circuit, the MOS switch transistors M4 and M5 are used to replace a rectifier diode to reduce the conduction loss, improve the efficiency of the boost circuit, and eliminate the dead zone voltage caused by the Schottky barrier voltage existing in the traditional Schottky diode;

[0050] Refer to Figure 3As shown in the figure, it is the power circuit diagram of the boost circuit of the present invention, which includes an inductor L, a capacitor C, an NMOS transistor, a PMOS transistor, and their respective driving circuits (Driver), and realizes the energy conversion between the input and the output through the capacitor C, the inductor L, the NMOS transistor, and the PMOS transistor.

[0051] Among them, the driving circuit is a power amplifier, which amplifies the PWM signal from the upper-level FPGA main controller through an external power supply to drive the operation of the NMOS transistor and the PMOS transistor.

[0052] Reference Figure 4 、 5 As shown in the figure, it is the PWM driving waveform diagram applied to the MOS transistor M4 and the MOS transistor M5 of the present invention;

[0053] Reference Figure 6 As shown in the figure, it is the output voltage simulation result diagram of the traditional boost circuit. It can be seen from the figure that although the rising curve of the output voltage is relatively fast, the transient output voltage is relatively high, which is easy to break down the load circuit, and the fluctuation amplitude is relatively large after reaching the highest output voltage value at 1.6 ms, and its stability is poor.

[0054] Reference Figure 7 As shown in the figure, it is the output voltage simulation result diagram of the boost circuit of the present invention. It can be seen from the figure that the rising curve of the voltage is smoother and more stable more quickly. Near the expected voltage value, there is no obvious fluctuation after reaching the expected voltage at 1.6 ms, and its stability is good.

[0055] Reference Figure 8 、 9 As shown in Figures 、10, based on the PSpice software, a transient analysis of the boost control circuit is carried out, which respectively shows the waveforms of the current, voltage, and power of the inductor L1, and the inductor L1 outputs stably.

[0056] The boost control circuit of the present invention is modeled and simulated by using the PSpice software, which proves the feasibility and superiority of the solution of the present invention. Then, a transient simulation analysis of the inductor in the circuit is carried out to verify its working state and the current and voltage values. The results show that, compared with the traditional boost circuit, the boost control circuit of the present application invention has better stability and higher control accuracy.

[0057] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A boost control circuit, characterized in that: Drive circuit and power circuit, The driving circuit includes a chip U1 and a chip U2, wherein the pin 1 of the chip U1 is grounded via a voltage source V5, the pin 2 is coupled to a resistor R2, the resistor R2 is grounded via a voltage source V3, and the pin 4 is grounded via a power source V2; The pin 9 of the chip U1 is coupled to the pin 4 of the chip U2, and the pins 12 and 16 of the chip U1 are coupled to the pins 12 and 16 of the chip U2 and then grounded via the voltage source V4; The pin 15 of the chip U1 is coupled to a MOS tube M5, the source of the MOS tube M5 is respectively connected in series with capacitors C4, C3 and a resistor R8, and the capacitors C4, C3 and the resistor R8 are connected in parallel and then grounded; The drain of the MOS tube M5 is coupled to the voltage source V5 via the inductor L1; Pin 1 of the chip U2 is grounded via a voltage source V1, pin 2 of the chip U2 is grounded via a resistor R1 and coupled to a voltage source V3, and pin 4 of the chip U2 is grounded after being coupled to a voltage source V2; The pin 15 of the chip U2 is coupled to a MOS tube M4 , and the drain of the MOS tube M4 is coupled to the drain of the MOS tube M5 .

2. A boost control circuit according to claim 1, characterized in that: The voltage difference between pin 4 and pin 9 of chip U2 is 3V.

3. A boost control circuit according to claim 1, characterized in that: The source of the MOS tube M4 is coupled to the capacitors C4, C3 and the resistor R8 respectively and then grounded.

4. A boost control circuit according to claim 1, characterized in that: The chips U1 and U2 are driving chips of the MOS tubes M4 and M5.

5. A boost control circuit according to claim 1, characterized in that: The driving circuit amplifies the PWM signal from the upper-level FPGA main controller through an external power supply to drive the MOS tubes M4 and M5 to operate.

6. A boost control circuit according to claim 1, characterized in that: The power circuit includes an inductor L, a capacitor C, an NMOS tube and a PMOS tube and an auxiliary power supply circuit.

7. A boost control circuit according to claim 6, characterized in that: The power circuit realizes energy conversion between input and output through capacitor C, inductor L and MOSFET switch tube.

8. A boost control circuit according to claim 6, characterized in that: The auxiliary power supply circuit is used to generate 7V and -3V voltages to power the drive circuit.

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