A complementary inverse class-f voltage-controlled oscillator and its nested voltage-controlled oscillator

Abstract

This invention discloses a complementary inverse F-type voltage-controlled oscillator and its nested type, mainly addressing the problems of large footprint or high cost of existing oscillators. The oscillator consists of two identical active cores A1 and A2, each containing a pair of complementary NMOS and PMOS transistors, with a drain capacitor C connected between the drains of the NMOS and PMOS transistors. D A gate capacitor C is connected between the gates of the NMOS and PMOS transistors. G The two active cores are interconnected via four transformers. The complementary inverse Class-F voltage-controlled oscillator proposed in this invention achieves wide bandwidth coverage, high performance, and low phase noise at high frequencies. By utilizing inductor nesting in basic units, it greatly reduces the problem of excessive area occupation of multi-core oscillators, meets the requirements of small chip size and low cost, and exhibits good performance consistency over a wide bandwidth.

Description

Technical Field

[0001] This invention relates to a voltage-controlled oscillator, and more specifically, to a complementary inverse F-type voltage-controlled oscillator and its nested type. Background Technology

[0002] An oscillator is a device that converts DC to AC signal output without external excitation. It possesses positive feedback and a certain gain to overcome losses in the circuit feedback path, thus generating a self-sustaining, stable oscillation signal. Voltage-controlled oscillators (VCOs), as a major type of oscillator, are used in modules such as phase-locked loops (PLLs) and clock recovery circuits, and are one of the core modules of wireless communication systems. Figure 1 As shown in (a), the oscillator can be divided into an active circuit and a resonant circuit. The negative resistance generated by the active circuit at the bottom cancels out the resistance generated by the resonant circuit, thus replenishing the energy loss in the resonant circuit. Therefore, when the oscillator oscillates stably, it achieves... Figure 1 (b) shows the stable output at the f0 resonant point.

[0003] As the heart of carrier generation in a frequency source, the oscillator plays a crucial role in multi-standard system design, influencing the overall performance of the frequency source system in key metrics such as phase noise, FoM (oscillator figure of merit), power consumption, area, frequency coverage, and frequency stability. The design of the frequency source architecture also plays a decisive role in in-band noise, frequency modulation accuracy, and system complexity. However, building a system configurable for different frequency bands and system requirements in the millimeter-wave band is extremely challenging, often facing strict design trade-offs between performance and bandwidth, as well as the problem of overly complex frequency source systems.

[0004] like Figure 2 The diagram shows an existing switched-inductor LC oscillator. Switched-inductor technology utilizes a switch to select the inductance value, thereby achieving frequency tuning and switching. This method can achieve a wide frequency coverage and has the following advantages: (1) wide frequency coverage; (2) simple design and relatively small footprint. However, the introduction of the switch's on-resistance degrades the inductance quality factor, which is more pronounced at high frequencies. Therefore, its performance is limited at high frequencies, and phase noise deteriorates significantly at higher frequencies, making it difficult to use in high-frequency applications.

[0005] like Figure 3 The existing schematic diagram shows a switch-coupled transformer LC oscillator. The switch-coupled transformer indirectly controls the change in the primary inductance value by introducing a switch into the secondary inductor, thereby reducing the impact of the switch's on-resistance on the quality factor and providing a relatively wide frequency modulation range. However, the excessive inductance windings of this oscillator often occupy too much area, increasing both cost and design complexity.

[0006] like Figure 4 The diagram shows an existing multi-core switching LC oscillator. This approach designs several oscillators with different frequencies and selects oscillators operating in different frequency bands for output, thereby achieving wide bandwidth coverage while reducing the impact of switching on the resonant circuit. However, since multiple oscillators are designed independently, each oscillator occupies an independent inductor area, which is often too large, leading to increased power consumption, complex circuit design, and a series of other problems.

[0007] like Figure 5 The diagram shows a schematic of an existing mode-switching LC oscillator. It utilizes a multi-stage resonator to generate multiple resonant frequencies, which are selected via an odd-even mode switch. In any mode, the switch only affects the unwanted resonant frequencies, thus not degrading the quality factor of the selected mode. However, the inherent performance differences between different modes of a mode-switching oscillator are often significant, resulting in poor performance consistency. Due to its complex inductive coupling method, some phase noise optimization techniques, such as waveform shaping, are difficult to apply to mode-switching oscillators, thus limiting their overall performance. Summary of the Invention

[0008] The purpose of this invention is to provide a complementary inverse F-type voltage-controlled oscillator and its nested type, which mainly solves the problems of existing oscillators having large footprints or high costs.

[0009] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0010] A complementary inverse Class-F voltage-controlled oscillator consists of two identical active cores A1 and A2. Each active core contains a pair of complementary NMOS and PMOS transistors, with a drain capacitor C connected between the drains of the NMOS and PMOS transistors. D A gate capacitor C is connected between the gates of the NMOS and PMOS transistors. GThe two active cores are interconnected via four transformers, designated F1, F2, F3, and F4. The primary winding terminal of transformer F1 is connected to the drain of the NMOS transistor in active core A1, and the secondary winding terminal of F1 is connected to the gate of the PMOS transistor in active core A1. Similarly, the primary winding terminal of transformer F2 is connected to the drain of the PMOS transistor in active core A1, and the secondary winding terminal of F2 is connected to the gate of the NMOS transistor in active core A1. The primary winding terminal of transformer F3 is connected to the drain of the NMOS transistor in active core A2, and the secondary winding terminal of F3 is connected to the gate of the PMOS transistor in active core A2. The gates of the MOS transistors are connected; the same-name terminal of the main winding of transformer F4 is connected to the drain of the PMOS transistor in active core A2, and the same-name terminal of the secondary winding of transformer F4 is connected to the gate of the NMOS transistor in active core A2; the opposite-name terminals of the main windings and the opposite-name terminals of the secondary windings of transformers F1 and F4 are connected accordingly; the opposite-name terminals of the main windings and the opposite-name terminals of the secondary windings of transformers F2 and F3 are connected accordingly; a capacitor or resistor is connected between the opposite-name terminals of the main winding and the opposite-name terminals of the secondary winding of transformer F1; a capacitor or resistor is connected between the opposite-name terminals of the main winding and the opposite-name terminals of the secondary winding of transformer F2; a capacitor or resistor is connected between the opposite-name terminals of the secondary windings of transformer F1 and the opposite-name terminals of the secondary winding of transformer F2.

[0011] Furthermore, in this invention, the drain capacitor C D or gate capacitance C G One or more of the following can be used: fixed capacitor, varactor diode, or switched capacitor.

[0012] Furthermore, in this invention, the active cores A1 and A2 are complementary double-junction transistors or complementary field-effect transistors.

[0013] Based on the above structure, the present invention also provides a complementary inverse F-class voltage-controlled oscillator based on inductor nesting, which is made by using two complementary inverse F-class voltage-controlled oscillators with different frequencies.

[0014] Furthermore, in this invention, two complementary inverse F-class voltage-controlled oscillators of different frequencies are placed orthogonally.

[0015] Furthermore, in this invention, one of the two complementary inverse F-class voltage-controlled oscillators with different frequencies is designed in a figure-eight shape, while the other is designed in a ring shape, and the two different oscillators are placed vertically.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] (1) The complementary inverse F-class voltage-controlled oscillator proposed in this invention achieves wide bandwidth coverage, high performance and low phase noise at high frequency. By using basic units for inductor nesting, the problem of large area occupation of multi-core oscillators is greatly reduced, which meets the requirements of small chip size and low cost, and has good performance consistency at wide bandwidth.

[0018] (2) The complementary inverse F-class waveform shaping technique used in this invention has a voltage waveform of half-sine wave and a current waveform of square wave. By using the second harmonic for waveform shaping, the sensitivity of the oscillator phase noise to noise is reduced, thereby reducing phase noise.

[0019] (3) The inductor implemented using this invention also has a high quality factor, further reducing phase noise and improving overall performance, which is beneficial for high-frequency applications. By placing the power supply layout outside the resonator, parasitic crosstalk of the power supply is reduced.

[0020] (4) Compared with the performance of traditional oscillators, this invention improves the output frequency range while still maintaining excellent phase noise and good performance consistency. This invention has advantages in overall performance and manufacturing cost. Attached Figure Description

[0021] Figure 1 (a) is a schematic diagram of an existing oscillator structure.

[0022] Figure 1 (b) is a schematic diagram of the resonant point of an existing oscillator.

[0023] Figure 2 This is a schematic diagram of an existing switched inductor LC oscillator.

[0024] Figure 3 This is a schematic diagram of an existing switch-coupled transformer LC oscillator.

[0025] Figure 4 This is a schematic diagram of an existing multi-core switching LC oscillator.

[0026] Figure 5 This is a schematic diagram of an existing mode-switching LC oscillator.

[0027] Figure 6 This invention relates to a complementary inverse F-class voltage-controlled oscillator.

[0028] Figure 7 This is a schematic diagram illustrating the parallel, nested, and coupled operations of the F-type voltage-controlled oscillator in an embodiment of the present invention.

[0029] Figure 8 This is the capacitor implementation of the complementary inverse F-class voltage-controlled oscillator of the present invention.

[0030] Figure 9 This invention presents an active core implementation of a complementary inverse F-class voltage-controlled oscillator based on area reuse.

[0031] Figure 10 The present invention is based on the implementation principle of a complementary inverse F-type voltage-controlled oscillator with nested inductors.

[0032] Figure 11 This is a specific implementation of the present invention based on a complementary inverse F-type voltage-controlled oscillator with nested inductors.

[0033] Figure 12 This is a schematic diagram of the inductor nesting technology mechanism in this invention. Detailed Implementation

[0034] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0035] Example 1

[0036] like Figure 6 As shown, the present invention discloses a complementary inverse F-class voltage-controlled oscillator, which consists of two identical active cores A1 and A2. Each active core contains a pair of complementary NMOS transistors and PMOS transistors, and a drain capacitor C is connected between the drains of the NMOS transistors and PMOS transistors. D A gate capacitor C is connected between the gates of the NMOS and PMOS transistors. G The two active cores are interconnected via four transformers; these four transformers are designated F1, F2, F3, and F4, respectively. The main winding of transformer F1 (i.e., Figure 6 L in D The same-named terminal of the transformer F1 is connected to the drain of the NMOS transistor in the active core A1, and the secondary winding of the transformer F1 (i.e. Figure 6 L in GThe same-name terminal of transformer F1 is connected to the gate of the PMOS transistor in active core A1; the same-name terminal of the main winding of transformer F2 is connected to the drain of the PMOS transistor in active core A1, and the same-name terminal of the secondary winding of transformer F2 is connected to the gate of the NMOS transistor in active core A1; the same-name terminal of the main winding of transformer F3 is connected to the drain of the NMOS transistor in active core A2, and the same-name terminal of the secondary winding of transformer F3 is connected to the gate of the PMOS transistor in active core A2; the same-name terminal of the main winding of transformer F4 is connected to the gate of the PMOS transistor in active core A2. The drains of the PMOS transistors in core A2 are connected, and the same-name terminal of the secondary winding of transformer F4 is connected to the gate of the NMOS transistor in active core A2; the opposite-name terminals of the primary and secondary windings of transformers F1 and F4 are connected accordingly; the opposite-name terminals of the primary and secondary windings of transformers F2 and F3 are connected accordingly; a capacitor or resistor is connected between the opposite-name terminals of the primary and secondary windings of transformer F1; a capacitor or resistor is connected between the opposite-name terminals of the primary and secondary windings of transformer F2 (i.e., Figure 6 (Components in the circuit); A capacitor or resistor is connected between the opposite terminals of the secondary winding of transformer F1 and the opposite terminals of the secondary winding of transformer F2. Compared with the traditional inverse class F oscillator, this design uses a transformer with a 1:1 turns ratio and co-coupled in the same direction, which can achieve a high Q value at a higher frequency, thus obtaining better performance and meeting the requirements of high-frequency design.

[0037] It employs inverse F-class waveform shaping technology, using second harmonics for waveform shaping, thereby achieving low phase noise and high performance. Figure 6 A schematic diagram of a complementary inverse F-class voltage-controlled oscillator based on area reuse is shown, which constitutes a basic unit.

[0038] By juxtaposing, nesting, or coupling different basic units, bandwidth can be further broadened and overall performance improved, such as... Figure 7 As shown.

[0039] By nesting two voltage-controlled oscillators of different frequencies, the inductors of the two oscillators share the same area, unlike traditional multi-core switching oscillators. Figure 4 Compared to traditional mode-switching oscillators, this significantly reduces circuit size and chip cost. The two oscillators can also be optimized independently, unlike traditional mode-switching oscillators. Figure 5 Compared to previous models, this significantly improves the broadband performance consistency of the oscillator. It meets the requirements of broadband high performance, low phase noise, small chip size, and good performance consistency.

[0040] Example 2

[0041] Based on Example 1, the gate capacitor (C) in this invention G ) and drain capacitance (CD ) are respectively connected to the gate and drain sides of the active core, such as Figure 8 As shown, this oscillator adjusts its output frequency by controlling the changes in the gate and drain capacitances. The capacitors can be implemented using fixed capacitors, varactor diodes, or switched capacitors. By adjusting the number and size of the capacitor banks, different frequency tuning ranges can be achieved, thus enabling continuous coverage of the oscillator's output frequency. Adjusting the ratio of the gate and drain capacitances ensures the accuracy of the second harmonic frequency.

[0042] Example 3

[0043] Based on Example 1, the active core implementation of the complementary inverse F-type voltage-controlled oscillator based on area reuse is as follows: Figure 9 As shown. A complementary double-junction transistor or a complementary field-effect transistor is used to provide negative resistance; different active cores can be used depending on the specific requirements.

[0044] Example 4

[0045] Based on Example 1, the extended implementation of the complementary inverse F-type voltage-controlled oscillator based on inductor nesting is as follows: Figure 10 As shown, the two oscillators operate at different frequencies: oscillator A operates at a low frequency, and oscillator B operates at a high frequency, thus improving the frequency coverage. The two oscillators, operating at different frequencies, are placed orthogonally and possess native isolation. This allows the different oscillator inductors to share the same area, reducing chip size and cost. The nesting mechanism is as follows... Figure 12 As shown in the figure, this diagram illustrates the principle of inductor nesting technology, demonstrating the current direction in four different resonant modes and the magnetic field distribution generated under each mode. The magnetic fields generated by the harmonics of different modes in each oscillator do not produce magnetic flux to the other oscillator, thus achieving mutual isolation of multi-order resonances between different oscillators.

[0046] Figure 11 This paper demonstrates the layout implementation of a complementary inverse Class-F voltage-controlled oscillator based on nested inductors. By employing a figure-eight design for one oscillator and a ring design for the other, and placing the two oscillators perpendicularly, independent and isolated operation is achieved. Within the same oscillator, the midpoints of the inductors are connected by resistors to suppress unwanted modes and ensure stable operation. The power supply layout is located outside the resonant cavity, simplifying the power supply layout and avoiding the parasitic effects of power supply traces on the oscillator resonant cavity. The two oscillators can be independently optimized, significantly improving the broadband performance consistency compared to traditional mode-switching oscillators. This approach meets the requirements of wideband performance, low phase noise, small chip size, and good performance consistency.

[0047] The above embodiments are merely one of the preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but solve the same technical problem as the present invention, should be included within the scope of protection of the present invention.

Claims

1. A complementary inverse F-type voltage-controlled oscillator, characterized in that, It consists of two identical active cores A1 and A2. Each active core contains a pair of complementary NMOS and PMOS transistors, with a drain capacitor C connected between the drains of the NMOS and PMOS transistors. D A gate capacitor C is connected between the gates of the NMOS and PMOS transistors. G The two active cores are interconnected via four transformers, designated F1, F2, F3, and F4. The primary winding of transformer F1 is connected to the drain of the PMOS transistor in active core A1, and the secondary winding of F1 is connected to the gate of the NMOS transistor in active core A1. Similarly, the primary winding of transformer F2 is connected to the drain of the NMOS transistor in active core A1, and the secondary winding of F2 is connected to the gate of the PMOS transistor in active core A1. The primary winding of transformer F3 is connected to the drain of the PMOS transistor in active core A2, and the secondary winding of F3 is connected to the gate of the NMOS transistor in active core A2. The primary winding of transformer F4 is connected to the drain of the NMOS transistor in active core A2. The same-name terminal of the secondary winding is connected to the gate of the PMOS transistor in active core A2; the opposite-name terminal of the main winding of transformer F1 is connected to the opposite-name terminal of the main winding of transformer F4, the opposite-name terminal of the secondary winding of transformer F1 is connected to the opposite-name terminal of the secondary winding of transformer F4, the opposite-name terminal of the main winding of transformer F2 is connected to the opposite-name terminal of the main winding of transformer F3, and the opposite-name terminal of the secondary winding of transformer F2 is connected to the opposite-name terminal of the secondary winding of transformer F3; a capacitor or resistor is connected between the opposite-name terminals of the main winding and the secondary winding of transformer F1; a capacitor or resistor is connected between the opposite-name terminals of the main winding and the secondary winding of transformer F2; a capacitor or resistor is connected between the opposite-name terminals of the secondary winding of transformer F1 and the secondary winding of transformer F2; the sources of the PMOS transistors in active core A1 and active core A2 are both connected to V. DD The sources of the NMOS transistors in active core A1 and active core A2 are both grounded.

2. A complementary inverse F-type voltage-controlled oscillator according to claim 1, characterized in that, The drain capacitor C D or gate capacitance C G One or more of the following can be used: fixed capacitor, varactor diode, or switched capacitor.

3. A complementary inverse F-type voltage-controlled oscillator according to claim 2, characterized in that, The active cores A1 and A2 are either complementary double junction transistors or complementary field-effect transistors.

4. A complementary inverse F-type voltage-controlled oscillator based on inductor nesting, characterized in that, It is made using two complementary inverse F-class voltage-controlled oscillators with different frequencies as described in claim 3.

5. A complementary inverse F-type voltage-controlled oscillator based on inductor nesting according to claim 4, characterized in that, Two complementary inverse-F class voltage-controlled oscillators of different frequencies are placed orthogonally; one of the two complementary inverse-F class voltage-controlled oscillators of different frequencies adopts an 8-shaped design and the other adopts a ring design, and the two different oscillators are placed vertically.

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