Differential signal generation circuit

Abstract

The invention discloses a differential signal generation circuit. The differential signal generation circuit includes: an oscillator that generates a plurality of clock signals; the duty ratio adjusting module is used for respectively adjusting the duty ratio of each clock signal so as to obtain a plurality of clock signals; the logic module is used for providing differential signal pairs with complementary phases according to the plurality of clock signals, the oscillator comprises N stages of mutually connected phase inverters, the output ends of the N stages of phase inverters are used for providing the plurality of clock signals, and initial phase differences exist among the plurality of clock signals. The differential signal generation circuit is high in precision and simple in circuit structure.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and more particularly, to a differential signal generation circuit. Background Art

[0002] Differential signals are a pair of electrical signals with the same amplitude and opposite phases, which have advantages such as anti-interference, common-mode interference suppression, and signal integrity improvement. They are widely used in fields such as high-speed data transmission, audio and video transmission, and analog and digital signal processing.

[0003] Currently, a differential inverter structure or an additional single-ended to differential structure is usually used to generate differential signals. However, the differential inverter structure will increase the circuit complexity and the matching difficulty of the layout, while increasing the power consumption and the layout area; the differential signals generated by the single-ended to differential structure are not accurate enough and deviate too much with process variations, which is not suitable for high-speed and high-precision circuits. In addition, in low-voltage applications, the duty cycles of the signals generated by the above two schemes will seriously deviate from 50%, which is not conducive to subsequent signal processing.

[0004] Therefore, it is desirable to provide an improved differential signal generation circuit to solve the above problems. Summary of the Invention

[0005] In view of the above problems, an object of the present invention is to provide a differential signal generation circuit to generate accurate differential signals and simplify the circuit and save costs.

[0006] According to an aspect of the present invention, there is provided a differential signal generation circuit, including: an oscillator that generates a plurality of clock signals; and a logic module that provides a pair of differential signals with complementary phases according to the plurality of clock signals, wherein the oscillator includes N stages of interconnected inverters, N is greater than 0 and is an integer multiple of 3, and the output terminals of the N stages of inverters provide the plurality of clock signals, and there is an initial phase difference between the plurality of clock signals.

[0007] Optionally, the initial phase difference is 360 / N°.

[0008] Optionally, the N stages of inverters include a first inverter, a second inverter, and a third inverter connected in parallel between a signal source and a reference ground, the plurality of clock signals include a first signal, a second signal, and a third signal, the control terminal of the first inverter is connected to the output terminal of the third inverter, the control terminal of the second inverter is connected to the output terminal of the first inverter, the control terminal of the third inverter is connected to the output terminal of the second inverter, the output terminal of the first inverter provides the first signal, the output terminal of the second inverter provides the second signal, and the output terminal of the third inverter provides the third signal.

[0009] Optionally, each of the inverters includes: a first switching transistor and a second switching transistor connected in series between the signal source and the reference ground, the control terminals of the first switching transistor and the second switching transistor are connected to each other and serve as the control terminal of the inverter, the first current terminal of the first switching transistor is connected to the signal source, the second current terminal of the first switching transistor is connected to the first current terminal of the second switching transistor, the second current terminal of the second switching transistor is connected to the reference ground, and the connection node between the second current terminal of the first switching transistor and the first current terminal of the second switching transistor serves as the output terminal of the inverter.

[0010] Optionally, it further includes: a duty cycle adjustment module connected between the oscillator and the logic module for adjusting the duty cycle of each of the clock signals respectively.

[0011] Optionally, the duty cycle adjustment module includes a plurality of sub-adjustment modules corresponding to the plurality of clock signals to adjust the duty cycles of the plurality of clock signals to a predetermined range respectively.

[0012] Optionally, each of the sub-adjustment modules includes: a duty cycle detection circuit for obtaining a detection signal representing the duty cycle of the clock signal according to the clock signal; and a duty cycle adjustment circuit for adjusting the duty cycle of the clock signal according to the detection signal.

[0013] Optionally, the duty cycle detection circuit includes a first resistor, a first capacitor and a second capacitor connected in series between a voltage source and the reference ground, the first end of the first resistor receives the clock signal, the second end of the first resistor is connected to the series node of the first capacitor and the second capacitor and provides the detection signal; the duty cycle adjustment circuit includes a fourth inverter, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor and an eighth switching transistor, the third switching transistor and the fourth switching transistor are connected in series between the voltage source and the reference ground in sequence, the fifth switching transistor, the sixth switching transistor, the seventh switching transistor and the eighth switching transistor are connected in series between the voltage source and the reference ground in sequence, the clock signal is connected to the control terminals of the third switching transistor, the fourth switching transistor, the fifth switching transistor and the eighth switching transistor through the fourth inverter, the detection signal is connected to the control terminals of the sixth switching transistor and the seventh switching transistor, and the series node between the third switching transistor and the fourth switching transistor and the series node between the sixth switching transistor and the seventh switching transistor are connected to provide a calibrated clock signal.

[0014] Optionally, the clock signal is corrected by adjusting the driving capabilities of the sixth switching transistor and the seventh switching transistor.

[0015] Optionally, the logic module includes a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, and a ninth inverter. The multiple clock signals include a first signal, a second signal, and a third signal. The fifth inverter receives the first signal, the sixth inverter receives the third signal, and the seventh inverter receives the second signal. The output terminals of the fifth inverter and the sixth inverter are connected and connected to the input terminal of the eighth inverter. The output terminal of the seventh inverter is connected to the input terminal of the ninth inverter. The eighth inverter and the ninth inverter provide the differential signal pair.

[0016] The differential signal generation circuit provided by the present invention can generate accurate differential signals by using an oscillator structure, and has a simple circuit structure and low cost.

[0017] Furthermore, in response to the problem that the duty cycle is prone to shift under low-voltage applications, the present application uses a duty cycle adjustment circuit with a simple structure for correction, further increasing the accuracy of the differential signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0019] Figure 1 A block diagram of a differential signal generation circuit according to an embodiment of the present invention is shown;

[0020] Figure 2 A circuit schematic diagram of a differential signal generation circuit according to an embodiment of the present invention is shown;

[0021] Figure 3 A circuit schematic diagram of a sub-adjustment module according to an embodiment of the present invention is shown;

[0022] Figure 4 A signal waveform diagram of a differential signal generation circuit according to an embodiment of the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The present invention will be described in more detail below with reference to the drawings. In each of the drawings, the same elements are denoted by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the figures.

[0024] Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques, and technologies of the devices, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details.

[0025] It should be understood that in the embodiments of the present application, the connection / coupling between A and B means that A and B can be connected in series or in parallel, or A and B are connected through other devices, and the embodiments of the present application do not limit this.

[0026] Embodiments of the differential signal generation circuit provided by the present application will be described below with reference to the accompanying drawings.

[0027] Figure 1 A block diagram of a differential signal generation circuit according to an embodiment of the present invention is shown.

[0028] As Figure 1 shown, the differential signal generation circuit 100 includes an oscillator 110 and a logic module 120. Optionally, it further includes a duty cycle adjustment module 130. The differential signal generation circuit 100 can generate differential signals with high precision.

[0029] The oscillator 110 is used to generate a plurality of clock signals (hereinafter, the clock signals generated by the oscillator 110 are referred to as initial clock signals clk_p); the duty cycle adjustment module 130 is used to adjust the duty cycle of each clock signal respectively (hereinafter, the clock signals generated by the oscillator 110 are referred to as calibrated clock signals clk_d); the logic module 120 is used to provide a pair of differential signals with complementary phases according to a plurality of clock signals. In some embodiments, when the accuracy of the initial clock signal clk_p provided by the oscillator 110 is relatively high, for example, in high-voltage applications, the duty cycle adjustment module 130 can be omitted, and the logic module 120 directly provides a pair of differential signals with complementary phases according to a plurality of initial clock signals clk_p. In other embodiments, when the accuracy of the initial clock signal clk_p provided by the oscillator 110 is relatively low, for example, in low-voltage applications, the logic module 120 provides a pair of differential signals with complementary phases according to the calibrated clock signal clk_d provided by the oscillator 110.

[0030] In the embodiments of the present invention, there is an initial phase difference between a plurality of initial clock signals clk_p generated by the oscillator 110. For example, the oscillator 110 generates three initial clock signals clk_p with an initial phase difference of 120°. The logic module 120 performs signal synthesis on these three initial clock signals clk_p or the calibrated clock signals clk_d corresponding to these three initial clock signals clk_p, and high-precision differential signals can be generated. In an alternative embodiment, the oscillator 110 generates N initial clock signals clk_p, N is greater than 0 and is an integer multiple of 3, and the initial phase difference between adjacent two initial clock signals clk_p is 360° / N. The logic module 120 selects three initial clock signals clk_p with a phase difference of 120° among the N initial clock signals clk_p or the calibrated clock signals clk_d corresponding to these three initial clock signals clk_p for signal processing to obtain differential signals.

[0031] Therefore, an embodiment of the present invention provides a differential signal generation circuit with a three-terminal to differential structure and high precision. The circuit structure of the differential signal generation circuit according to the embodiment of the present invention will be described in detail below in conjunction with Figures 2-4 the accompanying drawings.

[0032] Figure 2 FIG. [X] shows a circuit schematic diagram of a differential signal generation circuit according to an embodiment of the present invention; Figure 3 FIG. [X] shows a circuit schematic diagram of a sub-adjustment module according to an embodiment of the present invention; Figure 4 FIG. [X] shows a signal waveform diagram of the differential signal generation circuit according to an embodiment of the present invention. In Figure 2 FIG. [X], the oscillator 110 generates three initial clock signals clk_p only by using three inverters. It should be understood that Figure 2 the number of inverters shown is only a schematic example, and the structure of the oscillator 110 in the present application is not limited thereto. The oscillator 110 provided in the embodiment of the present application may include N inverters to generate N initial clock signals clk_p, where N is greater than 0 and is an integer multiple of 3.

[0033] As Figure 2 shown in FIG. [X], the differential signal generation circuit 100 includes an oscillator 110, a logic module 120, and a duty cycle adjustment module 130. The differential signal generation circuit 100 can generate differential signals with high precision. In some alternative embodiments, the duty cycle adjustment module 130 may be omitted.

[0034] The oscillator 110 is used to generate a plurality of initial clock signals clk_p. The oscillator 110 includes N stages of interconnected inverters, where N is greater than 0 and is an integer multiple of 3. The output terminals of the N-stage inverters provide a plurality of clock signals clk, and there is an initial phase difference between the plurality of clock signals clk. For example, the oscillator 110 generates three initial clock signals clk_p with an initial phase difference of 120°. For another example, the oscillator 110 generates N initial clock signals clk_p, where N is greater than 0 and is an integer multiple of 3, and the initial phase difference between adjacent two initial clock signals clk_p is 360° / N.

[0035] In this embodiment, the oscillator 110 includes N stages of inverters. The N stages of inverters include a first inverter 111, a second inverter 112, and a third inverter 113 connected in parallel between a signal source and a reference ground. The plurality of initial clock signals clk_p include a first signal P1, a second signal P2, and a third signal P3. The control terminal of the first inverter 111 is connected to the output terminal of the third inverter 113. The control terminal of the second inverter 112 is connected to the output terminal of the first inverter 111. The control terminal of the third inverter 113 is connected to the output terminal of the second inverter 112. The output terminal of the first inverter 111 provides the first signal P1. The output terminal of the second inverter 112 provides the second signal P2. The output terminal of the third inverter 113 provides the third signal P3.

[0036] As an example, the structures of the first inverter 111, the second inverter 112, and the third inverter 113 are exactly the same. Each inverter includes a first switching transistor M1 and a second switching transistor M2. In each inverter, the first switching transistor M1 and the second switching transistor M2 are connected in series between a signal source S1 and a reference ground GND. The signal source S1 can be a current source or a voltage source. The control terminals of the first switching transistor M1 and the second switching transistor M2 are connected to each other and serve as the control terminal of the inverter. The first current terminal of the first switching transistor M1 is connected to the signal source S1. The second current terminal of the first switching transistor M1 is connected to the first current terminal of the second switching transistor M2. The second current terminal of the second switching transistor M2 is connected to the reference ground GND. The connection node between the second current terminal of the first switching transistor M1 and the first current terminal of the second switching transistor M2 serves as the output terminal of the inverter. The types of the first switching transistor M1 and the second switching transistor M2 are opposite. For example, the first switching transistor M1 is an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the second switching transistor M2 is a P-type MOSFET.

[0037] The duty cycle adjustment module 130 is connected to the oscillator 110 and receives three initial clock signals clk_p with an initial phase difference. The duty cycle adjustment module 130 adjusts the duty cycles of the three initial clock signals clk_p to obtain three calibrated clock signals clk_d and sends the calibrated clock signals clk_d to the logic module 120. The duty cycle adjustment module 130 can obtain three calibrated clock signals clk_d with duty cycles within a predetermined range. Since the calibration effects of the duty cycle adjustment module 130 on the duty cycles of the three initial clock signals clk_p are basically the same, the three calibrated clock signals clk_d still have an initial phase difference. In this embodiment, the predetermined range is, for example, 40% - 60%. In an ideal case, the duty cycle of the calibrated clock signal clk_d is about 50%.

[0038] In this embodiment, the duty cycle adjustment module 130 includes a plurality of sub - adjustment modules 131 corresponding to a plurality of initial clock signals clk_p, so as to adjust the duty cycles of the plurality of initial clock signals clk_p to within a predetermined range respectively.

[0039] As an example, each sub - adjustment module 131 includes a duty cycle detection circuit 131a and a duty cycle adjustment circuit 131b. The duty cycle detection circuit 131a obtains a detection signal V2 representing the duty cycle of the initial clock signal clk_p according to the initial clock signal clk_p; the duty cycle adjustment circuit 131b adjusts the duty cycle of the initial clock signal clk_p according to the detection signal V2 to obtain a calibrated clock signal clk_d.

[0040] Please refer to Figure 3 , the duty cycle detection circuit 131a includes a first resistor R1 and a first capacitor C1 and a second capacitor C2 connected in series between a voltage source VCC and a reference ground GND. The first end of the first resistor R1 receives the initial clock signal clk_p, and the second end of the first resistor R1 is connected to the series node of the first capacitor C1 and the second capacitor C2 and provides the detection signal V2. The duty cycle detection circuit 131a converts the duty cycle information of the initial clock signal clk_p into a voltage signal (i.e., the detection signal V2) through an RC filtering structure. When the duty cycle of the initial clock signal clk_p is low, the detection signal V2 is low; when the duty cycle of the initial clock signal clk_p is high, the detection signal V2 is high. Therefore, the amplitude level of the detection signal V2 can represent the magnitude of the duty cycle of the initial clock signal clk_p.

[0041] The duty cycle adjustment circuit 131b includes a fourth inverter I4, a third switch M3, a fourth switch M4, a fifth switch M5, a sixth switch M6, a seventh switch M7, and an eighth switch M8. The third switch M3 and the fourth switch M4 are connected in series between the voltage source VCC and the reference ground GND in sequence. The fifth switch M5, the sixth switch M6, the seventh switch M7, and the eighth switch M8 are connected in series between the voltage source VCC and the reference ground GND in sequence. The initial clock signal clk_p passes through the fourth inverter I4 to obtain an intermediate clock signal V1. The intermediate clock signal V1 is connected to the control terminals of the third switch M3, the fourth switch M4, the fifth switch M5, and the eighth switch M8. The detection signal V2 is connected to the control terminals of the sixth switch M6 and the seventh switch M7. The series connection node between the third switch M3 and the fourth switch M4 and the series connection node between the sixth switch M6 and the seventh switch M7 are connected to provide a calibration clock signal clk_d. The types of the third switch M3 and the fourth switch M4 are opposite. The types of the third switch M3, the fifth switch M5, and the sixth switch M6 are the same. The types of the fourth switch M4, the seventh switch M7, and the eighth switch M8 are the same. For example, the third switch M3, the fifth switch M5, and the sixth switch M6 are N-type MOSFETs, and the fourth switch M4, the seventh switch M7, and the eighth switch M8 are P-type MOSFETs.

[0042] In some embodiments, in order to obtain a calibration clock signal clk_d with a duty cycle closer to 50%, the initial clock signal clk_p is calibrated by adjusting the driving capabilities of the sixth switch M6 and the seventh switch M7.

[0043] The logic module 120 provides a pair of phase-complementary differential signals according to multiple clock signals. In some embodiments, when the accuracy of the initial clock signal clk_p provided by the oscillator 110 is high, such as in high-voltage applications, the duty cycle adjustment module 130 can be omitted, and the logic module 120 directly provides a pair of phase-complementary differential signals according to multiple initial clock signals clk_p. In other embodiments, when the accuracy of the initial clock signal clk_p provided by the oscillator 110 is low, such as in low-voltage applications, the logic module 120 provides a pair of phase-complementary differential signals according to the calibration clock signal clk_d provided by the oscillator 110.

[0044] In this embodiment, the oscillator 110 generates three initial clock signals clk_p with an initial phase difference of 120°. The logic module 120 performs signal synthesis on these three initial clock signals clk_p or the calibrated clock signals clk_d corresponding to these three initial clock signals clk_p, thereby generating a high-precision differential signal. In an alternative embodiment, the oscillator 110 generates N initial clock signals clk_p, where N is greater than 0 and an integer multiple of 3, and the initial phase difference between adjacent two initial clock signals clk_p is 360° / N. The logic module 120 selects three initial clock signals clk_p with a phase difference of 120° from the N initial clock signals clk_p or the calibrated clock signals clk_d corresponding to these three initial clock signals clk_p for signal processing to obtain a differential signal.

[0045] As an example, the logic module 120 includes a fifth inverter I5, a sixth inverter I6, a seventh inverter I7, an eighth inverter I8, and a ninth inverter I9. The multiple clock signals (initial clock signals clk_p or calibrated clock signals clk_d) include a first signal D1, a second signal D2, and a third signal D3. The fifth inverter I5 receives the first signal D1, the sixth inverter I6 receives the third signal D3, the seventh inverter I7 receives the second signal D2. The output terminals of the fifth inverter I5 and the sixth inverter I6 are connected and connected to the input terminal of the eighth inverter I8. The output terminal of the seventh inverter I7 is connected to the input terminal of the ninth inverter I9. The output terminals of the eighth inverter I8 and the ninth inverter I9 provide a differential signal pair P5 and P7.

[0046] Specifically, please refer to Figure 4 , the oscillator 110 or the duty cycle adjustment module 130 provides a first signal D1, a second signal D2, and a third signal D3 with an initial phase difference of 120°. The fifth inverter I5 and the sixth inverter I6 respectively receive the first signal D1 and the third signal D3, and synthesize the inverted first signal D1 and third signal D3 into a signal P4. The seventh inverter I7 receives the second signal D2 and inverts the second signal D2 into a signal P6. The eighth inverter I8 receives the signal P4 and inverts the signal P4 into a signal P5. The ninth inverter I9 receives the signal P6 and inverts the signal P6 into a signal P7. The signals P5 and P7 are a pair of differential signals, with the same amplitude and opposite phases, that is, the phase difference between the signals P5 and P7 is 180°.

[0047] Some examples of the differential signal generation circuit according to the embodiments of the present invention are described above. However, the embodiments of the present invention are not limited thereto, and there may be other ways of expansion and deformation.

[0048] For example, it should be understood that the reference ground in the foregoing embodiments may be replaced with other non-zero reference potentials (with positive or negative voltage amplitudes) or reference signals with controlled variations in alternative embodiments.

[0049] For another example, the capacitors and resistors provided in the embodiments of the present application may be lumped-parameter capacitor elements and resistor elements, or may be other equivalent elements with functions similar to those of capacitors and resistors. The equivalent structures described herein include, for example but are not limited to, microstrip lines, varactor diodes, conductor structures with certain patterns, etc., which can provide impedance and / or capacitive impedance.

[0050] At the same time, those of ordinary skill in the art can realize that for the structures and methods of each example described in combination with the embodiments disclosed herein, different configuration methods or adjustment methods can be used to implement the described functions for each structure or reasonable deformations of the structure. However, such implementation should not be considered to exceed the scope of the present application. Moreover, it should be understood that the connection relationships between the various components of the amplifier in the foregoing figures in the embodiments of the present application are illustrative examples and do not impose any limitations on the embodiments of the present application.

[0051] In summary, the embodiments of the present invention provide a differential signal generation circuit, which can generate accurate differential signals by using a basic oscillator structure and a logic module. The circuit structure is simple and the cost is low.

[0052] In some optional embodiments, in view of the problem that the duty cycle is prone to shift under low-voltage applications, the present application uses a duty cycle adjustment circuit with a simple structure to perform correction, further increasing the accuracy of the differential signal.

[0053] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0054] As described above, the embodiments in accordance with the present invention do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A differential signal generating circuit, comprising: Oscillators, generating multiple clock signals; as well as A logic module, providing a differential signal pair with complementary phases according to a plurality of the clock signals, The oscillator includes N levels of inverters connected to each other, N is greater than 0 and is an integer multiple of 3, and the output ends of the N levels of inverters provide multiple clock signals, and there is an initial phase difference between the multiple clock signals.

2. The differential signal generating circuit according to claim 1, wherein: The initial phase difference is 360 / N°.

3. The differential signal generating circuit according to claim 1, wherein: The N-stage inverters include a first inverter, a second inverter and a third inverter connected in parallel between a signal source and a reference ground, and the plurality of clock signals include a first signal, a second signal and a third signal. The control end of the first inverter is connected to the output end of the third inverter, the control end of the second inverter is connected to the output end of the first inverter, and the control end of the third inverter is connected to the output end of the second inverter. The output terminal of the first inverter provides the first signal, the output terminal of the second inverter provides the second signal, and the output terminal of the third inverter provides the third signal.

4. The differential signal generating circuit according to any one of claims 1 to 3, wherein: Each of the inverters comprises: A first switch tube and a second switch tube are connected in series between a signal source and a reference ground, control ends of the first switch tube and the second switch tube are connected to each other and serve as the control end of the inverter, a first current end of the first switch tube is connected to the signal source, a second current end of the first switch tube is connected to the first current end of the second switch tube, a second current end of the second switch tube is connected to the reference ground, and a connection node between the second current end of the first switch tube and the first current end of the second switch tube serves as the output end of the inverter.

5. The differential signal generating circuit according to claim 1, further comprising: The duty cycle adjustment module is connected between the oscillator and the logic module, and is used to adjust the duty cycle of each of the clock signals.

6. The differential signal generating circuit according to claim 5, wherein: The duty cycle adjustment module includes a plurality of sub-adjustment modules corresponding to the plurality of clock signals, so as to adjust the duty cycles of the plurality of clock signals to within a predetermined range respectively.

7. The differential signal generating circuit according to claim 6, wherein: Each of the sub-adjustment modules comprises: a duty cycle detection circuit, which obtains a detection signal representing the duty cycle of the clock signal according to the clock signal; and The duty cycle adjustment circuit adjusts the duty cycle of the clock signal according to the detection signal.

8. The differential signal generating circuit according to claim 7, wherein: The duty cycle detection circuit comprises a first resistor and a first capacitor and a second capacitor connected in series between a voltage source and a reference ground, wherein a first end of the first resistor receives the clock signal, and a second end of the first resistor is connected to a series node of the first capacitor and the second capacitor and provides the detection signal; The duty cycle adjustment circuit includes a fourth inverter, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube and an eighth switch tube. The third switch tube and the fourth switch tube are connected in series between a voltage source and a reference ground in sequence. The fifth switch tube, the sixth switch tube, the seventh switch tube and the eighth switch tube are connected in series between the voltage source and the reference ground in sequence. The clock signal is connected to the control end of the third switch tube, the control end of the fourth switch tube, the control end of the fifth switch tube and the control end of the eighth switch tube through the fourth inverter. The detection signal is connected to the control end of the sixth switch tube and the control end of the seventh switch tube. The series node between the third switch tube and the fourth switch tube is connected to the series node between the sixth switch tube and the seventh switch tube and provides a calibrated clock signal.

9. The differential signal generating circuit according to claim 8, wherein: The clock signal is corrected by adjusting the driving capabilities of the sixth switch tube and the seventh switch tube.

10. The differential signal generating circuit according to claim 1, wherein: The logic module includes a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter and a ninth inverter, The plurality of clock signals include a first signal, a second signal and a third signal, The fifth inverter receives the first signal, the sixth inverter receives the third signal, and the seventh inverter receives the second signal. The output terminal of the fifth inverter is connected to the output terminal of the sixth inverter and is connected to the input terminal of the eighth inverter. The output terminal of the seventh inverter is connected to the input terminal of the ninth inverter, The eighth inverter and the ninth inverter provide the differential signal pair.

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