Clock and data recovery circuitry

Abstract

The invention relates to clock and data recovery circuitry. In an example, a circuit (114) includes clock data recovery (CDR) circuitry (202) having an input and an output. The circuit (114) also includes a delay circuit (204) having an input coupled to the output of the CDR circuitry (202), and having an output. The circuit (114) includes a multiphase oscillator (206) having an input coupled to the output of the delay circuit (204), and having an output. The circuit (114) also includes a frequency divider (208) having an input coupled to the output of the multiphase oscillator (206) and having an output coupled to the input of the CDR circuitry (202).

Description

Technical Field

[0001] This application generally relates to circuits, and more particularly to clock and data recovery circuitry. Background Art

[0002] Data can be transmitted from a transmitter to a receiver in a wired manner. The data is tracked by the receiver and aligned at the time points when the signal is at or near its maximum value, so that the data can be sampled appropriately. A clock and data recovery (CDR) circuitry at the receiver can be used to generate a clock signal based on the incoming data. The retrieved clock is used to re-time the incoming data. The data may also drift over time, and the drift is tracked. The clock and data can be aligned with a programmable delay unit. Summary of the Invention

[0003] In at least one example of the specification, a circuit includes a clock data recovery (CDR) circuitry having an input and an output. The circuit further includes a delay circuit having an input coupled to the output of the CDR circuitry and an output. The circuit includes a multi-phase oscillator having an input coupled to the output of the delay circuit and an output. The circuit further includes a frequency divider having an input coupled to the output of the multi-phase oscillator and an output coupled to the input of the CDR circuitry.

[0004] In at least one example of the specification, a circuit includes a CDR circuitry having an input and an output. The circuit includes a delay circuit having an input coupled to the output of the CDR circuitry and an output. The circuit further includes a multi-phase oscillator having an input coupled to the output of the delay circuit and an output. The circuit includes a frequency divider having an input coupled to the output of the multi-phase oscillator and an output coupled to the input of the CDR circuitry. The circuit further includes a calibration circuit having a first input, a second input, and a third input, the first input and the second input being coupled to the output of the delay circuit, and the third input being coupled to the output of the multi-phase oscillator.

[0005] In at least one example of the specification, a method includes providing a delay from a delay circuit to a first phase of a multi-phase oscillator on an injection clock path. The method further includes determining to update the delay using a correction value. The method includes changing the delay in response to a control signal provided to the delay circuit if the correction value is less than a threshold. The method further includes changing the injection time point of the delay circuit to a second phase of the multi-phase oscillator if the correction value exceeds the threshold. Brief Description of the Drawings

[0006] Figure 1 is a block diagram of an example serializer / deserializer.

[0007] Figure 2 It is a block diagram of an example CDR and clock circuit system.

[0008] Figure 3 It is a diagram showing the output phases of an example polyphase ring oscillator.

[0009] Figure 4 It is a flowchart of an example method for updating the delay provided by a delay circuit system.

[0010] Figure 5 It is a flowchart of an example method for updating the delay provided by a delay circuit system.

[0011] Figure 6 It is a block diagram of an example system for clock and data recovery.

[0012] Figure 7 It is a flowchart of an example method for performing calibration.

[0013] Figure 8 It is a flowchart of an example method for adjusting the injection phase of a polyphase oscillator.

[0014] Figure 9 It is a block diagram of an example system for clock and data recovery.

[0015] Figure 10 It is a block diagram of an example calibration circuit system and control logic.

[0016] Figure 11 It is a flowchart of an example method for calibration.

[0017] Figure 12 It is a flowchart of an example method for calibration and selection of the injection phase.

[0018] Figure 13 It is a flowchart of an example method for updating the delay provided by a delay circuit system.

[0019] In the drawings, the same reference numerals or other reference indicators are used to denote (functionally and / or structurally) identical or similar features. Detailed Description

[0020] A clock and data recovery (CDR) circuit system at a receiver can be used to generate a clock signal based on incoming data. The CDR circuit system recovers timing information from the incoming signal and retimes the received data. The data may also drift over time from its source, and the drift is tracked for correction. A programmable delay unit can be used to align the clock and data. However, in some systems, the delay unit must cover a large range such as from 1 microsecond (ms) to 100 femtoseconds (fs), and this range may involve a large amount of hardware. Additionally, in the case of high data rates, interleaved sampling is useful. Interleaved sampling uses multiple analog-to-digital converters (ADCs) to sample the same input waveform, but with different relative phases at which the sampling is performed. Then, the hardware interleaves these samples to create a waveform as if only one ADC had sampled the waveform at a higher sampling rate. For a rate of 112 gigabits per second (GBPS), 8 phases of a 14 gigahertz (GHz) clock can be sampled. The jitter tolerance specification may require tracking large delays, which requires large area and power. For a bit error rate (BER) of 1e-10, the incoming data is sampled, and the error may need to be as low as 100 femtoseconds (fs) to accurately sample.

[0021] In one system, a phase-locked loop (PLL) has a voltage-controlled oscillator (VCO), and the CDR loop controls the PLL phase. The output of the PLL has a delay unit and a phase interpolator (PI) to generate an interleaved sampling clock. The delay unit and PI at the output can have large power and area. In a second system, a ring oscillator (RO) is used instead of the VCO. The architecture of the RO provides multiple phases. However, the PLL in this system uses large power and area to meet the noise specification, and still uses the PI, which increases the power consumption. In a third system, the RO is injection-locked, so the PLL is not used. However, the PI is used at the output, which increases the power consumption.

[0022] In an example herein, an injection-locked oscillator (e.g., RO) has delay control implemented on the injection clock path rather than at the output of the oscillator. Delaying the injection clock delays all output phases of the multiphase oscillator. Therefore, the PI is not used at the output. Injection locking is used to low-pass filter the input phase, which relaxes the noise and power requirements since the delay unit is now on the injection path.

[0023] In one example, incoming data is provided to a CDR loop. A delay circuit system (e.g., a delay cell) measures the error between the data and the clock. The measured error is used to generate an injection clock provided to the input of the RO. The input is low-pass filtered, so the noise at the output is reduced and PI is not used at the output. In an example, if the bandwidth of the injection clock is 500 megahertz (MHz), noise above 500 MHz is suppressed and does not appear at the output of the RO. This feature reduces the specification of the delay cell and decreases the area and power used by the system.

[0024] In some examples, the delay circuit system provides a delay range of about 10 nanoseconds (ns) with an accuracy of 100 femtoseconds (fs). The delay is provided by the delay circuit system to each output of the RO. If the injection clock is delayed by the delay circuit system, all phases at the output of the RO are also delayed. For example, if the injection clock is shifted by 100 fs, all phases of the RO are shifted by 100 fs. Thus, in this example, only one delay cell or delay circuit is used instead of a delay circuit for each output of the RO. The injection clock also improves the low-pass behavior, which reduces the low-frequency phase noise of the RO. Additionally, the delay circuit provides a smaller delay range compared to other systems, which decreases the power and area. A large delay can be represented by changing the phase of the RO to which the injection clock is provided and using a smaller range for the delay circuit.

[0025] The examples described herein generate a delay range from microseconds to picoseconds for any application. The delay can be injected at any phase of the output clock. If the RO has a period T and there are eight output phases in an example, each phase has a period of T / 8. The delay circuit only needs to provide a delay of T / 8. If T is 70 ps, then T / 8 is 8.5 ps, so a delay range of ±8.5 ps can allow synthesis of any delay. For example, the injection time point can be changed (e.g., from phase 1 to phase N) to synthesize any delay.

[0026] Figure 1 is a block diagram of an example serializer / deserializer system 100. On the transmitter side, the system 100 includes a serializer 102 and a transmitter 104. A channel 106 connects the transmitter side and the receiver side. The receiver side includes a continuous-time linear equalizer (CTLE) / variable gain amplifier (VGA) 108, an ADC 110, a feed-forward equalizer (FFE) / decision feedback equalizer (DFE) 112, a CDR and clock circuit system 114, and a deserializer 124. The system 100 has an input terminal 120 and an output terminal 122. The system 100 also receives input data 116 at the input terminal 120 and provides output data 118 at the output terminal 122.

[0027] Serializer 102 has an input terminal 120 that receives input data 116 and an output that couples to an input of transmitter 104. Transmitter 104 has an output that couples to channel 106. CTLE / VGA 108 has an input that couples to channel 106 and an output that couples to an input of CDR and clock circuitry 114. CTLE / VGA 108 has an output that couples to an input of ADC 110. ADC 110 has another input that couples to an output of CDR and clock circuitry 114 and an output that couples to an input of FFE / DFE 112. FFE / DFE 112 has an output that couples to an input of CDR and clock circuitry 114 and an output that couples to an input of deserialization 124. Deserializer 124 has an output terminal 122 that provides output data 118.

[0028] In one example, serializer 102 receives input data 116 at input terminal 120 and provides serialized data at its output to an input of transmitter 104. Transmitter 104 transmits the serialized data over channel 106. CTLE / VGA 108 receives the serialized data from channel 106. CTLE / VGA 108 equalizes and amplifies the incoming input signal. ADC 110 receives data from CTLE / VGA 108 and performs analog-to-digital conversion. ADC 110 provides the data to FFE / DFE 112. FFE / DFE 112 provides feed-forward equalization and decision feedback equalization of the data. FFE / DFE 112 has an output that provides data to deserializer 124 and an output that provides data to an input of CDR and clock circuitry 114. Deserializer 124 provides deserialized output data 118 at output terminal 122. CDR and clock circuitry 114 provides clock and data recovery. As described in the examples herein, CDR and clock circuitry 114 provides N phase outputs from a multi-phase oscillator. CDR and clock circuitry 114 provides data and clock signals to CTLE / VGA 108 and ADC 110.

[0029] In the examples herein, CDR and clock circuitry 114 includes an injection-locked oscillator (e.g., RO) that has delay control implemented on an injection clock path rather than at the output of the oscillator. The injection-locked oscillator receives, at its input, a periodic clock signal (e.g., an injection clock signal or injection clock on the injection clock path) that locks the oscillator to the phase and / or frequency of the injection clock signal. The injection clock can be used to change the phase and / or frequency of the clock signal generated by the oscillator. Delaying the injection clock delays all output phases of the multi-phase oscillator. Described below with respect to Figure 2 CDR and clock circuitry 114 is described.

[0030] Figure 2is a block diagram of an example CDR and clock circuit system 114. The CDR and clock circuit system 114 includes a CDR 202, a delay circuit system 204 (e.g., a delay circuit), a multiphase oscillator 206, and an M-divider 208. Figure 2 Also shown are an input data 210, a VCTRL 212 (voltage control signal), an INJCLK 214 (injection clock or injection input signal), an N-phase output 216, and a CLK-FB 218 (clock feedback). In some instances, Figure 2 the components in are referred to as a CDR loop.

[0031] The CDR 202 has a first input that receives the input data 210 and a second input that receives the CLK-FB 218. The CDR 202 has an output that is coupled to an input of the delay circuit system 204, where the output provides the VCTRL 212 to the input of the delay circuit system 204 (referred to as a voltage control input). The delay circuit system 204 has an output that is coupled to an input of the multiphase oscillator 206, and the delay circuit system 204 provides the INJCLK 214 to the input of the multiphase oscillator 206. The multiphase oscillator 206 has an output that provides the N-phase output 216. In an example, the N-phase output 216 is a clock signal that is provided to other components in the receiver for processing the received data. As Figure 1 shown, the clock signal is provided to the CTLE / VGA 108, the ADC 110, and the FFE / DFE 112. The clock signal can also be provided to other components of the receiver. Example clock signals for the multiphase oscillator are described below with respect to Figure 3 One of the N-phase outputs 216 is provided to an input of the M-divider 208. The M-divider 208 has an output that is coupled to an input of the CDR 202, and the M-divider 208 provides the CLK-FB 218 to the input of the CDR 202. The M-divider 208 receives an input clock signal from the multiphase oscillator 206 at a frequency F 1 and generates an output signal CLK-FB 218 at a frequency F 2 The CLK-FB 218 is a feedback signal that is provided to the CDR 202 for comparing the N-phase output 216 with the incoming input data 210 and adjusting the INJCLK 214, as described herein.

[0032] In operation, input data 210 is provided to the CDR 202. The CDR 202 performs clock and data recovery operations using any suitable hardware, logic, or software. The CDR 202 provides a control voltage VCTRL 212 to the delay circuitry 204. VCTRL 212 controls the amount of delay generated by the delay circuitry 204. The CDR 202 generates VCTRL 212 based on the difference between the input data 210 and CLK-FB 218. The greater the difference between these two signals, the greater VCTRL 212, resulting in a greater delay generated by the delay circuitry 204. The delay circuitry 204 receives VCTRL 212, which represents a measure of the error present between the input data 210 and CLK-FB 218. This error is used by the delay circuitry 204 to generate INJCLK 214, which is provided to the multiphase oscillator 206. INJCLK 214 locks the multiphase oscillator 206 to the desired frequency. In the examples herein, the advantage of injection locking is to provide phase filtering. Since injection locking provides phase filtering, a phase interpolator at the output is not used for low-pass filtering. In some examples herein, the absence of these phase interpolators reduces power and area.

[0033] Figure 3 is a diagram 300 of the waveform of the output of an example RO. The RO generates an output signal at each stage or phase, where the number of phases N is 5 in this example. The output signals are spaced approximately evenly in phase. The frequency of the RO varies with the number of stages and the delay time of the inverters in each stage. The oscillation frequency in the RO can be set by changing the delay time or the number of stages.

[0034] In diagram 300, the y-axis represents the voltage of the output signal of the RO, and the x-axis represents time. In diagram 300, the example RO generates five phases. The waveforms 302, 304, 306, 308, and 310 represent the five phases. In the examples herein, INJCLK 214 can be provided to any phase of the multiphase oscillator 206. If a larger correction of the VCTRL 212 value is indicated, the delay circuitry 204 can switch to providing INJCLK 214 to a different phase of the multiphase oscillator 206. Calibration operations can also be performed as described below. Calibration determines the delay between any two adjacent phases of the multiphase oscillator. For example, calibration can be performed to determine the delay between waveform 302 and waveform 304. This delay can be stored and used as described below to indicate when to switch to providing INJCLK 214 to a different phase of the multiphase oscillator 206.

[0035] Figure 4is a flowchart of an example method 400 for updating the delay provided by the delay circuit system 204. The operations of method 400 may be performed in any suitable order. In some instances, the hardware components described above with respect to Figure 1-2 and below with respect to Figure 6 and 9 -10 may perform method 400. In some instances, any suitable hardware, software, or digital logic may perform method 400. Method 400 describes a simplified delay update process in which calibration is not performed. The delay update process described below Figure 5 includes a delay update process in which calibration is performed.

[0036] Method 400 begins at 410, where the delay is indicated by the provided VCTRL 212 signal. The delay circuit system 204 receives VCTRL 212 from the CDR 202 and provides the delay to the multiphase oscillator 206 via INJCLK 214 in response to and / or based on VCTRL 212. The magnitude of VCTRL 212 and thus the magnitude of the delay are determined by the difference between the input data 210 and CLK-FB 218.

[0037] Method 400 proceeds to 420, where the CDR 202 determines whether to update the delay. If the input data 210 and CLK-FB 218 are within an acceptable (e.g., programmed) first threshold of each other, no update is performed and the method returns to 410. If the CDR 202 determines that the input data 210 and CLK-FB 218 have drifted apart and the difference is to be corrected (e.g., not within the acceptable first threshold), then method 400 proceeds to 430.

[0038] At 430, method 400 determines whether the magnitude of the updated delay value exceeds a second threshold. The CDR 202 may make this determination using control logic, code, or software as described below. This second threshold relates to the magnitude of the updated delay value and whether the magnitude of the updated delay value is close to the value of the RO period (T) divided by the number of phases (N). For example, if the RO clock period is T VCO , and the RO has 8 phases, then the second threshold is the magnitude of the updated delay value that is close to or equal to T VCO / N or T VCO / 8. The second threshold may be set to the value of T VCO / N, or may be set to a value that is close to but less than T VCO / N, such as 70% or 90% of T VCO / N. Below with respect to Figure 5Describe the second threshold and its use for calibration. In method 400, the second threshold determines whether the injection time point changes to a different phase of the multiphase oscillator 206, or whether the delay value changes to an updated value and is provided to the current phase of the multiphase oscillator 206. If the updated delay value exceeds the second threshold, the injection time point changes to a different phase. If the updated delay value does not exceed the second threshold, the delay value is updated without changing the injection time point.

[0039] At 430, if the updated delay value does not exceed the second threshold (e.g., T VCO / N, 70% of T VCO / N, etc.), the method proceeds to 440. At 440, the updated delay value is indicated to the delay circuitry 204 via VCTRL 212. The CDR 202 provides the updated delay value via VCTRL 212. The delay circuitry 204 updates the value of the delay, and the new delay value is provided to the multiphase oscillator 206. Method 400 proceeds to 410, where the CDR loop continues to update the delay as needed.

[0040] At 430, if the updated delay value exceeds the second threshold (e.g., T VCO / N), method 400 proceeds to 450. At 450, the injection time point of INJCLK 214 is changed to the previous or next phase of the multiphase oscillator 206. The previous or next phase is selected based on the direction of the delay change. As an example, the injection clock can be provided to Figure 3 the waveform 304 in. If the delay value exceeds the second threshold and the injection time point changes to the next phase, the injection clock switches to waveform 306, which is a different phase of the multiphase oscillator 206. If the delay value exceeds the second threshold and the injection time point changes to the previous phase, the injection clock switches to waveform 302. Thus, if a larger change in the delay value exceeding the second threshold (e.g., T VCO / N) is needed, the phase of the injection clock can be switched. At 450, for example, if the injection clock changes to the previous or next phase of the multiphase oscillator 206, the correction delay can be reset to zero.

[0041] After 450, or after the "no" result at 430, method 400 proceeds to 440. The updated delay is provided by the CDR 202 to the delay circuitry 204 (the updated delay can be zero delay in some instances). Then, method 400 proceeds to 410, where the difference between the input data 210 and CLK-FB 218 is determined. If the input data 210 and CLK-FB 218 have drifted apart and the difference is to be corrected, an additional update of the delay value can be performed.

[0042] Figure 5 is a flow chart of an example method 500 for updating the delay provided by the delay circuit system 204. The operations of method 500 may be performed in any suitable order. In some instances, the hardware components described above with respect to Figure 1-2 and below with respect to Figure 6 and 9 -10 may perform method 500. In some instances, any suitable hardware, software, or digital logic may perform method 500.

[0043] Method 500 begins at 510, where a delay update is provided from the CDR 202. The CDR 202 determines the value of the delay update (e.g., the correction delay value) based on the difference between the input data 210 and the CLK-FB 218. In this instance, the CDR 202 determines to update the delay at 510.

[0044] Method 500 proceeds to 520, where control logic (e.g., Figure 6 , 9 and 604 of 10) determines whether the correction delay value exceeds a second threshold, e.g., T VCO / N. As described above, the second threshold may be a value less than T VCO / N, e.g., 70% of T VCO / N. If the correction delay value exceeds the second threshold, method 500 proceeds to 540. If the correction delay value does not exceed the second threshold, method 500 proceeds to 530. At 530, the CDR 202 increases or decreases the delay via the VCTRL 212. After updating the value of the VCTRL 212, method 500 returns to 510.

[0045] At 520, if the correction delay value exceeds the second threshold, method 500 proceeds to 540. At 540, the control logic determines whether calibration has been performed. If calibration has not been performed, method 500 proceeds to 550.

[0046] At 550, the CDR 202 increases or decreases the delay via the VCTRL 212. After updating the value of the VCTRL 212, method 500 returns to 510. Additionally, if calibration has not been performed, method 500 proceeds from 540 to 560. At 560, the calibration circuit system (described below) measures and stores the delay between the current phase of the multi-phase oscillator 206 and the previous and next phases of the multi-phase oscillator 206. The delay may be stored in a memory or any suitable storage device. Calibration is performed to determine the delay differences between the various phases of the multi-phase oscillator 206. These differences can be used to determine when to switch the injection clock to a different phase, or when to only update the delay value without switching the injection clock.

[0047] At 540, the control logic determines whether calibration has been performed. If calibration has been performed, method 500 proceeds to 570. At 570, the control logic determines whether the correction delay value is greater than the stored delay. The stored delay is stored as a result of the calibration process performed at 560, as described above. The stored delay represents the phase delay between the phases of the multi-phase oscillator 206. If the correction value is not greater than the stored delay, method 500 proceeds to 530, where the CDR 202 increases or decreases the delay via VCTRL 212. After updating the value of VCTRL 212, method 500 returns to 510.

[0048] At 570, if the control logic determines that the correction value is greater than the stored delay, method 500 proceeds to 580. If the correction value is greater than the stored delay, this means that the correction value has pushed the delay to the next or previous phase of the multi-phase oscillator 206. Method 500 changes the injection time point to the next or previous stage at 580, rather than implementing a larger delay that extends into another phase of the multi-phase oscillator 206. At 580, the control logic also resets the correction delay. After changing the injection time point to an adjacent stage at 580, method 500 proceeds to 530. At 530, the CDR 202 increases or decreases the delay via VCTRL 212 as needed, and the CDR loop proceeds to provide injection time points to different stages of the multi-phase oscillator 206.

[0049] Figure 6 is a block diagram of an example system 600 for clock and data recovery. System 600 includes some of the components described above with respect to Figure 2 and like reference numerals represent like components. In some instances herein, Figure 6 the components in may be referred to as a CDR loop.

[0050] System 600 includes a CDR 202, a delay circuitry 204 (which provides correction delay and injection clock generation), a multi-phase oscillator 206, and an M-divider 208. Also shown are input data 210, VCTRL 212, INJCLK 214 (shown as multiple injection input signals in Figure 6 ), an N-phase output 216, and CLK-FB 218. These components are coupled together and operate as described above with respect to Figure 2 . System 600 includes Figure 2 the components of the CDR loop shown in, as well as additional components for calibrating and controlling the CDR loop.

[0051] System 600 also includes a calibration circuitry 602, a control logic 604, and a memory 606. The CDR 202 includes a phase detector (PD) 608 and an integrator / accumulator 610. The calibration circuitry 602 includes multiple inputs that receive a clock signal and signals from the multi-phase oscillator 206. The calibration circuitry 602 is coupled to the control logic 604 and the memory 606 and communicates with the control logic and the memory. The control logic 604 is coupled to the calibration circuitry 602, the memory 606, the CDR 202, and the delay circuitry 204. The phase detector 608 has inputs that receive input data 210 and CLK_FB 218. The phase detector 608 has an output that is coupled to an input of the integrator / accumulator 610. Also shown are CLK_INJ 612, CLK1 614, CLK2 616, the RST_INTEGRATOR signal 618 (integrator reset), and the INJECTION_SELECT signal 620. The integrator 610 has an input that receives the RST_INTEGRATOR signal 618 and an output that provides VCTRL 212 to the delay circuitry 204 and the control logic 604.

[0052] In one example, the calibration circuitry 602 includes inputs that receive an N-phase output 216 and the CLK1 614 and CLK2 616 signals. CLK1 614 is a delayed clock signal provided by the delay circuitry 204, and CLK2 616 is an undelayed clock signal provided by the delay circuitry 204. CLK1 614 has a known delay compared to CLK2 616 that is used for calibration as described below. The calibration circuitry 602 is coupled to the control logic 604 and the memory 606. In one example, the control logic 604 can be stored in the memory 606. In an example, the control logic 604 can be computer code, software, or instructions executed by a processor or a controller ( Figure 6 not shown in the figure). In other examples, the control logic 604 can be programmable logic or digital logic. The calibration circuitry 602 and the control logic 604 interact with each other to perform various functions as described herein. Further, the RST_INTEGRATOR signal 618 is shown, which is provided by the control logic 604 to the integrator / accumulator 610 to reset the integrator / accumulator 610. Also shown is the INJECTION_SELECT signal 620, which is provided by the control logic 604 to the delay circuitry 204 to change the injection clock phase of the multi-phase oscillator 206 as described herein. The control logic 604 also receives VCTRL 212 at its input from the CDR 202, and the control logic 604 uses the VCTRL to compare with the stored delay values as described below.

[0053] In an example operation, PD 608 and integrator / accumulator 610 compare input data 210 with CLK_FB 218 to produce an error between the two signals. The error is integrated to produce VCTRL 212, which changes the delay of injection clock CLK_INJ 612 within delay circuitry 204. Injection clock CLK_INJ 612 may be provided by CDR 202 on an injection clock path (e.g., the path that provides CLK_INJ 612 to delay circuitry 204 at the input of delay circuitry 204). VCTRL 212 is a signal provided by CDR 202 to delay circuitry 204 to indicate the amount of delay to be produced by delay circuitry 204 in order to align the output signal of polyphase oscillator 206. Delay circuitry 204 also receives injection clock signal CLK_INJ 612, which is used to lock polyphase oscillator 206 to the phase and / or frequency of injection clock signal CLK_INJ 612. Delay circuitry 204 receives both CLK_INJ 612 and VCTRL 212 and uses these signals to generate injection inputs (INJCLK) 214 provided to each phase of polyphase oscillator 206. INJCLK 214 is a clock signal that is at a specific frequency (set by CLK_INJ 612) and has a specific delay (set by VCTRL 212) of a selected phase provided by delay circuitry 204 to polyphase oscillator 206. The INJCLK 214 signal may be injected at any phase and, in the example, is injected at only one phase. Figure 6 Multiple inputs of polyphase oscillator 206 for receiving the INJCLK 214 signal are shown to indicate that the INJCLK 214 signal may be provided to any phase of polyphase oscillator 206. Injection is applied to any phase of polyphase oscillator 206 based on INJECTION_SELECT signal 620 from control logic 604. The selected phase that receives the INJCLK 214 signal is M-divided and fed back to CDR 202.

[0054] In an example operation, the injected phase received from the delay circuit system 204 is compared with an adjacent phase. N phases of the multiphase oscillator 206 are provided to the calibration circuit system 602, where the calibration circuit system 602 measures the delay between two phases. The injection time point can be moved forward or backward to a different phase, depending on the magnitude and direction of the delay. CLK2 616 can be undelayed, and CLK1 614 can be delayed by the VCTRL 212 input, which provides a measurement of how much VCTRL 212 is delayed. If the corrected delay is as large as the stored delay, the control logic 604 increments or decrements the INJECTION_SELECT signal 620 and resets the VCTRL 212 with the RST_INTEGRATOR signal 618. The INJECTION_SELECT signal 620 moves the injection time point to a different phase of the multiphase oscillator 206. Then, the CDR loop can continue to monitor and adjust the delay as needed, or change the injection phase using the components described herein Figure 2 and 6 in the description. Additional descriptions of the calibration circuit system 602 and the control logic 604 are provided below.

[0055] Figure 7 is a flowchart of an example method 700 for performing calibration. The operations of method 700 can be performed in any suitable order. In some instances, the calibration circuit system 602 can perform method 700. In some instances, any suitable hardware, software, or digital logic can perform method 700.

[0056] Method 700 starts at 710, where the magnitude of the delay from the delay circuit system 204 is compared with a threshold T thresh T thresh is the threshold described above with respect to operation 520. As described above, the threshold T thresh can be a value less than T VCO / N, e.g., 70% of T VCO / N. If the absolute value of the corrected delay value does not exceed the threshold T thresh , then method 700 remains at 710. If the absolute value of the corrected delay value exceeds the threshold T thresh , then method 700 proceeds to 720.

[0057] At 720, the calibration circuit system 602 selects the current injection phase k of the multiphase oscillator 206. The calibration circuit system 602 also selects an adjacent phase (k + 1 or k - 1) depending on whether the corrected delay value is positive or negative. If the delay is positive, phases k and k - 1 are selected, and if the delay is negative, phases k and k + 1 are selected.

[0058] Method 700 then proceeds to 730, where calibration circuitry 602 measures and stores the delay between two selected phases (k and k+1, or k and k-1). In one instance, the delay is stored in memory 606. The delay is stored such that it can be compared to future correction delay values to determine whether to change the injection phase of polyphase oscillator 206. In one instance, a successive approximation register (SAR) loop is used to measure the delay.

[0059] Method 700 proceeds to 740, where control logic 604 is enabled and system 600 can operate as described herein. System 600 then continues to perform injection locking and providing a delay to polyphase oscillator 206 and adjusting the delay using calibration circuitry 602 and control logic 604.

[0060] Figure 8 is a flowchart of an example method 800 for adjusting the injection phase of polyphase oscillator 206. The operations of method 800 can be performed in any suitable order. In some instances, control logic 604 can perform method 800. In some instances, any suitable hardware, software, or digital logic can perform method 800.

[0061] Method 800 begins at 810, where control logic 604 compares the correction delay based on VCTRL with the stored delay determined by calibration circuitry 602. If the correction delay value is less than the stored delay value (e.g., the correction delay value is less than the difference between adjacent phases of polyphase oscillator 206), then method 800 remains at 810. If the correction delay value is greater than the stored delay value (e.g., the correction delay value is greater than the delay between adjacent phases), then method 800 proceeds to 820.

[0062] At 820, if the delay is positive, the injection time point is moved to the previous phase (k-1). If the delay is negative (e.g., early), the injection time point is moved to the next phase (k+1). Additionally, control logic 604 provides the RST_INTEGRATOR signal 618 to CDR 202 to reset VCTRL 212 and set the delay to zero. The CDR loop containing the components described above with respect to Figure 2 and 6 then continues to monitor and correct errors using delay circuitry 204 and other components in system 600.

[0063] Figure 9 is a block diagram of an example system 900 for clock and data recovery. System 900 includes some of the components described above with respect to Figure 2 and 6 and like reference numerals represent like components.

[0064] System 900 includes a CDR 202, a delay circuit system 204 (which includes delay circuit systems 904A and 904B), a multiphase oscillator 206, and an M-divider 208. The multiphase oscillator 206 includes N delay units 902.1, 902.2, …, 902.N, also referred to as delay circuits. Input data 210, VCTRL 212, INJCLK 214 (shown as multiple injection inputs in Figure 9 ), N-phase outputs 216, and CLK-FB 218 are also shown. Figure 9 The components in are coupled together and operate as described above with respect to Figure 2 .

[0065] System 900 also includes a calibration circuit system 602, control logic 604, and a memory 606. The CDR 202 includes a phase detector 608 and an integrator / accumulator 610. CLK_INJ 612, CLK1 614, CLK2 616, an RST_INTEGRATOR signal 618 (integrator reset), and an INJECTION_SELECT signal 620 are also shown. These components are coupled together and operate as described above with respect to Figure 6 . System 900 also includes a demultiplexer 906.

[0066] Each of the delay units 902.1, 902.2, …, 902.N has an input and an output and is connected in series from 902.1 to 902.N. The output of the delay unit 902.N is coupled to the input of the delay unit 902.1. Each input of the delay units 902.2 to 902.N is also coupled to the output of the demultiplexer 906. The delay circuit system 904A has an input that receives CLK_INJ 612 and an input that receives VCTRL 212. The delay circuit system 904A has an output that provides CLK1 614 to the demultiplexer 906 and the calibration circuit system 602. The delay circuit system 904B has an input that receives CLK_INJ 612 and an input that receives a value of 0 as a delay signal. The delay circuit system 904B has an output that provides CLK2 616 to the calibration circuit system 602. Since the delay circuit system 904B receives a value of 0 as a delay signal, CLK2 616 is an undelayed signal that can be used for control and calibration as described herein.

[0067] The demultiplexer 906 receives CLK1 614 at its input and provides a delayed signal to each phase of the polyphase oscillator 206 via its plurality of outputs via the injection input (INJCLK) 214. In system 900, the polyphase oscillator 206 is a RO having N delay cells 902. The injection input (INJCLK) 214 (e.g., injection delay) is provided to each delay cell 902 via the demultiplexer 906. The delay cell 902 can include any suitable circuitry or hardware to provide a delay.

[0068] In operation, the polyphase oscillator 206 can injection lock to any harmonic of CLK_INJ 612. Generally, the frequency (f VCO ) of the polyphase oscillator 206 is equal to M times the frequency of CLK_INJ 612 (e.g., f vco = M * f inj ). The polyphase oscillator 206 has N inverter stages, and Td is the delay of each delay cell 902.

[0069] The injection clock CLK_INJ 612 is delayed by the delay circuitry 904A to generate CLK1 614 based on VCTRL 212. CLK1 614 passes through the demultiplexer 906, where the INJECTION_SELECT signal 620 specifies which phase of the polyphase oscillator 206 to apply the injection. The clock CLK_FB 218 of the divided polyphase oscillator 206 is fed back to the PD 608, which compares CLK_FB 218 with the incoming input data 210. The error determined by the PD 608 is integrated by the integrator / accumulator 610 to generate VCTRL 212.

[0070] Figure 10 is a block diagram of an example system 1000 having a calibration circuitry 602, a control logic 604, and a memory 606. These components are coupled together and operate as described above. Also shown are VCTRL 212, the N-phase output 216, CLK1 614, CLK2 616, the RST_INTEGRATOR signal 618, and the INJECTION_SELECT signal 620.

[0071] The calibration circuit system 602 includes a toggle multiplexer (toggle MUX) 1002, a multiplexer 1 (MUX1) 1004, a multiplexer 2 (MUX2) 1006, a multiplexer 3 (MUX3) 1008, and a multiplexer 4 (MUX4) 1010. The calibration circuit system 602 includes a delay unit 1012, a delay calibration unit (or circuit system) 1014, a delay calibration unit (or circuit system) 1016, a comparator 1018, and an integrator / accumulator 1020. Various signals are also shown, such as CLK1_IN 1022, CLK2_IN 1024, RO_PATH1 1026, RO_PATH2 1028, CLKP1 1030, CLKP2 1032, CMPIN1 1034, CMPIN2 1036, CAL_CODE 1038, SEL_CAL_MODE 1040, SEL_RO_PATH1 1042, SEL_RO_PATH2 1044, and SEL_DIRECTION 1046. The select inputs of the multiplexers described herein may be coupled to a processor or a controller ( Figure 10 not shown), or coupled to hardware or digital logic configured to control the multiplexers and perform the operations described herein ( Figure 10 not shown). The control logic 604 may control the select inputs of the multiplexers described herein.

[0072] The toggle MUX 1002 has two inputs coupled to a delay circuit system 204 ( Figure 10 not shown). The toggle MUX 1002 has two outputs coupled to the MUX3 1008 and the MUX4 1010. The toggle MUX 1002 has a select input controlled by the control logic 604. The MUX1 1004 has an input coupled to a polyphase oscillator 206 ( Figure 10 not shown), an output coupled to the input of the MUX3 1008, and a select input controlled by the control logic 604. The MUX2 1006 has an input coupled to the polyphase oscillator 206, an output coupled to the input of the MUX4 1010, and a select input controlled by the control logic 604.

[0073] MUX3 1008 has two inputs that are coupled to the output of MUX1 1004 and the output of the flip MUX 1002. MUX3 1008 has an output that is coupled to the input of the delay calibration unit 1014. MUX3 1008 has a select input that is controlled by the control logic 604. MUX4 1010 has two inputs that are coupled to the output of MUX2 1006 and the output of the flip MUX 1002. MUX4 1010 has an output that is coupled to the input of the delay unit 1012. MUX4 1010 has a select input that is controlled by the control logic 604. The delay unit 1012 has an output that is coupled to the delay calibration unit 1016.

[0074] The delay calibration unit 1014 has a second input that receives 0 delay and an output that is coupled to the comparator 1018. The delay calibration unit 1016 has an input that is coupled to the delay unit 1012 and an input that is coupled to the integrator / accumulator 1020. The delay calibration unit 1016 has an output that is coupled to the comparator 1018. The comparator 1018 has an output that is coupled to the input of the integrator / accumulator 1020. The comparator 1018 also provides an output signal to the control logic 604.

[0075] The flip MUX 1002 has two inputs, a first input that receives CLK1 614 and a second input that receives CLK2 616. The flip MUX 1002 has a select input that receives SEL_DIRECTION 1046. The flip MUX 1002 has a first output that provides CLK1_IN 1022 to the input of MUX3 1008, and a second output that provides CLK2_IN 1024 to the input of MUX4 1010.

[0076] MUX1 1004 has an input that receives the N-phase output 216 and a select input that receives SEL_RO_PATH1 1042 from the control logic 604. MUX1 1004 has an output that provides RO_PATH1 1026 to the input of MUX3 1008. MUX2 1006 has an input that receives the N-phase output 216 and a select input that receives SEL_RO_PATH2 1044 from the control logic 604. MUX2 1006 has an output that provides RO_PATH2 1028 to the input of MUX4 1010.

[0077] As described above, MUX3 1008 has an input coupled to the output of the flip MUX 1002 and an input coupled to the output of MUX1 1004. MUX3 1008 has a selection input that receives SEL_CAL_MODE 1040 from the control logic 604. MUX 3 1008 has an output that provides CLKP1 1030 to the delay calibration unit 1014. As described above, MUX4 1010 has an input coupled to the output of the flip MUX 1002 and an input coupled to the output of MUX2 1006. MUX4 1010 has a selection input that receives SEL_CAL_MODE 1040 from the control logic 604. MUX4 1010 has an output that provides a signal to the delay unit 1012. The delay unit 1012 has an output that provides the signal CLKP2 1032 to the delay calibration unit 1016.

[0078] The delay calibration unit 1014 receives the CLKP1 1030 signal from MUX3 1008 and receives a zero calibration input. The delay calibration unit 1014 provides the output signal CMPIN1 1034 to the comparator 1018. The delay calibration unit 1016 receives the CLKP2 1032 signal from the delay unit 1012 and receives the calibration input CAL_CODE 1038 from the integrator / accumulator 1020. The delay calibration unit 1014 provides the output signal CMPIN2 1036 to the comparator 1018. The comparator 1018 provides the output signal to the control logic 604 and to the integrator / accumulator 1020. The integrator / accumulator 1020 receives the output at its input from the comparator 1018 and provides CAL_CODE 1038 to the delay calibration unit 1016 at its output.

[0079] The control logic 604 receives VCTRL 212 at a first input and receives a signal from the comparator 1018 at a second input. The control logic 604 provides a plurality of signals, including the RST_INTEGRATOR signal 618, the INJECTION_SELECT signal 620, SEL_CAL_MODE 1040, SEL_RO_PATH1 1042, SEL_RO_PATH2 1044, and SEL_DIRECTION 1046.

[0080] In operation, the calibration circuitry performs calibration between two phases of the polyphase oscillator 206 as described herein. In one example, two phases from the polyphase oscillator 206 are selected for comparison. In one example, the delay cell 1012 in the calibration circuitry 602 is the same type of delay cell 902 found in the polyphase oscillator 206. If there is no mismatch (e.g., due to process, temperature, etc.), the delays from the delay cell 902 and the delay cell 1012 are the same. After performing the calibration, the delayed clock (CLK1 614) and the undelayed clock (CLK2 616) are made to pass through the same path using the delay cell 1012 and the CAL_CODE 1038 from the calibration. The time point at which the comparator 1018 toggles is the time point at which the delay on CLK1 614 (generated by VCTRL 212) is exactly the same as the delay between the two selected phases of the polyphase oscillator 206 compared to CLK2 616 which has zero delay. In this example, two phases of the RO are selected, and the earlier phase (e.g., the one that comes before the other selected phase among the selected phases) is delayed by using the delay cell 1012. The calibration circuitry 602 performs calibration until the clocks are aligned, and then CLK1 614 and CLK2 616 pass through the same path. Since the same path is used, no mismatch error occurs.

[0081] In a more detailed example, when the delay generated by the delay circuitry 204 reaches a threshold close to ±Td (the delay generated by the delay cell 902), the calibration circuitry 602 compares the current phase and the previous / next phase of the polyphase oscillator 206 based on the polarity of the correction delay. In one example, the threshold is 90% of Td, but in other examples other thresholds are useful, such as 80% or 95%. The delay is provided by the value of VCTRL 212, so the CDR 202 can determine whether the delay has reached the threshold by monitoring the value of VCTRL 212. The output signal provided by the comparator 1018 is integrated by the integrator / accumulator 1020 to generate the CAL_CODE 1038, which indicates information about the delay between the two selected phases.

[0082] First, set SEL_CAL_MODE 1040 to 1 through control logic 604. When SEL_CAL_MODE 1040 is set to 1, MUX1 1004 and MUX2 1006 select the corresponding phases of the polyphase oscillator 206 to be calibrated. The codes of SEL_RO_PATH1 1042 and SEL_RO_PATH2 1044 are selected by control logic 604 based on the error provided to control logic 604 by PD 608 via VCTRL 212. The codes are selected such that RO_PATH1 1026 is delayed with respect to RO_PATH2 1028.

[0083] Since the delay between subsequent phases is Td, delaying RO_PATH2 1028 by Td (using delay unit 1012) makes CLKP1 1030 and CLKP2 1032 be in substantially the same phase. Calibrate the residual mismatch between the selected delay units 902 (corresponding to the selected phases) using delay calibration unit 1016. The range requirement of delay calibration unit 1016 is to reduce from Td to only the mismatch between the selected delay units 902 in the polyphase oscillator 206. Compare clock CLKP1 1030 and CLKP2 1032 using comparator 1018, and integrator / accumulator 1020 changes the calibration code CAL_CODE 1038 by adjusting the integration signal provided at the output of integrator / accumulator 1020.

[0084] After calibration is completed, control logic 604 sets SEL_CAL_MODE 1040 to zero, and CLK1 614 and CLK2 616 pass through the same path as the above RO signals (through the selection of MUX3 1008 and MUX4 1010, and then through the path provided by delay unit 1012, delay calibration unit 1014, and delay calibration unit 1016). Use CAL_CODE 1038 from the previous calibration.

[0085] Derive CLK2 616 by passing CLK_INJ 612 through delay circuit path 904B, whose control voltage is 0 (see Figure 9 ). Flip MUX 1002 to flip CLK1 614 and CLK2 616 between different paths (MUX3 1008 or MUX4 1010) according to the polarity of VCTRL 212.

[0086] When the comparator 1018 switches, the calibration delay exceeds the stored delay. The switching of the comparator 1018 is provided to the control logic 604, and the control logic 604 increments or decrements the INJECTION_SELECT signal 620 to change the phase of the injection clock provided to the polyphase oscillator 206. The control logic 604 also activates the RST_INTEGRATOR 618 to reset the VCTRL 212 value provided by the CDR 202.

[0087] Figure 11 is a flowchart of an example method 1100 for calibration. The operations of the method 1100 can be performed in any suitable order. In some instances, the calibration circuitry 602 and / or the control logic 604 can perform the method 1100. In some instances, any suitable hardware, software, or digital logic can perform the method 1100.

[0088] The method 1100 performs calibration upon power-up and stores the phase delay between the phases of the polyphase oscillator 206 in a look-up table (LUT). In one instance, the LUT can be stored in the memory 606. If the calibration delay is to be compared with the stored delay, the calibration code CAL_CODE 1038 is read out from the LUT and the comparison is performed. In some instances, a new calibration can be performed (instead of reading out the stored value from the LUT), and the LUT can be updated at that time. The method can save power because the calibration is not run redundantly. Another advantage is that any mismatch in the injection path delay between each phase is eliminated because all adjacent phase pairs are calibrated.

[0089] The method 1100 starts at 1110, where the system 600 (or other systems described herein, such as system 200) starts operation and implements injection at phase k = 0 of the polyphase oscillator 206. The method 1100 then continues to 1120, where the calibration circuitry 602 measures the delay between phases k and k+1.

[0090] The method 1100 continues to 1130, where the LUT is updated with a calibration code (CAL_CODE) that indicates information about the delay between two phases (k and k+1). In one instance, the LUT can be stored in the memory 606.

[0091] The method 1100 continues to 1140, where the calibration circuitry measures the delay between phases k and k-1. The method 1100 continues to 1150, where the LUT is updated with the calibration code for phases k and k-1.

[0092] Method 1100 proceeds to 1160, where delay circuitry 204 determines whether k = N - 1 is satisfied. Thus, delay circuitry 204 or control logic 604 determines whether phase k is the last phase of the multiphase oscillator 206. If k is not the last phase, method 1100 proceeds to 1180. If k is the last phase, method 1100 proceeds to 1170.

[0093] At 1180, if k is not the last phase, k is incremented to k + 1, and method 1100 returns to 1120. Then, method 1100 determines the calibration code for the next phase, just as it did for the previous phase. In one example, the calibration code is determined by calibration circuitry 602 and stored in a LUT in memory 606. The process continues until calibration has been performed for each phase.

[0094] If k = N - 1 at 1160, method 1100 proceeds to 1170. At 1170, the calibration and LUT filling process using method 1100 ends. The calibration codes are stored for each phase and those codes can be read from the LUT as needed during operation of system 600.

[0095] Figure 12 is a flowchart of an example method 1200 for calibration and selection of injection phases. The operations of method 1200 can be performed in any suitable order. In some examples, calibration circuitry 602 and / or control logic 604 can perform method 1200. In some examples, any suitable hardware, software, or digital logic can perform method 1200.

[0096] Method 1200 begins at 1210, where control logic 604 determines whether the absolute value of the delay is greater than T thresh . As described above, the threshold T thresh can be a value less than T VCO / N, such as 70% of T VCO / N. If the absolute value of the corrected delay value is less than the threshold T thresh , method 1200 remains at 1210. If the absolute value of the corrected delay value exceeds the threshold T thresh , method 1200 proceeds to 1220.

[0097] At 1220, control logic 604 determines whether calibration is needed as required. If there is no calibration code stored for the current phase k, calibration is needed and method 1200 proceeds to 1240. If the calibration code is stored in the LUT, calibration is not needed and method 1200 proceeds to 1230.

[0098] At 1230, calibration is not required, and the calibration code corresponding to the phase is read from the LUT. After 1230, method 1200 proceeds to 1270.

[0099] At 1220, if calibration is required, method 1200 proceeds to 1240. At 1240, calibration circuitry 602 selects the current injection phase k of polyphase oscillator 206. Calibration circuitry 602 also selects an adjacent phase (k + 1 or k - 1) depending on whether the correction delay value is positive or negative. If the delay is positive, phases k and k - 1 are selected, and if the delay is negative, phases k and k + 1 are selected.

[0100] Method 1200 then proceeds to 1250, where calibration circuitry 602 measures and stores the delay between the two selected phases (k and k + 1, or k and k - 1). At 1260, the delay is stored in the LUT. In one example, the LUT may be stored in memory 606. The delay is stored such that it can be compared with future correction delay values to determine whether to change the injection phase of polyphase oscillator 206. In one example, a successive approximation register (SAR) loop is used to measure the delay.

[0101] After updating the LUT at 1260, method 1200 proceeds to 1270. At 1270, control logic 604 determines whether the correction delay is greater than the stored delay. If it is not greater, since the injection phase does not need to be updated, the method can remain at 1270. If the correction delay is greater than the stored delay in the LUT, method 1200 proceeds to 1280.

[0102] At 1280, control logic 604 updates the injection selection code (INJECTION_SELECT signal 620). If the delay is positive, the injection time point is moved to the previous phase (k - 1). If the delay is negative (e.g., early), the injection time point is moved to the next phase (k + 1). Additionally, control logic 604 provides the RST_INTEGRATOR signal 618 to CDR202 to reset VCTRL 212 and set the delay to zero. Then, the CDR loop continues to monitor and correct errors using delay circuitry 204 and other components in system 600.

[0103] Figure 13 is a flowchart of an example method 1300 for updating the delay provided by delay circuitry 204. The operations of method 1300 can be performed in any suitable order. In some examples, the hardware components described above with respect to Figure 1-2 6 and 9 - 10 can perform method 1300. In some examples, any suitable hardware, software, or digital logic can perform method 1200.

[0104] Method 1300 begins at 1310, where delay circuitry 204 provides a delay on an injection clock path to a first phase of a multiphase oscillator 206. In one example, the multiphase oscillator 206 can be a ring oscillator. The delay circuitry 204 can be any suitable circuitry or hardware for delaying a clock signal provided to the multiphase oscillator 206 as an input.

[0105] Method 1300 proceeds to 1320, where a CDR loop or CDR circuitry determines to update the delay using a correction value. The CDR circuitry (e.g., CDR 202) can determine to update the delay due to a difference between input data 210 and CLK_FB 218.

[0106] Method 1300 proceeds to 1330, where control logic 604 determines whether the correction value is less than a threshold. If the correction value is less than the threshold, the CDR 202 changes the delay by adjusting a control signal (e.g., VCTRL 212) provided to the delay circuitry 204. The delay can be adjusted in either direction (positive or negative).

[0107] Method 1300 proceeds to 1340, where control logic 604 determines that the correction value exceeds the threshold. If the correction value exceeds the threshold, the control logic 604 changes an injection time point of the delay circuitry 204 to a second phase of the multiphase oscillator 206. The threshold can be a delay difference between the first phase and an adjacent phase of the multiphase oscillator 206. If the correction value is greater than the threshold, the control logic 604 instructs the delay circuitry 204 to change the injection time point to an adjacent phase of the multiphase oscillator 206. The threshold between adjacent phases of the multiphase oscillator 206 can be stored in a memory 606 or a look-up table.

[0108] In an example herein, a phase interpolator is not used because all phases equivalently delay an input injection delay. Only ±T VCO / N delay is used on an input side of the multiphase oscillator 206. Due to a filtering effect of an injection-locked multiphase oscillator, a jitter specification on the delay unit or delay circuitry 204 is much looser. Accordingly, power and area usage of the delay circuitry 204 also becomes looser.

[0109] The calibration scheme described herein also provides some example advantages. For cases where the error between the input data and the output clock is small, the phase drift will be slower. The calibration circuitry 602 can be used only after the delay is significantly larger. This duty cycle of the calibration circuitry 602 can save power. The calibration and control logic paths are the same, so offsets and mismatches such as comparator offset, RO cell delay mismatch, and path delay mismatch are taken into account. This solution also saves area and power because the path is reused.

[0110] In some instances, compared to other systems, the specifications regarding comparator offset, calibration delay cell range, and power consumption are relaxed. Additionally, since the delay is calibrated for each injection time point, any mismatch between any RO phases does not affect linearity. The linearity is better in the examples herein compared to systems with output phase interpolators. The examples described herein can be implemented in high-speed serializer / deserializers. Other examples may be useful in high-speed digital video interfaces such as flat panel display links (FPD links). FPD links are used in various applications such as connecting the output of a graphics processing unit (GPU) to a display panel. FPD links can also be used in automotive applications such as navigation systems, vehicle entertainment systems, and backup cameras, as well as advanced driver assistance systems and autonomous vehicles.

[0111] In this specification, the term "coupled" may cover connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0112] A device "configured to" perform a task or function can be configured (e.g., programmed and / or hardwired) by the manufacturer to perform the function at the time of manufacture, and / or can be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. The configuration can be achieved through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnects of the device, or a combination thereof.

[0113] A circuit or apparatus described herein as including certain components may alternatively be coupled to those components to form the described circuitry or apparatus. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be coupled to at least some of the passive elements and / or sources to form the described structure during or after manufacture, e.g., by an end user and / or a third party.

[0114] In this specification, unless otherwise stated, "about," "substantially," or "essentially" before a parameter means within + / - 10% of the stated parameter. Modifications to the described examples are possible within the scope of the claims, and other examples are possible.

Claims

1. A circuit comprising: A clock data recovery (CDR) circuit system having an input and an output; a delay circuit having an input coupled to the output of the CDR circuitry and having an output; a multiphase oscillator having an input coupled to the output of the delay circuit and having an output; as well as A frequency divider has an input coupled to the output of the multiphase oscillator and has an output coupled to the input of the CDR circuitry.

2. The circuit of claim 1, wherein the multiphase oscillator is a ring oscillator.

3. The circuit of claim 1, wherein the CDR circuitry comprises a phase detector and an integrator.

4. The circuit of claim 1, wherein the input to the delay circuit is a voltage controlled input.

5. The circuit of claim 1, wherein the delay circuit comprises a multiplexer output and the multiphase oscillator comprises a plurality of inputs coupled to the multiplexer output.

6. The circuit of claim 1, wherein the output of the multiphase oscillator is coupled to an input of calibration circuitry.

7. The circuit of claim 6, wherein the calibration circuitry has an input coupled to the delay circuit and an output coupled to the CDR circuitry.

8. The circuit of claim 1, wherein the delay circuit comprises a second input coupled to an injected clock path.

9. A circuit comprising: A clock data recovery (CDR) circuit system having an input and an output; a delay circuit having an input coupled to the output of the CDR circuitry and having an output; a multiphase oscillator having an input coupled to the output of the delay circuit and having an output; a frequency divider having an input coupled to the output of the multiphase oscillator and having an output coupled to the input of the CDR circuitry; as well as A calibration circuit has first, second and third inputs, the first and second inputs being coupled to the output of the delay circuit and the third input being coupled to the output of the multiphase oscillator.

10. The circuit of claim 9, wherein the CDR circuitry comprises a phase detector having an input coupled to the output of the frequency divider.

11. The circuit of claim 10, wherein the phase detector has an output coupled to an input of an integrator / accumulator, and wherein the integrator / accumulator has an output coupled to the delay circuit.

12. The circuit of claim 9, wherein the multiphase oscillator is a ring oscillator.

13. The circuit of claim 9, wherein the calibration circuit comprises a multiplexer coupled to a third input thereof, the multiplexer having an input coupled to the output of the multiphase oscillator and an output coupled to a second multiplexer.

14. The circuit of claim 13, wherein the calibration circuit comprises a second delay circuit and delay calibration circuitry.

15. The circuit of claim 14, wherein the calibration circuit comprises a comparator having a first input coupled to the first delay calibration circuit and a second input coupled to the second delay calibration circuit, and having an output coupled to the input of the integrator.

16. A method comprising: providing a delay from a delay circuit to a first phase of a multiphase oscillator on an injected clock path; determining to update the delay with a correction value; if the correction value is less than a threshold, modifying the delay in response to a control signal provided to the delay circuit; as well as If the correction value exceeds the threshold, the injection time point of the delay circuit is changed to a second phase of the multi-phase oscillator.

17. The method of claim 16, wherein the threshold is based on a clock period divided by the number of phases in the multiphase oscillator.

18. The method according to claim 16, further comprising: responsive to determining to update the delay, determining whether calibration has been performed; performing the calibration to calculate phase delays between phases of the multiphase oscillator if the calibration has not already been performed; as well as If the calibration has been performed, the delay is altered using the control signal provided to the delay circuit.

19. The method of claim 16, wherein the delay on the injected clock path delays each phase of the multiphase oscillator.

20. The method of claim 16, wherein the threshold is determined for each adjacent phase of the multiphase oscillator.

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