Bias driving circuit suitable for bipolar process, control method and digital-to-analog converter

Abstract

The invention provides a bias drive circuit suitable for a bipolar process, a control method and a digital-to-analog converter, the bias drive circuit comprises a bias generation module and a compensation module, the bias generation module generates a bias voltage, when a to-be-driven load changes, a corresponding initial compensation current is generated, and when the to-be-driven load changes, the to-be-driven load changes, the to-be-driven load changes; and mirroring the initial compensation current and adjusting the current to obtain a target compensation current so as to stabilize the bias voltage through the target compensation current. According to the bias driving circuit suitable for the bipolar process, when the driving load is increased, the target compensation current needed for increasing the load is generated through the compensation module, the influence on the bias voltage is reduced, the driving capacity of the bias driving circuit is improved, the bias driving circuit can be applied to a high-resolution current-steering DAC, a stable bias is provided for the DAC, and the reliability of the DAC is improved. And the stability of the DAC is improved.

Description

Technical Field

[0001] The present invention relates to the design of monolithic integrated circuits for digital-to-analog converters, and particularly to a bias driving circuit applicable to bipolar processes, a control method thereof, and a digital-to-analog converter. Background Art

[0002] In the field of signal processing, the performance of high-speed and high-precision digital-to-analog converters has largely become the bottleneck of the entire system. The current-steering DAC (Digital to Analog Converter), that is, the current-driven steering-type digital-to-analog converter, is widely used for its advantages such as high speed and high precision. In the current-driven steering-type digital-to-analog converter using bipolar processes, since there is current in the base of the triode, in a large-scale current source array, after the load changes, it will inversely affect the bias voltage, and further affect the resolution of the digital-to-analog converter.

[0003] Therefore, how to provide a bias driving circuit with a bias voltage that does not fluctuate with the change of the load is a technical problem that needs to be solved urgently at present. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the present invention provides a bias driving circuit applicable to bipolar processes to solve at least one of the above-mentioned technical problems.

[0005] To achieve the above object and other related objects, the technical solutions provided in this application are as follows.

[0006] According to the first aspect of the embodiments of the present application, a bias driving circuit applicable to bipolar processes is provided, including:

[0007] A bias generation module for generating a bias voltage;

[0008] A compensation module connected to the bias generation module, generating an initial compensation current according to the change of the load to be driven, mirroring and adjusting the size of the initial compensation current to obtain a target compensation current, so as to keep the bias voltage stable through the target compensation current.

[0009] In an embodiment of the present invention, the bias generation module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NPN transistor, a second NPN transistor, a third NPN transistor, a first resistor and a second resistor. The source of the first PMOS transistor is connected to the power supply voltage. The drain of the first PMOS transistor is connected to the collector of the first NPN transistor. The emitter of the first NPN transistor is grounded through the first resistor. The first end of the second resistor is connected to the power supply voltage. The second end of the second resistor is connected to the gate of the second PMOS transistor. The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor. The second end of the second resistor is also connected to the source of the third PMOS transistor. The source of the second PMOS transistor is connected to the power supply voltage. The drain of the second PMOS transistor is connected to the gate of the third PMOS transistor. The drain of the second PMOS transistor is also connected to the collector of the third NPN transistor. The base of the third NPN transistor is connected to the base of the second NPN transistor. The drain of the third PMOS transistor is connected to the collector of the second NPN transistor. The collector of the second NPN transistor is connected to the base of the second NPN transistor. The emitter of the second NPN transistor is connected to the emitter of the third NPN transistor. The emitter of the second NPN transistor is also grounded. Wherein, the collector and the base of the first NPN transistor cooperate to output the bias voltage externally.

[0010] In an embodiment of the present invention, the ratio of the size of the second PMOS transistor to the size of the first PMOS transistor is n, and the sizes of the second NPN transistor and the third NPN transistor are equal.

[0011] In an embodiment of the present invention, the compensation module includes a first NMOS transistor, a second NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth NPN transistor, and a fifth NPN transistor. The collector of the fourth NPN transistor is connected to the power supply voltage, the emitter of the fourth NPN transistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor, the source of the first NMOS transistor is connected to the source of the second NMOS transistor, the source of the second NMOS transistor is grounded, the source of the fourth PMOS transistor is connected to the collector of the fourth NPN transistor, the gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor, the gate of the fourth PMOS transistor is further connected to the base of the fourth NPN transistor, the drain of the fourth PMOS transistor is connected to the base of the fourth NPN transistor, the source of the fifth PMOS transistor is connected to the source of the fourth PMOS transistor, the drain of the fifth PMOS transistor is connected to the base of the fifth NPN transistor, the source of the sixth PMOS transistor is connected to the source of the fifth PMOS transistor, the source of the sixth PMOS transistor is further connected to the source of the seventh PMOS transistor, the gate of the sixth PMOS transistor is connected to the gate of the seventh PMOS transistor, the drain of the sixth PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the seventh PMOS transistor is connected to the drain of the seventh PMOS transistor, and the drain of the seventh PMOS transistor is connected to the collector of the fifth NPN transistor. Wherein, the base and emitter of the fifth NPN transistor are connected to the bias generation module.

[0012] In an embodiment of the present invention, the size of the first NMOS transistor is equal to the size of the second NMOS transistor, the size of the fourth PMOS transistor is equal to the size of the fifth PMOS transistor, and the size of the sixth PMOS transistor is equal to the size of the seventh PMOS transistor.

[0013] According to the second aspect of the embodiments of the present application, a control method for a bias driving circuit applicable to a bipolar process is provided, including:

[0014] Providing a bias voltage and obtaining load driving parameters corresponding to the bias voltage and target driving parameters of a load to be driven;

[0015] Generating an initial compensation current according to the load driving parameters and the target driving parameters;

[0016] Performing mirror processing on the initial compensation current and adjusting its magnitude to obtain a target compensation current, so as to stabilize the bias voltage through the target compensation current.

[0017] In an embodiment of the present invention, generating an initial compensation current according to the load driving parameter and the target driving parameter includes: determining a load change difference according to the target driving parameter and the load driving parameter; generating an initial compensation current according to the load change difference.

[0018] In an embodiment of the present invention, mirror processing and size adjustment are performed on the initial compensation current to obtain a target compensation current, including: performing two mirror processes on the initial compensation current to obtain a mirror compensation current; first performing multiple adjustment on the mirror compensation current and then performing mirror processing to obtain a target compensation current.

[0019] In an embodiment of the present invention, providing a bias voltage includes: generating a branch current, performing mirror amplification on the branch current to obtain a mirror branch current; generating the bias voltage according to the mirror branch current and the branch current.

[0020] According to the second aspect of the embodiments of the present application, a digital-to-analog converter is further provided, and the digital-to-analog converter includes a bias driving circuit applicable to a bipolar process as described above.

[0021] The present application provides a bias driving circuit applicable to a bipolar process, a control method, and a digital-to-analog converter. The bias driving circuit includes a bias generation module and a compensation module. The bias generation module generates a bias voltage. When the load to be driven changes, a corresponding initial compensation current is generated. Mirror processing and current size adjustment are performed on the initial compensation current to obtain a target compensation current, so as to stabilize the bias voltage through the target compensation current. When the load driven by the bias driving circuit applicable to the bipolar process provided by the present application increases, the compensation module generates a target compensation current required for the increased load, reduces the influence on the bias voltage, improves the driving ability of the bias driving circuit, and can be applied to a high-resolution current-steering DAC to provide a stable bias for the DAC and improve the stability of the DAC.

[0022] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0024] Figure 1 is a block diagram of a bias driving circuit applicable to a bipolar process shown in an exemplary embodiment of the present invention;

[0025] Figure 2 It is the specific circuit structure of the bias driving circuit applicable to the bipolar process shown in an exemplary embodiment of the present invention;

[0026] Figure 3 It is a schematic diagram of the compensation current transmission path in the bias driving circuit shown in an exemplary embodiment of the present invention;

[0027] Figure 4 It is a schematic diagram showing the change of the output terminal voltage of the bias generation module with and without the compensation template along with the load in an exemplary embodiment of the present invention;

[0028] Figure 5 It is a schematic diagram showing the change of the output terminal current of the bias generation module with and without the compensation template along with the load in an exemplary embodiment of the present invention. Detailed implementation manners

[0029] The following will illustrate the implementation manners of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, rather than for limiting the protection scope of the present invention.

[0030] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0031] In the following description, a large number of details are explored to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0032] In the field of signal processing, the performance of high-speed and high-precision digital-to-analog converters has largely become the bottleneck of the entire system. The current-steering DAC (Digital to Analog Converter), that is, the current-driven steering digital-to-analog converter, is widely used due to its advantages such as high speed and high precision. In the current-driven steering digital-to-analog converter with bipolar process, since there is current in the base of the triode, in a large-scale current source array, after the load changes, it will inversely affect the bias voltage, and further affect the resolution of the digital-to-analog converter.

[0033] To solve the above problems, as Figure 1 shown, the present application provides a bias driving circuit applicable to the bipolar process, including:

[0034] A bias generation module for generating a bias voltage VB1;

[0035] A compensation module, connected to the bias generation module, generating an initial compensation current i according to the change of the load to be driven, mirroring and adjusting the size of the initial compensation current i to obtain a target compensation current i / β, so as to keep the bias voltage VB1 stable through the target compensation current i / β.

[0036] Specifically, the bias voltage generation module includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a first resistor R1 and a second resistor R2. The source of the first PMOS transistor M1 is connected to the power supply voltage VCC, the drain of the first PMOS transistor M1 is connected to the collector of the first NPN transistor Q1, the emitter of the first NPN transistor Q1 is grounded through the first resistor R1, the first end of the second resistor R2 is connected to the power supply voltage VCC, the second end of the second resistor R2 is connected to the gate of the second PMOS transistor M2, the gate of the second PMOS transistor M2 is connected to the gate of the first PMOS transistor M1, the second end of the second resistor R2 is also connected to the source of the third PMOS transistor M3, the source of the second PMOS transistor M2 is connected to the power supply voltage VCC, the drain of the second PMOS transistor M2 is connected to the gate of the third PMOS transistor M3, the drain of the second PMOS transistor M2 is also connected to the collector of the third NPN transistor Q3, the base of the third NPN transistor Q3 is connected to the base of the second NPN transistor Q2, the drain of the third PMOS transistor M3 is connected to the collector of the second NPN transistor Q2, the collector of the second NPN transistor Q2 is connected to the base of the second NPN transistor Q2, the emitter of the second NPN transistor Q2 is connected to the emitter of the third NPN transistor Q3, and the emitter of the second NPN transistor Q2 is also grounded. Among them, the collector and the base of the first NPN transistor Q1 cooperate to output the bias voltage VB1 externally.

[0037] More specifically, the size ratio of the second PMOS transistor M2 to the first PMOS transistor M1 is n, and the sizes of the second NPN transistor Q2 and the third NPN transistor Q3 are equal.

[0038] More specifically, the compensation module includes a first NMOS transistor N1, a second NMOS transistor N2, a fourth PMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, a fourth NPN transistor Q4, and a fifth NPN transistor Q5. The collector of the fourth NPN transistor Q4 is connected to the power supply voltage VCC. The emitter of the fourth NPN transistor Q4 is connected to the drain of the first NMOS transistor N1. The gate of the first NMOS transistor N1 is connected to the gate of the second NMOS transistor N2. The source of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2. The source of the second NMOS transistor N2 is grounded. The source of the fourth PMOS transistor M4 is connected to the collector of the fourth NPN transistor Q4. The gate of the fourth PMOS transistor M4 is connected to the gate of the fifth PMOS transistor M5. The gate of the fourth PMOS transistor M4 is also connected to the base of the fourth NPN transistor Q4. The drain of the fourth PMOS transistor M4 is connected to the base of the fourth NPN transistor Q4. The source of the fifth PMOS transistor M5 is connected to the source of the fourth PMOS transistor M4. The drain of the fifth PMOS transistor M5 is connected to the base of the fifth NPN transistor Q5. The source of the sixth PMOS transistor M6 is connected to the source of the fifth PMOS transistor M5. The source of the sixth PMOS transistor M6 is also connected to the source of the seventh PMOS transistor M7. The gate of the sixth PMOS transistor M6 is connected to the gate of the seventh PMOS transistor M7. The drain of the sixth PMOS transistor M6 is connected to the drain of the second NMOS transistor N2. The gate of the seventh PMOS transistor M7 is connected to its drain. The drain of the seventh PMOS transistor M7 is connected to the collector of the fifth NPN transistor Q5. Among them, the base and emitter of the fifth NPN transistor Q5 are connected to the bias generation module. The base of the fifth NPN transistor Q5 is connected to the collector of the first NPN transistor Q1. The emitter of the fifth NPN transistor Q5 is connected to the base of the first NPN transistor Q1.

[0039] More specifically, the sizes of the first NMOS transistor N1 and the second NMOS transistor N2 are equal. The sizes of the fourth PMOS transistor M4 and the fifth PMOS transistor M5 are equal. The sizes of the sixth PMOS transistor M6 and the seventh PMOS transistor M7 are equal.

[0040] As Figures 1 to 5 shown, the working principle of the bias driving circuit applicable to the bipolar process provided by this application is as follows:

[0041] Combined with Figures 1 to 2As shown, the bias generation module generates a branch current I in a branch including the first PMOS transistor M1 based on the power supply voltage VCC, amplifies the branch current I through the size relationship between the first PMOS transistor M1 and the second PMOS transistor M2, and the amplified current is nI. Then, through the mirror structure composed of the second NPN transistor Q2 and the third NPN transistor Q3, the amplified current is mirror-copied to form an nI current in the branch including the second resistor R2. The magnitude of the current can be adjusted by changing the value of n or the second resistor R2. The bias generation module finally generates a bias voltage VB1 between the collector and the base of the first NPN transistor Q1, and the bias voltage VB1 is output from the base of the first NPN transistor Q1.

[0042] Assume that when the number of loads increases, the current at the emitter of the fifth NPN transistor Q5 increases by i. If the fifth NPN transistor Q5 operates normally, the base current of the fifth NPN transistor Q5 should increase by i / β, where β is the amplification factor of the fifth NPN transistor Q5. As Figure 3 shown, when the emitter current of the fifth NPN transistor Q5 increases by i, the seventh PMOS transistor M7 generates a corresponding initial compensation current i. The initial compensation current i is mirror-processed through the mirror structure composed of the seventh PMOS transistor M7 and the sixth PMOS transistor, and the mirror structure composed of the first NMOS transistor N1 and the second NMOS transistor N2. The current flowing through the first NMOS transistor N1 is the initial compensation current i. The magnitude of the current flowing through the first NMOS transistor N1 is adjusted by the fourth NPN transistor Q4, and a target compensation current i / β is obtained at the base of the fourth NPN transistor Q4. The target compensation current i / β is mirror-processed through the mirror structure composed of the fourth PMOS transistor M4 and the fifth PMOS transistor M5, so that the current of the fifth PMOS transistor M5 increases by i / β. This target compensation current i / β just meets the increased current i / β required by the base of the fifth NPN transistor Q5. Therefore, the base of the fifth NPN transistor Q5 does not need to draw current from the collector of the first NPN transistor Q1, and the emitter of the fifth NPN transistor Q5 does not need to draw current from the base of the first NPN transistor Q1 either. As a result, the voltage between the collector and the base of the first NPN transistor Q1 is stabilized, thereby improving the driving ability of the bias circuit and providing a stable bias voltage VB1 for the circuit.

[0043] As Figure 4 shown, the output voltage of the bias generation module changes with the load with and without the compensation module, that is, the bias voltage VB1 changes with the load. It can be seen that when the number of loads increases, the bias voltage VB1 of the circuit with the compensation module remains unchanged, while the bias voltage VB1 of the circuit without the compensation module decreases with the increase in the number of loads. As Figure 5As shown, the output current of the bias generation module with and without the compensation module varies with the load. It can be seen that when the number of loads increases, the output current of the bias generation module without the compensation module remains basically unchanged, while the output current of the bias generation module with the compensation module increases with the increase in the number of loads.

[0044] In the second aspect of the present application, the present application further provides a control method for a bias driving circuit applicable to a bipolar process. The method includes:

[0045] Providing a bias voltage VB1 and obtaining the load driving parameters corresponding to the bias voltage VB1 and the target driving parameters of the load to be driven;

[0046] Generating an initial compensation current according to the load driving parameters and the target driving parameters;

[0047] Performing mirror processing on the initial compensation current and adjusting its magnitude to obtain a target compensation current, so as to stabilize the bias voltage VB1 through the target compensation current.

[0048] Specifically, a bias voltage VB1 is provided by a bias generation module, and the load driving parameters for driving the load are determined according to the magnitude of the bias voltage VB1, and the target driving parameters of the load to be driven are obtained; the compensation module determines the magnitude of the current to be compensated according to the difference between the load driving parameters and the target driving parameters, and generates a relevant initial compensation current; the initial compensation current is subjected to multiple mirror processing by the compensation module, and the magnitude of the initial compensation current is adjusted to obtain a target compensation current, and the bias voltage is stabilized through the target compensation current.

[0049] In detail, generating an initial compensation current according to the load driving parameters and the target driving parameters includes: determining the load change difference according to the target driving parameters and the load driving parameters; generating an initial compensation current according to the load change difference. Specifically, the load change difference after the load change is calculated according to the target driving parameters and the load driving parameters, and the corresponding initial compensation current i is determined according to the load change difference.

[0050] Specifically, the initial compensation current is mirrored and sized to obtain a target compensation current, including: mirroring the initial compensation current twice to obtain a mirrored compensation current; first multiplying and then mirroring the mirrored compensation current to obtain the target compensation current. Specifically, the initial compensation current is mirrored by a mirror structure composed of a sixth PMOS transistor M6 and a seventh PMOS transistor M7, and a mirror structure composed of a first NMOS transistor N1 and a second NMOS transistor N2, and then the size of the initial compensation current is adjusted by a fourth NPN transistor Q4 to obtain the target compensation current, and then the target compensation current is mirrored by a mirror structure composed of a fourth PMOS transistor M4 and a fifth PMOS transistor M5 and applied to the base of a fifth NPN transistor Q5 to achieve compensation for the bias voltage VB1.

[0051] Specifically, a bias voltage VB1 is provided, including: generating a branch current, mirroring and amplifying the branch current to obtain a mirrored branch current; generating the bias voltage VB1 based on the mirrored branch current and the branch current. Specifically, a bias generation module generates a branch current I in a branch including a first PMOS transistor M1 based on a power supply voltage VCC, and performs an n-fold amplification process on the branch current I according to the size relationship between the first PMOS transistor M1 and the second PMOS transistor M2. The amplified mirrored branch current is nI, and then the amplified current is mirrored and copied by a mirror structure composed of a second NPN transistor Q2 and a third NPN transistor Q3 to form a mirrored branch current nI in a branch including a second resistor R2. The bias generation module outputs the bias voltage VB1 at the base of a first NPN transistor Q1 based on the mirrored branch current nI and the branch current I.

[0052] In a third aspect of the present application, the present application further provides a digital-to-analog converter, which includes the bias driving circuit applicable to the bipolar process described above to improve the stability of the digital-to-analog converter.

[0053] The present application provides a bias driving circuit, a control method, and a digital-to-analog converter applicable to the bipolar process. The bias driving circuit includes a bias generation module and a compensation module. The bias generation module generates a bias voltage and generates a corresponding initial compensation current when the load to be driven changes. The initial compensation current is mirrored and the current size is adjusted to obtain a target compensation current, so that the bias voltage is stabilized by the target compensation current. When the driving load increases, the bias driving circuit provided in the present application generates the target compensation current required for the increased load through the compensation module, reduces the influence on the bias voltage, improves the driving ability of the bias driving circuit, and can be applied to a high-resolution current-steering DAC to provide a stable bias for the DAC and improve the stability of the DAC.

[0054] The above embodiments are only used to exemplarily illustrate the principles and effects of the present invention, rather than to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A bias drive circuit suitable for bipolar process, characterized in that: include: A bias generating module, used for generating a bias voltage; The compensation module is connected to the bias generating module, generates an initial compensation current according to the change of the load to be driven, performs mirror processing on the initial compensation current and adjusts the size to obtain a target compensation current, so as to keep the bias voltage stable through the target compensation current.

2. The bias driving circuit suitable for bipolar process according to claim 1, characterized in that: The bias generating module comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NPN transistor, a second NPN transistor, a third NPN transistor, a first resistor and a second resistor, wherein the source of the first PMOS tube is connected to a power supply voltage, the drain of the first PMOS tube is connected to the collector of the first NPN transistor, the emitter of the first NPN transistor is grounded after passing through the first resistor, the first end of the second resistor is connected to the power supply voltage, the second end of the second resistor is connected to the gate of the second PMOS tube, the gate of the second PMOS tube is connected to the gate of the first PMOS tube, the second end of the second resistor is also connected to the source of the third PMOS tube, and the second PMOS tube The source of the second PMOS tube is connected to the power supply voltage, the drain of the second PMOS tube is connected to the gate of the third PMOS tube, the drain of the second PMOS tube is also connected to the collector of the third NPN transistor, the base of the third NPN transistor is connected to the base of the second NPN transistor, the drain of the third PMOS tube is connected to the collector of the second NPN transistor, the collector of the second NPN transistor is connected to the base of the second NPN transistor, the emitter of the second NPN transistor is connected to the emitter of the third NPN transistor, and the emitter of the second NPN transistor is also grounded, wherein the collector of the first NPN transistor and the base of the first NPN transistor cooperate to output the bias voltage to the outside.

3. The bias driving circuit suitable for bipolar process according to claim 2, characterized in that: The ratio of the size of the second PMOS tube to the size of the first PMOS tube is n, and the size of the second NPN transistor is equal to the size of the third NPN transistor.

4. The bias driving circuit suitable for bipolar process according to claim 2, characterized in that: The compensation module includes a first NMOS tube, a second NMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a fourth NPN transistor and a fifth NPN transistor, the collector of the fourth NPN transistor is connected to the power supply voltage, the emitter of the fourth NPN transistor is connected to the drain of the first NMOS tube, the gate of the first NMOS tube is connected to the gate of the second NMOS tube, the source of the first NMOS tube is connected to the source of the second NMOS tube, the source of the second NMOS tube is grounded, the source of the fourth PMOS tube is connected to the collector of the fourth NPN transistor, the gate of the fourth PMOS tube is connected to the gate of the fifth PMOS tube, and the gate of the fourth PMOS tube is also connected to the base of the fourth NPN transistor. The drain of the fourth PMOS tube is connected to the base of the fourth NPN transistor, the source of the fifth PMOS tube is connected to the source of the fourth PMOS tube, the drain of the fifth PMOS tube is connected to the base of the fifth NPN transistor, the source of the sixth PMOS tube is connected to the source of the fifth PMOS tube, the source of the sixth PMOS tube is also connected to the source of the seventh PMOS tube, the gate of the sixth PMOS tube is connected to the gate of the seventh PMOS tube, the drain of the sixth PMOS tube is connected to the drain of the second NMOS tube, the gate of the seventh PMOS tube is connected to the drain of the seventh PMOS tube, and the drain of the seventh PMOS tube is connected to the collector of the fifth NPN transistor, wherein the base and emitter of the fifth NPN transistor are connected to the bias generating module.

5. The bias driving circuit suitable for bipolar process according to claim 4, characterized in that: The size of the first NMOS tube is equal to that of the second NMOS tube, the size of the fourth PMOS tube is equal to that of the fifth PMOS tube, and the size of the sixth PMOS tube is equal to that of the seventh PMOS tube.

6. A control method for a bias drive circuit suitable for bipolar technology, characterized in that: include: Providing a bias voltage and acquiring a load driving parameter corresponding to the bias voltage and a target driving parameter of a load to be driven; generating an initial compensation current according to the load driving parameter and the target driving parameter; The initial compensation current is mirrored and the magnitude is adjusted to obtain a target compensation current, so as to stabilize the bias voltage through the target compensation current.

7. The control method of the bias driving circuit suitable for bipolar process according to claim 6, characterized in that: Generating an initial compensation current according to the load driving parameter and the target driving parameter includes: Determining a load change difference according to the target drive parameter and the load drive parameter; An initial compensation current is generated according to the load change difference.

8. The control method of the bias driving circuit suitable for bipolar process according to claim 6, characterized in that: The initial compensation current is mirrored and adjusted to obtain a target compensation current, including: Performing mirror processing twice on the initial compensation current to obtain a mirror compensation current; The mirror compensation current is first adjusted in multiples and mirrored to obtain a target compensation current.

9. The control method of the bias driving circuit suitable for bipolar process according to claim 6, characterized in that: Provides bias voltages including: Generate a branch current, and perform mirror amplification on the branch current to obtain a mirror branch current; The bias voltage is generated according to the mirror branch current and the branch current.

10. A digital-to-analog converter, characterized in that: The digital-to-analog converter includes a bias driving circuit suitable for bipolar process as described in any one of claims 1-5.

Images