Circuit for level shifting

Abstract

This application discloses a circuit for level conversion. The circuit includes: a bootstrap circuit for converting an input voltage into a control voltage; and a level conversion circuit for providing an output voltage based on the control voltage, wherein the output voltage is higher than the input voltage. The control voltage has a voltage amplitude greater than the threshold voltage of a switch in the level conversion circuit. This circuit utilizes a control voltage with a higher voltage amplitude to control the level conversion circuit for level conversion, generating a larger current and significantly improving the level conversion speed.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and more particularly to a circuit for level conversion. Background Art

[0002] As integrated circuit design becomes increasingly complex, higher requirements are placed on integration, stability, compatibility, and other features. Hybrid digital-analog chips, with their advantages of high integration, intelligence and automation, high reliability and stability, multi-core and parallel processing, and customization and personalization, are widely used in various fields such as communications, medical care, and industrial control.

[0003] However, with the advancement of integrated circuit (IC) technology, the voltages in the digital voltage domain have become increasingly lower, while the voltages in the analog voltage domain remain relatively constant or even increase in specialized processes. When low-voltage digital circuit signals are output to high-voltage analog circuits, level shifters are required to perform the level conversion. As digital frequencies increase, the speed requirements for level shifters are also increasing. The larger the voltage amplitude when converting from a digital low level to an analog high level, the slower the conversion speed of the level shifter. Therefore, traditional level shifters cannot meet the level conversion speed requirements of integrated circuits.

[0004] Therefore, it is desired to provide an improved level conversion circuit to solve the above problems. Summary of the Invention

[0005] In view of the above problems, an object of the present invention is to provide a circuit for level conversion to improve the level conversion speed.

[0006] According to one aspect of the present invention, there is provided a circuit for level conversion, comprising:

[0007] A bootstrap circuit for converting the input voltage into a control voltage; and

[0008] The level conversion circuit includes a plurality of switch tubes, which are used to provide an output voltage according to the control voltage, wherein the level of the output voltage is higher than the level of the input voltage.

[0009] Wherein, the voltage amplitude of the control voltage is greater than the threshold voltage of the switch tube of the level conversion circuit.

[0010] Optionally, the voltage amplitude of the control voltage is greater than or equal to twice the voltage amplitude of the input voltage.

[0011] Optionally, the control voltage includes a first voltage and a second voltage that are complementary, and the bootstrap circuit includes a first branch and a second branch having the same circuit structure.

[0012] The first branch uses a first capacitor to charge and discharge to obtain the first voltage;

[0013] The second branch uses the second capacitor to charge and discharge to obtain the second voltage,

[0014] The charging and discharging paths of the first branch and the second branch are controlled by the input voltage.

[0015] Optionally, when the input voltage is at a high level, the first power supply charges the first capacitor, the first voltage is pulled down to a reference ground, the second capacitor starts to discharge to provide the second voltage, and a path from the second voltage to the reference ground is cut off;

[0016] When the input voltage is at a low level, the first capacitor starts to discharge to provide the first voltage, the path from the first voltage to the reference ground is cut off, the first power supply charges the second capacitor, and the second voltage is pulled down to the reference ground.

[0017] Optionally, the first branch includes:

[0018] a first inverter, configured to convert the input voltage into a first intermediate voltage;

[0019] The first capacitor has a second end connected to the output end of the first inverter;

[0020] A first switch tube is connected between the first power supply and the first end of the first capacitor, and a control end of the first switch tube is connected to the first end of the second capacitor;

[0021] a second switch tube, connected between the first end of the first capacitor and the first output end;

[0022] a third switch tube, connected between the first output terminal and the reference ground;

[0023] The second branch includes:

[0024] a second inverter connected to an output terminal of the first inverter, configured to convert the first intermediate voltage into a second intermediate voltage;

[0025] The second capacitor has a second end connected to the output end of the second inverter;

[0026] a fourth switch tube, connected between the first power supply and the first end of the second capacitor, wherein the control end of the fourth switch tube is connected to the second end of the first capacitor;

[0027] a fifth switching tube, connected between the first terminal and the second output terminal of the second capacitor;

[0028] A sixth switch tube is connected between the second output terminal and the reference ground.

[0029] Optionally, the second switch tube and the third switch tube are controlled by the second intermediate voltage, and the fifth switch tube and the sixth switch tube are controlled by the first intermediate voltage; the conduction type of the first switch tube, the third switch tube, the fourth switch tube and the sixth switch tube is the same, and opposite to the conduction type of the second switch tube and the fifth switch tube.

[0030] Optionally, the control voltage includes a first voltage and a second voltage that are complementary, and the level conversion circuit includes:

[0031] a seventh switch tube, an eighth switch tube, and a ninth switch tube connected in sequence between the second power supply and the reference ground,

[0032] a tenth switching tube, an eleventh switching tube, and a twelfth switching tube connected in sequence between the second power supply and the reference ground;

[0033] The control terminal of the eighth switch tube is connected to the control terminal of the ninth switch tube and receives the second voltage. The control terminal of the eleventh switch tube is connected to the control terminal of the twelfth switch tube and receives the first voltage. The control terminal of the seventh switch tube is connected to a second node between the eleventh switch tube and the twelfth switch tube. The control terminal of the tenth switch tube is connected to a first node between the eighth switch tube and the ninth switch tube. The second node provides the output voltage.

[0034] The voltage amplitude of the control voltage is greater than the threshold voltages of the eighth switching tube, the ninth switching tube, the eleventh switching tube, and the twelfth switching tube.

[0035] Optionally, the control voltage includes a first voltage and a second voltage that are complementary, and the level conversion circuit includes:

[0036] a seventh switch tube, an eighth switch tube, and a ninth switch tube connected in sequence between the second power supply and the reference ground,

[0037] a tenth switching tube, an eleventh switching tube, and a twelfth switching tube connected in sequence between the second power supply and the reference ground;

[0038] The control terminal of the ninth switch tube receives the second voltage, the control terminal of the twelfth switch tube receives the first voltage, the control terminal of the seventh switch tube and the control terminal of the eleventh switch tube are respectively connected to a first node between the eighth switch tube and the ninth switch tube, the control terminal of the eighth switch tube and the control terminal of the tenth switch tube are respectively connected to a second node between the eleventh switch tube and the twelfth switch tube, and the second node provides the output voltage.

[0039] The voltage amplitude of the control voltage is greater than the threshold voltages of the ninth switching tube and the twelfth switching tube.

[0040] Optionally, the control voltage includes a first voltage and a second voltage that are complementary, and the level conversion circuit includes:

[0041] A current mirror circuit includes a third branch and a fourth branch;

[0042] a seventh switch tube, connected to the third branch, the seventh switch tube being controlled by the second voltage; and

[0043] an eighth switch tube, connected to the fourth branch, the eighth switch tube being controlled by the first voltage,

[0044] The voltage amplitude of the control voltage is greater than the threshold voltages of the seventh switching tube and the eighth switching tube.

[0045] Optionally, the control voltage includes a first voltage and a second voltage that are complementary, and the level conversion circuit includes:

[0046] A current mirror circuit includes a third branch and a fourth branch;

[0047] a seventh switch tube, connected to the third branch, the seventh switch tube being controlled by the second voltage;

[0048] an eighth switch tube, connected to the fourth branch, the eighth switch tube being controlled by the first voltage; and

[0049] a ninth switch tube, connected between the second power supply and the third branch, or connected between the third branch and the seventh switch tube, and controlled by the output voltage;

[0050] When the output voltage is at a high level, the ninth switch is turned off.

[0051] The voltage amplitude of the control voltage is greater than the threshold voltages of the seventh switching tube and the eighth switching tube.

[0052] The circuit for level conversion provided by the present invention utilizes a control voltage with a relatively high voltage amplitude to control the level conversion circuit to perform level conversion, thereby generating a relatively large current and significantly improving the level conversion speed.

[0053] In some optional embodiments, the circuit improves the level conversion circuit and forms an inverter structure in the level conversion circuit, which can pull down the voltage of the first node / the second node more quickly, further improving the level conversion speed.

[0054] In some optional embodiments, the circuit improves the level conversion circuit, eliminates static current, and has the advantages of low power consumption and leakage prevention. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0056] Figure 1 FIG2 shows a schematic diagram of a circuit for level conversion according to a first embodiment of the present invention;

[0057] Figure 2 shows a schematic diagram of a bootstrap circuit according to an embodiment of the present invention;

[0058] Figure 3 shows a signal waveform diagram of voltages at various locations of a circuit for level conversion according to an embodiment of the present invention;

[0059] Figure 4 FIG2 shows a schematic diagram of a circuit for level conversion according to a second embodiment of the present invention;

[0060] Figure 5 FIG. 1 is a schematic diagram showing a circuit for level conversion according to a third embodiment of the present invention;

[0061] Figure 6 FIG. 1 is a schematic diagram showing a circuit for level conversion according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0062] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0063] Many specific details of the present invention are described below, such as device structures, materials, dimensions, processing techniques, and technologies, to provide a clearer understanding of the present invention. However, as will be appreciated by those skilled in the art, the present invention may be practiced without these specific details.

[0064] It should be understood that the connection / coupling of A and B in the embodiment of the present application means that A and B can be connected in series or in parallel, or A and B can be connected through other devices, and the embodiment of the present application is not limited to this.

[0065] The following describes an embodiment of a circuit for level conversion provided by the present application in conjunction with the accompanying drawings.

[0066] Figure 1 FIG2 shows a schematic diagram of a circuit for level conversion according to a first embodiment of the present invention; Figure 2 shows a schematic diagram of a bootstrap circuit according to an embodiment of the present invention; Figure 3 FIG. 4 shows a signal waveform diagram of voltages at various locations in a circuit for level conversion according to an embodiment of the present invention.

[0067] like Figure 1 As shown, a circuit 100 for level conversion provided by an embodiment of the present invention includes a bootstrap circuit 110 and a level conversion circuit 120 . The circuit 100 can convert an input voltage VIN into an output voltage VOUT.

[0068] In some embodiments, the circuit 100 is applied to a display driver chip, a power supply chip, etc., or to a system on chip (SoC) or a mixed analog-digital circuit. The input voltage VIN is applied to the digital circuit part of these chips or circuits, and its voltage amplitude is relatively low. The output voltage VOUT is applied to the analog circuit part of these chips or circuits, and its voltage amplitude is relatively high.

[0069] The bootstrap circuit 110 is used to convert the input voltage VIN into a control voltage. Specifically, the control voltage includes at least a first voltage VN and a second voltage VP, and the first voltage VN and the second voltage VP are complementary. For example, when the first voltage VN is at a high level, the second voltage VP is at a low level; when the first voltage VN is at a low level, the second voltage VP is at a high level. In an embodiment of the present invention, the voltage amplitude of the control voltage is configured to be greater than the threshold voltage of the switch tube in the level conversion circuit 120, and the voltage amplitude of the control voltage is greater than or equal to twice the voltage amplitude of the input voltage VIN. For example, if the high level of the input voltage VIN is VDDL, then the high levels of the first voltage VN and the second voltage VP are both 2*VDDL, and if the low level of the input voltage VIN is 0, then the low levels of the first voltage VN and the second voltage VP are also 0.

[0070] The level conversion circuit 120 is configured to provide an output voltage VOUT according to a control voltage, wherein the level of the output voltage VOUT is higher than the level of the input voltage VIN. In some embodiments, the level conversion circuit 120 implements level conversion based on a current mirror.

[0071] In the embodiment of the present invention, the bootstrap circuit 110 is used to convert the input voltage VIN into a control voltage with a higher voltage amplitude, which can generate a larger current in the level conversion circuit 120, thereby increasing the speed of level conversion.

[0072] See Figure 2Bootstrap circuit 110 includes a first branch 111 and a second branch 112 with identical circuit structures. First branch 111 utilizes a first capacitor C1 for charging and discharging to obtain a first voltage VN, with the charging and discharging path of first branch 111 controlled by input voltage VIN. Second branch 112 utilizes a second capacitor C2 for charging and discharging to obtain a second voltage VP, with the charging and discharging path of second branch 112 controlled by the inverse voltage of input voltage VIN. Because first branch 111 and second branch 112 are controlled by opposite voltages, bootstrap circuit 110 can generate complementary first voltage VN and second voltage VP based on input voltage VIN.

[0073] In this embodiment, when the input voltage VIN is at a high level, the first power supply VDDL charges the first capacitor C1, the first voltage VN is pulled down to the reference ground GND (usually 0), the second capacitor C2 starts to discharge to provide the second voltage VP, and the path from the second voltage VP to the reference ground GND is cut off; when the input voltage VIN is at a low level, the first capacitor C1 starts to discharge to provide the first voltage VN, the path from the first voltage VN to the reference ground GND is cut off, the first power supply VDDL charges the second capacitor C2, and the second voltage VP is pulled down to the reference ground GND.

[0074] Specifically, the first branch 111 includes a first inverter INV1, a first switch M1, a second switch M2, a third switch M3, and a first capacitor C1. The input terminal of the first inverter INV1 receives an input voltage VIN and converts the input voltage VIN into a first intermediate voltage VG1. The second terminal of the first capacitor C1 is connected to the output terminal of the first inverter INV1. The first switch M1 is connected between a first power supply VDDL and the first terminal of the first capacitor C1. The second switch M2 is connected between the first terminal of the first capacitor C1 and the first output terminal. The third switch M3 is connected between the first output terminal and the reference ground GND. The control terminal of the first switch M1 is connected to the first terminal of the second capacitor C2 and is controlled by a fourth intermediate voltage VG4. The second and third switches M2 and M3 are controlled by a second intermediate voltage VG2. The second intermediate voltage VG2 is also equivalent to a voltage obtained by delaying the input voltage VIN. The fourth intermediate voltage VG4 is the voltage at the first terminal of the second capacitor C2.

[0075] The second branch 112 includes a second inverter INV2, a fourth switch M4, a fifth switch M5, a sixth switch M6, and a second capacitor C2. The input of the second inverter INV2 is connected to the output of the first inverter INV1, converting the first intermediate voltage VG1 into a second intermediate voltage VG2. The second end of the second capacitor C2 is connected to the output of the second inverter INV2. The fourth switch M4 is connected between the first power supply VDDL and the first end of the second capacitor C2. The fifth switch M5 is connected between the first end and the second output end of the second capacitor C2. The sixth switch M6 is connected between the second output end and the reference ground GND. The control end of the fourth switch M4 is connected to the first end of the first capacitor C1 and is controlled by the third intermediate voltage VG3. The fifth and sixth switches M5 and M6 are controlled by the first intermediate voltage VG1. The first intermediate voltage VG1 is also equivalent to the inverse voltage of the input voltage VIN. The third intermediate voltage VG3 is the voltage at the first end of the first capacitor C1.

[0076] In this embodiment, the first switch M1, the third switch M3, the fourth switch M4, and the sixth switch M6 have the same conduction type, which is opposite to the conduction type of the second switch M2 and the fifth switch M5. For example, the first switch M1, the third switch M3, the fourth switch M4, and the sixth switch M6 are all N-type metal oxide semiconductor field effect transistors (NMOS), and the second switch M2 and the fifth switch M5 are both P-type metal oxide semiconductor field effect transistors (PMOS).

[0077] After the circuit enters a stable state, the first power supply VDDL charges the upper plates (first ends) of the first capacitor C1 and the second capacitor C2 to VDDL. The low level of the input voltage VIN is, for example, 0, and the high level is, for example, VDDL.

[0078] When the input voltage VIN switches from a high level to a low level, the first intermediate voltage VG1 provided by the first inverter INV1 is a high level, and the second intermediate voltage VG2 provided by the second inverter INV2 is a low level. At this time, the second end of the first capacitor C1 is charged to VDDL. Based on the principle that the capacitor voltage cannot change suddenly, the voltage at the first end of the first capacitor C1 becomes VDDL+VDDL=2*VDDL, and the fourth switch tube M4 is turned on. The charging path from the first power supply VDDL to the second capacitor C2 is turned on, charging the first end of the second capacitor C2 to VDDL. At this time, the second switch tube M2 is turned on, the third switch tube M3 is turned off, the fifth switch tube M5 is turned off, and the sixth switch tube M6 is turned on. Therefore, the discharge path from the first capacitor C1 to the first output terminal is conductive, and the current path between the first output terminal and the reference ground GND is blocked, resulting in a high voltage VN provided by the first output terminal. The discharge path from the second capacitor C2 to the second output terminal is blocked, and the current path between the second output terminal and the reference ground GND is conductive, resulting in a low voltage VP provided by the second output terminal. Therefore, when the input voltage VIN changes from a high level to a low level, the first voltage VN changes from a low level to a high level, and the second voltage VP changes from a high level to a low level. The high level of the first voltage VN is twice the high level of the input voltage VIN.

[0079] When the input voltage VIN switches from a low level to a high level, the first intermediate voltage VG1 provided by the first inverter INV1 is a low level, and the second intermediate voltage VG2 provided by the second inverter INV2 is a high level. At this time, the second end of the second capacitor C2 is charged to VDDL. Based on the principle that the capacitor voltage cannot change suddenly, the voltage at the first end of the second capacitor C2 becomes VDDL+VDDL=2*VDDL, and the first switch tube M1 is turned on. The charging path from the first power supply VDDL to the first capacitor C1 is turned on, charging the first end of the first capacitor C1 to VDDL. At this time, the second switch tube M2 is turned off, the third switch tube M3 is turned on, the fifth switch tube M5 is turned on, and the sixth switch tube M6 is turned off. Therefore, the discharge path from the first capacitor C1 to the first output terminal is disconnected, and the current path from the first output terminal to the reference ground GND is conductive, resulting in a low-level first voltage VN provided by the first output terminal. The discharge path from the second capacitor C2 to the second output terminal is conductive, and the current path from the second output terminal to the reference ground GND is disconnected, resulting in a high-level second voltage VP provided by the second output terminal. Therefore, when the input voltage VIN changes from a low level to a high level, the first voltage VN changes from a high level to a low level, and the second voltage VP changes from a low level to a high level, with the high level of the second voltage VP being twice the high level of the input voltage VIN.

[0080] It should be understood that the circuit structures of the first branch 111 and the second branch 112 described above are merely illustrative examples, and those skilled in the art can achieve the same or similar technical effects by changing parameters such as the type of the switch tube and the corresponding circuit connection relationship. In addition, the voltage value of the first power supply VDDL can be the same as the input voltage VIN, so that the voltage amplitude of the first voltage VN and the second voltage VP is approximately twice the voltage amplitude of the input voltage VIN; the voltage value of the first power supply VDDL can be greater than the input voltage VIN, so that the voltage amplitude of the first voltage VN and the second voltage VP is greater than twice the voltage amplitude of the input voltage VIN. By adjusting the voltage value of the first power supply VDDL, the voltage amplitude of the first voltage VN and the second voltage VP can be controlled so that the voltage amplitude of the first voltage VN and the second voltage VP is greater than the threshold voltage of the switch tube in the level conversion circuit 120.

[0081] In this embodiment, the level conversion circuit 120 includes a seventh switch transistor M7 , an eighth switch transistor M8 , a ninth switch transistor M9 , a tenth switch transistor M10 , an eleventh switch transistor M11 , and a twelfth switch transistor M12 .

[0082] The seventh, eighth, and ninth switching transistors M7, M8, and M9 are sequentially connected between the second power supply VDDH and the reference ground GND. The tenth, eleventh, and twelfth switching transistors M10, M11, and M12 are also sequentially connected between the second power supply VDDH and the reference ground GND. The control terminal of the eighth switching transistor M8 is connected to the control terminal of the ninth switching transistor M9 and receives the second voltage VP. The control terminal of the eleventh switching transistor M11 is connected to the control terminal of the twelfth switching transistor M12 and receives the first voltage VN. The control terminal of the seventh switching transistor M7 is connected to the second node Q2 between the eleventh switching transistor M11 and the twelfth switching transistor M12. The control terminal of the tenth switching transistor M10 is connected to the first node Q1 between the eighth switching transistor M8 and the ninth switching transistor M9. The second node Q2 provides the output voltage VOUT. Therefore, the eighth switching transistor M8 and the ninth switching transistor M9 form an inverter structure, and the eleventh switching transistor M11 and the twelfth switching transistor M12 form an inverter structure. In this embodiment, the voltage amplitude of the control voltage (including the first voltage VN and the second voltage VP) is greater than the threshold voltages of the eighth switch M8 , the ninth switch M9 , the eleventh switch M11 , and the twelfth switch M12 .

[0083] In this embodiment, the seventh switch transistor M7 , the eighth switch transistor M8 , the tenth switch transistor M10 , and the eleventh switch transistor M11 are all PMOS transistors, and the ninth switch transistor M9 and the twelfth switch transistor M12 are all NMOS transistors.

[0084] In this embodiment, for example, the high level of the input voltage VIN is set to VDDL, the high levels of the first voltage VN and the second voltage VP are both 2*VDDL, and the low levels of the input voltage VIN, the first voltage VN and the second voltage VP are all 0.

[0085] When the input voltage VIN is high, the first voltage VN provided by the bootstrap circuit 110 is low, and the second voltage VP is high. The eighth switch M8 is turned off, and the ninth switch M9 is turned on. Therefore, the first node Q1 is quickly pulled down to a low level. The eleventh switch M11 is turned on, and the twelfth switch M12 is turned off, allowing the second node Q2 to be charged to a high level more quickly.

[0086] When the input voltage VIN is low, the first voltage VN provided by the bootstrap circuit 110 is high, and the second voltage VP is low. The eighth switch M8 is turned on, and the ninth switch M9 is turned off. Therefore, the first node Q1 can be quickly charged to a high level. The eleventh switch M11 is turned off, and the twelfth switch M12 is turned on, allowing the second node Q2 to be discharged to a low level more quickly.

[0087] In this embodiment, the eighth switch tube M8 and the ninth switch tube M9 form an inverter structure, and the eleventh switch tube M11 and the twelfth switch tube M12 form an inverter structure, thereby further accelerating the level conversion.

[0088] It should be understood that the circuit structure of the level shifter circuit 120 is merely an illustrative example. Those skilled in the art can achieve the same or similar technical effects by changing parameters such as the type of the switch tube and the corresponding circuit connections. Furthermore, the output voltage VOUT can be adjusted by adjusting the voltage of the second power supply VDDH.

[0089] After the above signal processing, the circuit 100 for level conversion according to the embodiment of the present invention converts the input voltage VIN with a lower level into the output voltage VOUT with a higher level. Figure 3 The first power supply VDDL charges the third intermediate voltage VG3 on the first capacitor C1 and the fourth intermediate voltage VG4 on the second capacitor C2 to VDDL, and the third intermediate voltage VG3 on the first capacitor C1 and the fourth intermediate voltage VG4 on the second capacitor C2 are alternately pulled up to 2*VDD under the action of the input voltage VIN. Therefore, the bootstrap circuit 110 converts the input voltage VIN with a voltage amplitude of VDDL into a first voltage VN and a second voltage VP with a voltage amplitude of 2*VDDL. The level conversion circuit 120 generates an output voltage VOUT with a voltage amplitude of VDDH based on the first voltage VN and the second voltage VP. The phases of the input voltage VIN and the output voltage VOUT are basically synchronized.

[0090] Some examples of circuits for level conversion according to embodiments of the present invention are described above. However, embodiments of the present invention are not limited thereto and may be expanded and modified in other ways.

[0091] For example, it should be understood that the reference ground potential in the aforementioned embodiments may be replaced by other non-zero reference potentials (having positive or negative voltage amplitudes) or controlled varying reference signals in alternative embodiments.

[0092] For another example, the capacitor provided in the embodiment of the present application can be a lumped parameter capacitor element, or it can be other equivalent elements with similar functions to capacitors. The equivalent structures described here include, but are not limited to, structures that can provide capacitive impedance, such as microstrip lines, varactors, and conductor structures with certain patterns.

[0093] At the same time, those skilled in the art will appreciate that, in conjunction with the various exemplary structures and methods described in the embodiments disclosed herein, different configuration methods or adjustment methods can be used for each structure or reasonable variations of the structure to achieve the described functions, but such implementations should not be considered beyond the scope of this application. Furthermore, it should be understood that the connection relationships between the various components of the amplifier in the aforementioned figures in the embodiments of this application are for illustrative purposes only and do not impose any limitations on the embodiments of this application.

[0094] Figure 4 The circuit structure of the bootstrap circuit 110 of the second embodiment of the present invention is identical to that of the bootstrap circuit 110 of the first embodiment, and will not be described in detail here.

[0095] In this embodiment, the level conversion circuit 120 includes a seventh switch transistor M7 , an eighth switch transistor M8 , a ninth switch transistor M9 , a tenth switch transistor M10 , an eleventh switch transistor M11 , a twelfth switch transistor M12 and a third inverter INV3 .

[0096] The seventh switch tube M7, the eighth switch tube M8 and the ninth switch tube M9 are sequentially connected between the second power supply VDDH and the reference ground GND. The tenth switch tube M10, the eleventh switch tube M11 and the twelfth switch tube M12 are also sequentially connected between the second power supply VDDH and the reference ground GND.

[0097] The control terminal of the ninth switch M9 receives the second voltage VP, the control terminal of the twelfth switch M12 receives the first voltage VN, the control terminals of the seventh switch M7 and the eleventh switch M11 are respectively connected to a first node Q1, which is the connection node between the eighth switch M8 and the ninth switch M9. The control terminals of the eighth switch M8 and the tenth switch M10 are respectively connected to a second node Q2, which is the connection node between the eleventh switch M11 and the twelfth switch M12. The second node Q2 is connected to the input terminal of the third inverter INV3, and the output terminal of the third inverter INV3 provides the output voltage VOUT. In this embodiment, the voltage amplitude of the control voltage (including the first voltage VN and the second voltage VP) is greater than the threshold voltages of the ninth switch M9 and the twelfth switch M12.

[0098] In this embodiment, the seventh switch transistor M7 , the eighth switch transistor M8 , the tenth switch transistor M10 , and the eleventh switch transistor M11 are all PMOS transistors, and the ninth switch transistor M9 and the twelfth switch transistor M12 are all NMOS transistors.

[0099] In this embodiment, for example, the high level of the input voltage VIN is set to VDDL, the high levels of the first voltage VN and the second voltage VP are both 2*VDDL, and the low levels of the input voltage VIN, the first voltage VN and the second voltage VP are all 0.

[0100] When the input voltage VIN is high, the first voltage VN provided by the bootstrap circuit 110 is low, and the second voltage VP is high. The eighth, ninth, and tenth switches M9, M10 are turned on, quickly pulling the first node Q1 down to a low level. The seventh, eleventh, and twelfth switches M7, M11, and M12 are turned off, allowing the second node Q2 to charge to a high level more quickly.

[0101] When the input voltage VIN is low, the first voltage VN provided by the bootstrap circuit 110 is high, and the second voltage VP is low. The eighth, ninth, and tenth switches M9, M10 are turned off, allowing the first node Q1 to quickly charge to a high level. The seventh, eleventh, and twelfth switches M7, M11, and M12 are turned on, allowing the second node Q2 to discharge to a low level even more quickly.

[0102] It should be understood that the circuit structure of the level shifter circuit 120 is merely an illustrative example. Those skilled in the art can achieve the same or similar technical effects by changing parameters such as the type of the switch tube and the corresponding circuit connections. Furthermore, the output voltage VOUT can be adjusted by adjusting the voltage of the second power supply VDDH.

[0103] Figure 5FIG. 1 is a schematic diagram showing a circuit for level conversion according to a third embodiment of the present invention.

[0104] In this embodiment, the level shifter circuit 120 includes a current mirror circuit, a seventh switch M7, and an eighth switch M8. The current mirror circuit includes a third branch 121 and a fourth branch 122. The third branch 121 is a current input branch, and the fourth branch 122 is a current output branch. The seventh switch M7 is connected to the third branch 121 and is controlled by a second voltage VP. The eighth switch M8 is connected to the fourth branch 122 and is controlled by a first voltage VN. The connection node between the fourth branch 122 and the eighth switch M8 serves as the output terminal of the level shifter circuit 120 and provides the output voltage VOUT.

[0105] As an example, the third branch 121 includes an eleventh switch transistor M11, and the fourth branch 122 includes a twelfth switch transistor M12. The first current terminal of the eleventh switch transistor M11 is directly connected to the second power supply VDDH, and the second current terminal of the eleventh switch transistor M11 is connected to the reference ground GND through the seventh switch transistor M7. The control terminal of the eleventh switch transistor M11 is connected to the control terminal of the twelfth switch transistor M12 and is also connected to the second current terminal of the eleventh switch transistor M11. The first current terminal of the twelfth switch transistor M12 is directly connected to the second power supply VDDH, and the second current terminal of the twelfth switch transistor M12 is connected to the reference ground GND through the eighth switch transistor M8.

[0106] In this example, the seventh switch transistor M7 and the eighth switch transistor M8 are NMOS transistors, and the eleventh switch transistor M11 and the twelfth switch transistor M12 are PMOS transistors.

[0107] In this example, for example, the high level of the input voltage VIN is set to VDDL, the high levels of the first voltage VN and the second voltage VP are both 2*VDDL, and the low levels of the input voltage VIN, the first voltage VN and the second voltage VP are all 0.

[0108] When the input voltage VIN is high, the first voltage VN provided by the bootstrap circuit 110 is low, and the second voltage VP is high. The seventh switch M7 is turned on, and the eighth switch M8 is turned off. The gate voltage of the eleventh switch M11 is pulled down to the reference ground GND (typically 0). As a result, the eleventh and twelfth switches M11 and M12 are turned on, and the output voltage VOUT provided by the output terminal of the level shifter circuit 120 is pulled up to VDDH.

[0109] When the input voltage VIN is low, the first voltage VN provided by the bootstrap circuit 110 is high and the second voltage VP is low. The seventh switch M7 is turned off and the eighth switch M8 is turned on. The output voltage VOUT provided by the output terminal of the level shifter circuit 120 is pulled down to the reference ground GND voltage.

[0110] It should be understood that the circuit structure of the level shifter circuit 120 is merely an illustrative example. Those skilled in the art can achieve the same or similar technical effects by changing parameters such as the type of the switch tube and the corresponding circuit connections. Furthermore, the output voltage VOUT can be adjusted by adjusting the voltage of the second power supply VDDH.

[0111] Figure 6 FIG. 1 is a schematic diagram showing a circuit for level conversion according to a fourth embodiment of the present invention.

[0112] In this embodiment, the level shifter circuit 120 includes a current mirror circuit, a seventh switch M7, an eighth switch M8, and a ninth switch M9. The current mirror circuit includes a third branch 121 and a fourth branch 122. The third branch 121 is a current input branch, and the fourth branch 122 is a current output branch. The seventh switch M7 is connected to the third branch 121 and is controlled by a second voltage VP. The eighth switch M8 is connected to the fourth branch 122 and is controlled by a first voltage VN. The ninth switch M9 is connected between the third branch 121 and the seventh switch M7 and is controlled by an output voltage VOUT. The connection node between the fourth branch 122 and the eighth switch M8 serves as the output terminal of the level shifter circuit 120 and provides the output voltage VOUT. In other embodiments, the ninth switch M9 is connected between the third branch 121 and the second power supply VDDH.

[0113] As an example, the third branch 121 includes an eleventh switch transistor M11, and the fourth branch 122 includes a twelfth switch transistor M12. The first current terminal of the eleventh switch transistor M11 is directly connected to the second power supply VDDH, and the second current terminal of the eleventh switch transistor M11 is connected to the reference ground GND via the ninth switch transistor M9 and the seventh switch transistor M7. The control terminal of the eleventh switch transistor M11 is connected to the control terminal of the twelfth switch transistor M12 and is also connected to the second current terminal of the eleventh switch transistor M11. The first current terminal of the twelfth switch transistor M12 is directly connected to the second power supply VDDH, and the second current terminal of the twelfth switch transistor M12 is connected to the reference ground GND via the eighth switch transistor M8.

[0114] In this example, the seventh switch transistor M7 and the eighth switch transistor M8 are NMOS transistors, and the ninth switch transistor M9, the eleventh switch transistor M11, and the twelfth switch transistor M12 are PMOS transistors.

[0115] In this example, for example, the high level of the input voltage VIN is set to VDDL, the high levels of the first voltage VN and the second voltage VP are both 2*VDDL, and the low levels of the input voltage VIN, the first voltage VN and the second voltage VP are all 0.

[0116] When the input voltage VIN is high, the first voltage VN provided by the bootstrap circuit 110 is low, and the second voltage VP is high. The seventh switch M7 is turned on, and the eighth switch M8 is turned off. The gate voltage of the eleventh switch M11 is pulled down to the reference ground GND (typically 0 level), turning on the eleventh and twelfth switches M11 and M12. The output voltage VOUT provided by the output terminal of the level shifter circuit 120 is pulled up to VDDH. At this time, the ninth switch M9 is turned off, closing the leakage path. This prevents leakage current, eliminates static current, and reduces circuit power consumption.

[0117] When the input voltage VIN is low, the first voltage VN provided by the bootstrap circuit 110 is high and the second voltage VP is low. The seventh switch M7 is turned off and the eighth switch M8 is turned on. The output voltage VOUT provided by the output terminal of the level shifter circuit 120 is pulled down to the reference ground GND voltage.

[0118] In this embodiment, a ninth switch tube M9 is provided for eliminating static current, thus having the advantages of low power consumption and anti-leakage.

[0119] It should be understood that the circuit structure of the level shifter circuit 120 is merely an illustrative example. Those skilled in the art can achieve the same or similar technical effects by changing parameters such as the type of the switch tube and the corresponding circuit connections. Furthermore, the output voltage VOUT can be adjusted by adjusting the voltage of the second power supply VDDH.

[0120] In summary, the embodiment of the present invention provides a circuit for level conversion. By using a control voltage with a relatively high voltage amplitude to control the level conversion circuit 120 to perform level conversion, a relatively large current can be generated, thereby significantly improving the level conversion speed.

[0121] In some optional embodiments, the circuit improves the current mirror circuit, eliminates the static current, and has the advantages of low power consumption and leakage prevention.

[0122] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0123] While embodiments of the present invention have been described above, these embodiments do not exhaustively describe all details and do not limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A circuit for level conversion, comprising: A bootstrap circuit, configured to convert an input voltage into a control voltage, the bootstrap circuit comprising a first branch and a second branch having the same circuit structure; as well as The level conversion circuit includes a plurality of switch tubes, which are used to provide an output voltage according to the control voltage, wherein the level of the output voltage is higher than the level of the input voltage. The voltage amplitude of the control voltage is greater than the threshold voltage of the switch tube of the level conversion circuit. The first branch includes: a first inverter, configured to convert the input voltage into a first intermediate voltage; a first capacitor, a second end of which is connected to the output end of the first inverter; a first switch tube, connected between a first power supply and a first end of the first capacitor, wherein a control end of the first switch tube is connected to a first end of a second capacitor; a second switch tube, connected between the first end of the first capacitor and the first output end; a third switch tube, connected between the first output terminal and a reference ground; The second branch includes: a second inverter connected to an output terminal of the first inverter, configured to convert the first intermediate voltage into a second intermediate voltage; a second capacitor, a second end of which is connected to the output end of the second inverter; a fourth switch tube, connected between the first power supply and the first end of the second capacitor, wherein the control end of the fourth switch tube is connected to the second end of the first capacitor; a fifth switching tube, connected between the first terminal and the second output terminal of the second capacitor; a sixth switch tube, connected between the second output terminal and the reference ground, The level conversion circuit includes: a seventh switching tube, an eighth switching tube, and a ninth switching tube connected in sequence between the second power supply and the reference ground, and a tenth switching tube, an eleventh switching tube, and a twelfth switching tube connected in sequence between the second power supply and the reference ground; or the level conversion circuit includes: a current mirror circuit including a third branch and a fourth branch; a seventh switching tube connected to the third branch; and an eighth switching tube connected to the fourth branch.

2. The circuit according to claim 1, wherein The voltage amplitude of the control voltage is greater than or equal to twice the voltage amplitude of the input voltage.

3. The circuit according to claim 1, wherein The control voltage includes a first voltage and a second voltage that are complementary, The first branch uses a first capacitor to charge and discharge to obtain the first voltage; The second branch uses the second capacitor to charge and discharge to obtain the second voltage, The charging and discharging paths of the first branch and the second branch are controlled by the input voltage.

4. The circuit according to claim 3, wherein When the input voltage is at a high level, the first power supply charges the first capacitor, the first voltage is pulled down to the reference ground, the second capacitor starts to discharge to provide the second voltage, and the path from the second voltage to the reference ground is cut off; When the input voltage is at a low level, the first capacitor starts to discharge to provide the first voltage, the path from the first voltage to the reference ground is cut off, the first power supply charges the second capacitor, and the second voltage is pulled down to the reference ground.

5. The circuit according to claim 4, wherein The second switch tube and the third switch tube are controlled by the second intermediate voltage, and the fifth switch tube and the sixth switch tube are controlled by the first intermediate voltage; the first switch tube, the third switch tube, the fourth switch tube and the sixth switch tube have the same conduction type, which is opposite to the conduction type of the second switch tube and the fifth switch tube.

6. The circuit according to claim 1, wherein The control voltage includes a complementary first voltage and a second voltage. The control terminal of the eighth switch tube is connected to the control terminal of the ninth switch tube and receives the second voltage. The control terminal of the eleventh switch tube is connected to the control terminal of the twelfth switch tube and receives the first voltage. The control terminal of the seventh switch tube is connected to a second node between the eleventh switch tube and the twelfth switch tube. The control terminal of the tenth switch tube is connected to a first node between the eighth switch tube and the ninth switch tube. The second node provides the output voltage. The voltage amplitude of the control voltage is greater than the threshold voltages of the eighth switching tube, the ninth switching tube, the eleventh switching tube, and the twelfth switching tube.

7. The circuit according to claim 1, wherein The control voltage includes a complementary first voltage and a second voltage. The control terminal of the ninth switch tube receives the second voltage, and the control terminal of the twelfth switch tube receives the first voltage. The control terminals of the seventh switch tube and the eleventh switch tube are respectively connected to a first node between the eighth switch tube and the ninth switch tube. The control terminals of the eighth switch tube and the tenth switch tube are respectively connected to a second node between the eleventh switch tube and the twelfth switch tube. The second node provides the output voltage. The voltage amplitude of the control voltage is greater than the threshold voltages of the ninth switching tube and the twelfth switching tube.

8. The circuit according to claim 1, wherein The control voltage includes a complementary first voltage and a second voltage, the level conversion circuit includes the current mirror circuit, the seventh switch tube and the eighth switch tube, the seventh switch tube is controlled by the second voltage, and the eighth switch tube is controlled by the first voltage. The voltage amplitude of the control voltage is greater than the threshold voltages of the seventh switching tube and the eighth switching tube.

9. The circuit according to claim 1, wherein The control voltage includes a complementary first voltage and a second voltage. The level conversion circuit includes the current mirror circuit, the seventh switch tube, the eighth switch tube, and a ninth switch tube. The seventh switch tube is controlled by the second voltage, the eighth switch tube is controlled by the first voltage, and the ninth switch tube is connected between the second power supply and the third branch, or between the third branch and the seventh switch tube, and is controlled by the output voltage. When the output voltage is at a high level, the ninth switch is turned off. The voltage amplitude of the control voltage is greater than the threshold voltages of the seventh switching tube and the eighth switching tube.

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