Offset correction circuit, offset correction system and driving chip

Abstract

The invention discloses an offset correction circuit, an offset correction system and a driving chip, and relates to the technical field of analog-to-digital converter correction, and the disclosed offset correction circuit comprises a control module and a correction module; the control module is respectively connected with the analog-to-digital converter and the correction module; the correction module is connected with the analog-to-digital converter; the correction module is used for performing parameter correction on the analog-to-digital converter when the circuit is powered on, and transmitting a correction completion signal to the control module when the parameter correction is completed; the control module is used for comparing the correction completion signal with a preset completion signal and acquiring the power of the analog-to-digital converter when the correction completion signal is consistent with the preset completion signal; and the control module is also used for performing power correction on the analog-to-digital converter, so that the output power of the analog-to-digital converter reaches a preset power range.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital converter calibration, and particularly to an offset calibration circuit, an offset calibration system, and a driver chip. Background Art

[0002] In recent years, with the update and progress of wireless communication technologies, the bandwidth, speed, and power consumption of analog-to-digital converters have been driven to develop in a more optimal direction, and continuous-time delta-sigma ADCs (Delta-Sigma Analog-to-Digital Converters) have emerged as the times require. To improve the performance of continuous-time delta-sigma ADCs, the sampling clock rate has become increasingly high, reaching up to GHz (gigahertz), and the requirements for quantizers have also become higher and higher. Therefore, a full-dynamic comparator is used in the quantizer. This comparator has a high speed, but has a large offset and noise. The large offset voltage will cause the transfer function of the continuous-time delta-sigma ADC to change, resulting in a decline in the performance of the analog-to-digital converter or system oscillation.

[0003] The above content is only used to assist in understanding the technical solution of the present invention, and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main object of the present invention is to provide an offset calibration circuit, an offset calibration system, and a driver chip, aiming to solve the technical problem of the decline in the performance of the analog-to-digital converter.

[0005] To achieve the above object, the present invention proposes an offset calibration circuit. The offset calibration circuit is applied to an analog-to-digital converter, and the offset calibration circuit includes:

[0006] A control module and a calibration module;

[0007] The control module is respectively connected to the analog-to-digital converter and the calibration module; the calibration module is connected to the analog-to-digital converter;

[0008] The calibration module is configured to calibrate the parameters of the analog-to-digital converter when the circuit is powered on, and transmit a calibration completion signal to the control module when the parameter calibration is completed;

[0009] The control module is configured to compare the calibration completion signal with a preset completion signal, and obtain the power of the analog-to-digital converter when the calibration completion signal is consistent with the preset completion signal;

[0010] The control module is further configured to perform power calibration on the analog-to-digital converter so that the output power of the analog-to-digital converter reaches a preset power range.

[0011] In one embodiment, the data correction includes DAC correction, quantizer correction, and RC parameter correction. The correction completion signal includes a DAC correction completion signal, a quantizer correction completion signal, and an RC correction completion signal. The correction module includes:

[0012] A DAC correction subunit, a quantizer correction subunit, and an RC correction subunit;

[0013] The control module and the analog-to-digital converter are respectively connected to the DAC correction subunit, the quantizer correction subunit, and the RC correction subunit;

[0014] The DAC correction subunit is configured to perform the DAC correction on the analog-to-digital converter when the circuit is powered on, and transmit the DAC correction completion signal to the control module when the DAC correction is completed;

[0015] The quantizer correction subunit is configured to perform the quantizer correction on the analog-to-digital converter when the DAC correction is completed, and transmit the quantizer correction completion signal to the control module when the quantizer correction is completed;

[0016] The RC correction subunit is configured to perform the RC parameter correction on the analog-to-digital converter when the quantizer correction is completed, and transmit the RC correction completion signal to the control module when the RC parameter correction is completed.

[0017] In one embodiment, the preset completion signal includes a DAC preset completion signal, a quantizer preset completion signal, and an RC preset completion signal. The control module includes:

[0018] A DAC control subunit, a quantizer control subunit, and an RC control subunit;

[0019] The DAC control subunit is respectively connected to the quantizer control subunit, the DAC correction subunit, and the quantizer correction subunit; the quantizer control subunit is respectively connected to the RC control subunit and the quantizer correction subunit; the RC control subunit is respectively connected to the RC correction subunit and the analog-to-digital converter;

[0020] The DAC control subunit is configured to compare the DAC correction completion signal with the DAC preset completion signal, and send a first execution signal to the quantizer control subunit when the DAC correction completion signal is consistent with the DAC preset completion signal;

[0021] The quantizer control sub-unit is configured to compare the quantizer calibration completion signal with the quantizer preset completion signal when receiving the first execution signal, and send a second execution signal to the RC control sub-unit when the quantizer calibration completion signal is consistent with the quantizer preset completion signal;

[0022] The RC control sub-unit is configured to compare the RC calibration completion signal with the RC preset completion signal when receiving the second execution signal, and obtain the power of the analog-to-digital converter when the RC calibration completion signal is consistent with the RC preset completion signal.

[0023] In one embodiment, the offset correction circuit further includes:

[0024] A clock module;

[0025] The clock module is respectively connected to the control module and the analog-to-digital converter;

[0026] The clock module is configured to provide clock signals to the analog-to-digital converter and the control module.

[0027] In one embodiment, the offset correction circuit further includes:

[0028] A downsampling module;

[0029] The downsampling module is connected to the analog-to-digital converter;

[0030] The downsampling module is configured to reduce the data volume of the power.

[0031] In one embodiment, the offset correction circuit further includes:

[0032] A power detection module;

[0033] The power detection module is respectively connected to the downsampling module and the control module;

[0034] The power detection module is configured to obtain the power with reduced data volume, compare the power with the preset power range, and send a power correction signal to the control module when the power does not reach the preset power range.

[0035] In one embodiment, the control module is further configured to transmit a calibration execution signal to the calibration module when detecting that the circuit is powered on.

[0036] In one embodiment, the control module is further configured to perform power correction on the analog-to-digital converter according to the power correction signal, so that the output power of the analog-to-digital converter reaches the preset power range.

[0037] In addition, to achieve the above object, the present invention further provides an offset correction system, and the offset correction system includes the above-mentioned offset correction circuit.

[0038] In addition, to achieve the above object, the present invention further provides a driving chip, and the driving chip includes the above-mentioned analog-to-digital converter and offset correction circuit, and the analog-to-digital converter is connected to the offset correction circuit.

[0039] One or more technical solutions proposed by the present invention have at least the following technical effects:

[0040] The offset correction circuit of the present invention includes: a control module and a correction module; the control module is respectively connected to the analog-to-digital converter and the correction module; the correction module is connected to the analog-to-digital converter; the correction module is used to perform parameter correction on the analog-to-digital converter when the circuit is powered on, and transmit a correction completion signal to the control module when the parameter correction is completed; the control module is used to compare the correction completion signal with a preset completion signal, and obtain the power of the analog-to-digital converter when the correction completion signal is consistent with the preset completion signal; the control module is further used to perform power correction on the analog-to-digital converter so that the output power of the analog-to-digital converter reaches a preset power range. By performing DAC correction, quantizer correction, and RC parameter correction on the analog-to-digital converter, the performance of the analog-to-digital converter is improved. Description of the Drawings

[0041] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention.

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0043] Figure 1 It is a schematic structural diagram provided for Embodiment 1 of the offset correction circuit of the present invention;

[0044] Figure 2 It is a schematic structural diagram provided for Embodiment 2 of the offset correction circuit of the present invention.

[0045] Explanation of the Reference Numerals in the Drawings:

[0046]

[0047]

[0048] The implementation, functional features, and advantages of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0049] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0050] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present invention, such directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0051] In addition, if there are descriptions such as "first", "second", etc. involved in the embodiments of the present invention, such descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, if "and / or" or "and / or" appears throughout the text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or a solution where A and B are satisfied simultaneously. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0052] With the update and progress of wireless communication technologies, the bandwidth, speed, and power consumption of analog-to-digital converters are driven to develop in a more optimal direction, and the continuous-time delta-sigma ADC (Delta-Sigma Analog-to-Digital Converter) emerges as the times require. To improve the performance of the continuous-time delta-sigma ADC, the rate of the sampling clock is getting higher and higher, reaching up to GHz (gigahertz), and the requirements for the quantizer are also getting higher and higher. Therefore, a fully dynamic comparator is adopted in the quantizer. This comparator has a high speed, but has a large offset and noise. The large offset voltage will cause the transfer function of the continuous-time delta-sigma ADC to change, resulting in a decline in the performance of the analog-to-digital converter or system oscillation.

[0053] To solve the above problems, the present invention proposes an offset correction circuit, aiming to solve the technical problem of the decline in the performance of the analog-to-digital converter.

[0054] Reference Figure 1 , Figure 1 is a schematic structural diagram provided for the first embodiment of the offset correction circuit of the present invention. The offset correction circuit is applied to the analog-to-digital converter 3, and the offset correction circuit includes:

[0055] a control module 1 and a correction module 2;

[0056] The control module 1 is respectively connected to the analog-to-digital converter 3 and the correction module 2; the correction module 2 is connected to the analog-to-digital converter 3;

[0057] The correction module 2 is configured to perform data correction on the analog-to-digital converter 3 when the circuit is powered on, and transmit a correction completion signal to the control module 1 when the data correction is completed;

[0058] The control module 1 is configured to compare the correction completion signal with a preset completion signal, and obtain the power of the analog-to-digital converter 3 when the correction completion signal is consistent with the preset completion signal;

[0059] The control module 1 is further configured to perform power correction on the analog-to-digital converter 3 to make the output power of the analog-to-digital converter 3 reach a preset power range.

[0060] It should be noted that in this embodiment, the above analog-to-digital converter is a continuous-time delta-sigma ADC (Delta-Sigma Analog-to-Digital Converter);

[0061] It should be noted that the above preset power range can be the power range when the accuracy and dynamic performance of the above analog-to-digital converter 3 both reach the target requirements under PVT (Process, Voltage, Temperature) conditions, and the specific range is calibrated by technical personnel according to actual requirements.

[0062] In a specific implementation, when the above-mentioned calibration module 2 powers on the entire above-mentioned offset calibration circuit, it performs data calibration on the above-mentioned analog-to-digital converter 3, and transmits the above-mentioned calibration completion signal to the above-mentioned control module 1 when the above-mentioned data calibration is completed. After receiving the above-mentioned calibration completion signal, the above-mentioned control module 1 compares it with the above-mentioned preset completion signal. If the above-mentioned calibration completion signal is consistent with the above-mentioned preset completion signal, it obtains the power of the above-mentioned analog-to-digital converter 3. If the above-mentioned calibration completion signal is inconsistent with the above-mentioned preset completion signal, it controls the above-mentioned calibration module 2 to re-perform the above-mentioned data calibration on the above-mentioned analog-to-digital converter 3, and repeats until the above-mentioned calibration completion signal is consistent with the above-mentioned preset completion signal. The above-mentioned control module 1 is also used to perform power calibration on the above-mentioned analog-to-digital converter 3. If the power output by the above-mentioned analog-to-digital converter 3 reaches the above-mentioned preset power range, it stops the power calibration work of the above-mentioned control module 1. If the power output by the above-mentioned analog-to-digital converter 3 does not reach the above-mentioned preset power range, it controls the capacitor array in the above-mentioned calibration module 3 to calibrate the output power of the above-mentioned analog-to-digital converter 3. Through the above-mentioned data calibration and power calibration, the performance of the above-mentioned analog-to-digital converter in the working state is ensured.

[0063] To ensure that the above-mentioned analog-to-digital converter 3 is more accurate and efficient during the calibration process, refer to Figure 2 , Figure 2 which is the structural schematic diagram provided by the second embodiment of the offset calibration circuit of the present invention.

[0064] In this embodiment, the data calibration includes DAC calibration, quantizer calibration, and RC parameter calibration. The calibration completion signal includes a DAC calibration completion signal, a quantizer calibration completion signal, and an RC calibration completion signal. The calibration module 2 includes:

[0065] a DAC calibration sub-unit 21, a quantizer calibration sub-unit 22, and an RC calibration sub-unit 23;

[0066] The above-mentioned control module 1 and the above-mentioned analog-to-digital converter 3 are respectively connected to the above-mentioned DAC calibration sub-unit 21, the above-mentioned quantizer calibration sub-unit 22, and the above-mentioned RC calibration sub-unit 23;

[0067] The DAC calibration sub-unit 21 is used to perform the DAC calibration on the above-mentioned analog-to-digital converter 3 when the circuit powers on, and transmit the DAC calibration completion signal to the above-mentioned control module 1 when the DAC calibration is completed;

[0068] The quantizer calibration sub-unit 22 is used to perform the quantizer calibration on the above-mentioned analog-to-digital converter 3 when the DAC calibration is completed, and transmit the quantizer calibration completion signal to the above-mentioned control module 1 when the quantizer calibration is completed;

[0069] The RC calibration subunit 23 is configured to perform the RC parameter calibration on the analog-to-digital converter 3 when the quantizer calibration is completed, and transmit the RC calibration completion signal to the control module 1 when the RC parameter calibration is completed.

[0070] It should be noted that the above DAC calibration is current source mismatch calibration. Current source mismatch calibration refers to the process of calibrating the current source to eliminate or reduce its mismatch error. In a current-steering digital-to-analog converter (DAC), the mismatch of the current source will have a negative impact on the linearity and performance of the DAC.

[0071] It should be noted that the above quantizer calibration is comparator offset calibration. The reasons for comparator offset may include manufacturing process deviations, temperature changes, power supply voltage fluctuations, and component aging, etc. These factors may cause changes in the input offset voltage or offset current of the comparator, thus affecting its normal operation.

[0072] It should be noted that the above RC parameter calibration is to correct and adjust the resistance and capacitance values in the circuit.

[0073] It can be understood that the above DAC calibration completion signal, the above quantizer calibration completion signal, and the above RC calibration completion signal are all high-level signals.

[0074] In a specific implementation, when the circuit is powered on, the above DAC calibration subunit 21 performs the above DAC calibration on the analog-to-digital converter 3, and transmits the above DAC calibration completion signal to the control module 1 when the DAC calibration is completed. The quantizer calibration subunit 22 is configured to perform the above quantizer calibration on the analog-to-digital converter 3 when the DAC calibration is completed, and transmit the above quantizer calibration completion signal to the control module 1 when the quantizer calibration is completed; wherein, the steps of the above DAC calibration and the above quantizer calibration can be interchanged. The above RC calibration subunit is configured to perform the above RC parameter calibration on the analog-to-digital converter 3 when both the above DAC calibration and the above quantizer calibration are completed, and transmit the above RC calibration completion signal to the control module 1 when the RC parameter calibration is completed, wherein the above RC parameter calibration is performed as the last step.

[0075] In an embodiment, the preset completion signal includes a DAC preset completion signal, a quantizer preset completion signal, and an RC preset completion signal. The control module 1 includes:

[0076] A DAC control subunit 11, a quantizer control subunit 12, and an RC control subunit 13;

[0077] The DAC control sub-unit 11 is respectively connected to the quantizer control sub-unit 12, the DAC calibration sub-unit 21, and the quantizer calibration sub-unit 22; the quantizer control sub-unit 12 is respectively connected to the RC control sub-unit 13 and the quantizer calibration sub-unit 22; the RC control sub-unit 13 is respectively connected to the RC calibration sub-unit 23 and the analog-to-digital converter 3;

[0078] The DAC control sub-unit 11 is configured to compare the DAC calibration completion signal with the DAC preset completion signal, and when the DAC calibration completion signal is consistent with the DAC preset completion signal, send a first execution signal to the quantizer control sub-unit 12;

[0079] The quantizer control sub-unit 12 is configured to, when receiving the first execution signal, compare the quantizer calibration completion signal with the quantizer preset completion signal, and when the quantizer calibration completion signal is consistent with the quantizer preset completion signal, send a second execution signal to the RC control sub-unit 13;

[0080] The RC control sub-unit 13 is configured to, when receiving the second execution signal, compare the RC calibration completion signal with the RC preset completion signal, and when the RC calibration completion signal is consistent with the RC preset completion signal, obtain the power of the analog-to-digital converter 3.

[0081] It should be noted that in order to meet the timing working problem of the circuit, the above first execution signal is used to control the quantizer control sub-unit 12 to work when the DAC control sub-unit 11 finishes working, and the above second execution signal is used to control the RC control sub-unit 13 to work when the quantizer control sub-unit 12 finishes working.

[0082] It can be understood that the above DAC preset completion signal is a signal with 16-bit data precision, the above first execution signal is a signal with 128-bit data precision, the above quantizer preset completion signal and the above second execution signal are signals with 64-bit data precision, and the above RC preset completion signal is a signal with 8-bit data precision.

[0083] In a specific implementation, the above-mentioned DAC control sub-unit 11 is used to compare the above-mentioned DAC calibration completion signal with the above-mentioned DAC preset completion signal, and when the above-mentioned DAC calibration completion signal is consistent with the above-mentioned DAC preset completion signal, send the above-mentioned first execution signal to the above-mentioned quantizer control sub-unit; the above-mentioned quantizer control sub-unit 12 is used to compare the above-mentioned quantizer calibration completion signal with the above-mentioned quantizer preset completion signal when receiving the above-mentioned first execution signal, and when the above-mentioned quantizer calibration completion signal is consistent with the above-mentioned quantizer preset completion signal, send the above-mentioned second execution signal to the above-mentioned RC control sub-unit 13; the above-mentioned RC control sub-unit 13 is used to compare the above-mentioned RC calibration completion signal with the above-mentioned RC preset completion signal when receiving the above-mentioned second execution signal, and when the above-mentioned RC calibration completion signal is consistent with the above-mentioned RC preset completion signal, obtain the power of the above-mentioned analog-to-digital converter 3.

[0084] In one embodiment, the offset correction circuit further includes:

[0085] A clock module 4;

[0086] The clock module 4 is respectively connected to the control module 1 and the analog-to-digital converter 3;

[0087] The clock module 4 is used to provide clock signals to the analog-to-digital converter 3 and the control module 1.

[0088] In a specific implementation, the above-mentioned clock module 4 is used to provide clocks to the above-mentioned control module 1 and the above-mentioned analog-to-digital converter 3. Since the clock rate of the above-mentioned analog-to-digital converter is very high, when the circuit operates at this rate up to GHz, it will cause timing chaos and high power consumption. Therefore, it is necessary to perform frequency division processing on the clock of the above-mentioned analog-to-digital converter 3. Low-speed frequency division is adopted in the above-mentioned DAC calibration and the above-mentioned quantizer calibration, and normal clocks are adopted in the above-mentioned RC parameter calibration and normal operation. To ensure that the two clocks do not affect each other, when the above-mentioned control module 1 uses a low-speed clock during the above-mentioned DAC calibration and the above-mentioned quantizer calibration, the clock is automatically turned off after the calibration is completed, and a high-speed clock starts to be output.

[0089] In one embodiment, the offset correction circuit further includes:

[0090] A decimation module 5;

[0091] The decimation module 5 is connected to the analog-to-digital converter 3;

[0092] The decimation module 5 is used to reduce the data volume of the power.

[0093] In a specific implementation, due to the relatively high clock frequency, it is difficult for the above-mentioned offset correction circuit to operate at such a high frequency. Therefore, it is necessary to reduce the sampling rate for subsequent digital processing, that is, to reduce the amount of data of the above-mentioned power.

[0094] In one embodiment, the offset correction circuit further includes:

[0095] A power detection module 6;

[0096] The power detection module 6 is respectively connected to the downsampling module 5 and the control module 1;

[0097] The power detection module 6 is configured to obtain the power of the reduced data volume, compare the power with the preset power range, and send a power correction signal to the control module 1 when the power does not reach the preset power range.

[0098] In a specific implementation, the above-mentioned power detection module 6 is configured to compare the above-mentioned power with the above-mentioned preset power range, and send the above-mentioned power correction signal to the above-mentioned control module 1 when the above-mentioned power does not reach the above-mentioned preset power range.

[0099] In one embodiment, the control module 1 is further configured to transmit a correction execution signal to the correction module 2 when detecting that the circuit is powered on.

[0100] It should be noted that the above-mentioned correction execution signal is used to activate the above-mentioned correction module 2.

[0101] In a specific implementation, the above-mentioned control module 1 transmits the above-mentioned correction execution signal to the above-mentioned correction module 2 when detecting that the circuit is powered on.

[0102] In one embodiment, the control module 1 is further configured to perform power correction on the analog-to-digital converter 3 according to the power correction signal, so that the output power of the analog-to-digital converter reaches the preset power range.

[0103] In a specific implementation, the above-mentioned control module 1 is further configured to control the capacitor array in the above-mentioned RC correction module 23 to adjust the power of the above-mentioned analog-to-digital converter 3 according to the above-mentioned power correction signal, that is, to perform power correction on the above-mentioned analog-to-digital converter 3 so that the output power of the above-mentioned analog-to-digital converter 3 reaches the preset power range.

[0104] In addition, to achieve the above object, the present invention also proposes an offset correction system, and the offset correction system includes the offset correction circuit as described above. Other embodiments or specific implementation manners of the offset correction system of the present invention can refer to the embodiments of the above-mentioned offset correction circuit, which will not be elaborated here.

[0105] In addition, to achieve the above object, the present invention further provides a driving chip, which includes the analog-to-digital converter and the offset correction circuit as described above. Other embodiments or specific implementation manners of the driving chip of the present invention may refer to the embodiments of the above offset correction circuit, which will not be elaborated herein.

[0106] The above description is only an exemplary embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structural transformation made under the technical concept of the present invention by using the content of the specification and drawings of the present invention, or direct / indirect application in other related technical fields is included in the patent protection scope of the present invention.

Claims

1. An offset correction circuit, characterized in that: The offset correction circuit is applied to an analog-to-digital converter, and the offset correction circuit comprises: Control module and correction module; The control module is connected to the analog-to-digital converter and the correction module respectively; the correction module is connected to the analog-to-digital converter; The correction module is used to perform data correction on the analog-to-digital converter when the circuit is powered on, and transmit a correction completion signal to the control module when the data correction is completed; The control module is used to compare the calibration completion signal with a preset completion signal, and obtain the power of the analog-to-digital converter when the calibration completion signal is consistent with the preset completion signal; The control module is further used to perform power calibration on the analog-to-digital converter so that the output power of the analog-to-digital converter reaches a preset power range.

2. The offset correction circuit according to claim 1, wherein: The data correction includes DAC correction, quantizer correction and RC parameter correction, the correction completion signal includes a DAC correction completion signal, a quantizer correction completion signal and an RC correction completion signal, and the correction module includes: DAC correction subunit, quantizer correction subunit and RC correction subunit; The control module and the analog-to-digital converter are connected to the DAC correction subunit, the quantizer correction subunit and the RC correction subunit respectively; The DAC correction subunit is used to perform the DAC correction on the analog-to-digital converter when the circuit is powered on, and transmit the DAC correction completion signal to the control module when the DAC correction is completed; The quantizer correction subunit is used to perform the quantizer correction on the analog-to-digital converter when the DAC correction is completed, and transmit the quantizer correction completion signal to the control module when the quantizer correction is completed; The RC correction subunit is used to perform the RC parameter correction on the analog-to-digital converter when the quantizer correction is completed, and transmit the RC correction completion signal to the control module when the RC parameter correction is completed.

3. The offset correction circuit according to claim 2, wherein: The preset completion signal includes a DAC preset completion signal, a quantizer preset completion signal and an RC preset completion signal, and the control module includes: DAC control subunit, quantizer control subunit and RC control subunit; The DAC control subunit is connected to the quantizer control subunit, the DAC correction subunit and the quantizer correction subunit respectively; the quantizer control subunit is connected to the RC control subunit and the quantizer correction subunit respectively; the RC control subunit is connected to the RC correction subunit and the analog-to-digital converter respectively; The DAC control subunit is used to compare the DAC correction completion signal with the DAC preset completion signal, and send a first execution signal to the quantizer control subunit when the DAC correction completion signal is consistent with the DAC preset completion signal; The quantizer control subunit is configured to compare the quantizer correction completion signal with the quantizer preset completion signal upon receiving the first execution signal, and send a second execution signal to the RC control subunit when the quantizer correction completion signal is consistent with the quantizer preset completion signal; The RC control subunit is used to compare the RC correction completion signal with the RC preset completion signal when receiving the second execution signal, and obtain the power of the analog-to-digital converter when the RC correction completion signal is consistent with the RC preset completion signal.

4. The offset correction circuit according to claim 3, characterized in that: The offset correction circuit further includes: Clock module; The clock module is connected to the control module and the analog-to-digital converter respectively; The clock module is used to provide a clock signal to the analog-to-digital converter and the control module.

5. The offset correction circuit according to claim 4, characterized in that: The offset correction circuit further includes: Downsampling module; The downsampling module is connected to the analog-to-digital converter; The downsampling module is used to reduce the amount of data of the power.

6. The offset correction circuit according to claim 5, characterized in that: The offset correction circuit further includes: Power detection module; The power detection module is connected to the down-sampling module and the control module respectively; The power detection module is used to obtain the power for reducing the amount of data, compare the power with the preset power range, and send a power correction signal to the control module when the power does not reach the preset power range.

7. The offset correction circuit according to claim 6, wherein: The control module is further configured to transmit a correction execution signal to the correction module when it is detected that the circuit is powered on.

8. The offset correction circuit according to claim 6, wherein: The control module is further used to perform power correction on the analog-to-digital converter according to the power correction signal, so that the output power of the analog-to-digital converter reaches the preset power range.

9. An offset correction system, characterized in that: The offset correction system comprises: the offset correction circuit according to any one of claims 1 to 7.

10. A driver chip, characterized in that: The driving chip comprises: an analog-to-digital converter and the offset correction circuit according to any one of claims 1 to 7, and the analog-to-digital converter is connected to the offset correction circuit.

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