CDAC Self-Calibration Method Based on Noise Shaping Successive Approximation Analog-to-Digital Converter

Abstract

The present invention discloses a CDAC self-calibration method based on a noise-shaping successive approximation analog-to-digital converter (A / D converter). The method reuses the capacitors and redundant capacitors in the lower section of the capacitor array, a noise-shaping filter circuit, a comparator, and a SAR logic circuit as a Z-ADC with ideal weight coefficients to quantize the voltage change generated by the capacitor to be calibrated. To improve the accuracy of the calibration, the present invention performs multiple resets and quantizations on the same capacitor to be calibrated, which is equivalent to oversampling. Combined with noise-shaping technology, it greatly suppresses the quantization noise within the bandwidth and ensures the accuracy of the calibration. After completing the capacitance calibration of the current bit, the present invention incorporates it into the Z-ADC as the highest bit, and calibrates the higher bits in sequence until the highest bit.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-to-digital converters, and in particular relates to a CDAC self-calibration method based on a noise shaping successive approximation analog-to-digital converter. Background Art

[0002] Analog-to-digital converters (ADCs) convert analog signals from the environment into digital signals for processing by processors. They are essential modules in fields such as communications, the Internet of Things, and biomedicine. Among various ADC architectures, successive approximation register (SAR) ADCs offer low power consumption due to their highly digital structure, making them widely used in low- to medium-speed (1kHz to 100MHz) and medium-precision (8 to 12-bit) scenarios. However, SAR ADCs are limited by quantization noise and capacitor mismatch errors in the capacitor array (CDAC), making it difficult to develop high-precision ADCs. To maintain their low power consumption and achieve high precision (greater than 14 bits), noise-shaping (NS) SAR ADCs combine delta-sigma modulation and oversampling techniques to effectively suppress quantization noise within the bandwidth. Therefore, calibrating the capacitor mismatch error of the CDAC becomes a challenge that needs to be addressed.

[0003] Capacitor mismatch error in a CDAC refers to the deviation between the actual and designed capacitance values in a chip. This deviation arises from the chip's manufacturing process. This mismatch error alters the proportional weighting coefficients between high-order and low-order capacitances, creating nonlinearity and hindering the development of high-precision ADCs.

[0004] Existing CDAC calibration techniques can be roughly divided into two categories. The first is split-ADC technology (e.g., [Wang Mingyue. Research and Implementation of a High-Precision Successive Approximation Analog-to-Digital Converter Calibration Algorithm]. Xi'an: Xidian University, 2023]). This technique, with its fast convergence speed, is used for both foreground and background calibration. However, it requires splitting a single ADC design into two sub-ADCs, significantly increasing circuit power consumption and area. The second is self-calibration technology (e.g., Chinese patent application publication number CN117879603A). This is primarily used in the calibration of high-precision SAR ADCs, leveraging its low quantization noise to calibrate the actual weight coefficients from low to high bits. However, the CDAC of a high-precision noise-shaping successive approximation ADC is typically around 10 bits, and the remaining quantization noise after 10 conversions is still significant. Therefore, simply applying self-calibration technology from SAR ADCs to the calibration process of noise-shaping successive approximation ADCs cannot support the high-precision design goals. Summary of the Invention

[0005] In view of the above, the present invention provides a CDAC self-calibration method based on a noise-shaping successive approximation analog-to-digital converter, which can realize the calibration of the CDAC weight coefficient and improve the linearity of the noise-shaping successive approximation ADC.

[0006] A CDAC self-calibration method based on a noise shaping successive approximation analog-to-digital converter (A / D converter) comprises the following steps:

[0007] (1) Initially, the lowest i-1 capacitors C1, C2, ..., C i-1 Considered as a CDAC with ideal weight coefficients, it is denoted as calibration CDAC, where C i-1 is a redundant capacitor, and the rest are bit capacitors, i-1<N, N is the number of bits of the noise shaping successive approximation analog-to-digital converter;

[0008] (2) The calibration CDAC, noise shaping filter circuit, comparator and SAR logic circuit are combined to form an ideal noise shaping successive approximation analog-to-digital converter, denoted as Z-ADC, which is used to calibrate the capacitor C in the capacitor array. i (capacitance to be calibrated);

[0009] (3) Switch C i The lower plate of the capacitor is at high potential, and the Z-ADC is used to calibrate it to obtain C i The weight coefficient calibration matrix D i,set1 ;

[0010] (4) Switch C i The lower plate of the CMOS is at ground potential, and the Z-ADC is used to calibrate it to obtain C i The weight coefficient calibration matrix D i,set0;

[0011] (5) D i,set1 -D i,set0 The result is digitally filtered and averaged to obtain C i The true weight coefficient w i , thus completing the capacitor C i calibration;

[0012] (6) Let i = i + 1, and determine whether i > N: If so, the weight coefficient matrix W corresponding to Z-ADC is used as the final weight coefficient matrix, the calibration is completed, and the calibration mode is exited; if not, C i Incorporate into the calibration CDAC, w i Incorporate the weight coefficient matrix W and return to step (3) to start the next calibration.

[0013] Furthermore, the noise-shaping successive approximation analog-to-digital converter includes a capacitor array, a noise-shaping filter circuit, a comparator, a SAR logic circuit, a calibration control circuit, and a digital filter weight calculation circuit. The analog-to-digital converter has two operating modes, namely, a calibration mode and a conversion mode. In the calibration mode, the ADC performs calibration work, and in the conversion mode, the ADC performs normal analog-to-digital conversion work.

[0014] Furthermore, the specific implementation of step (3) is as follows: first switch C i The lower plate of the capacitor is 1, that is, high potential, so that the upper plate of the entire capacitor array appears to represent C i Voltage change of weight coefficient +V i , use Z-ADC to convert +V i Quantize into digital code; repeat the above process for K times, and store the digital code obtained in these K cycles into a K×(i-1) size matrix DOUT in the calibration control circuit i,set1 , K is a natural number greater than 1; then C is obtained by matrix multiplication i The weight coefficient calibration matrix D i,set1 =DOUT i,set1 ×W,W=[w i-1 ,w i-2 ,…,w1] T , that is, C i The weight coefficient when the K-th lower plate is set to 1.

[0015] Furthermore, the specific implementation of step (4) is as follows: first switch C i The lower plate of the capacitor is at 0, that is, the ground potential, so that the upper plate of the entire capacitor array appears to represent C i Voltage change of weight coefficient -V i , use Z-ADC to convert -Vi Quantize into digital code; repeat the above process for K times, and store the digital code obtained in these K cycles into a K×(i-1) size matrix DOUT in the calibration control circuit i,set0 , K is a natural number greater than 1; then C is obtained by matrix multiplication i The weight coefficient calibration matrix D i,set0 =DOUT i,set0 ×W,W=[w i-1 ,w i-2 ,…,w1] T , that is, C i The weight coefficient when the lower plate is set to 0 for the Kth time.

[0016] Furthermore, the CDAC self-calibration method reuses the noise shaping filter circuit in the noise shaping successive approximation analog-to-digital converter to suppress quantization noise in the calibration mode.

[0017] Furthermore, the upper plate of the calibration CDAC is connected to the input of the comparator through a noise shaping filter circuit. The comparison result output by the comparator controls the potential connection of the lower plate of the calibration CDAC through the SAR logic circuit. At the same time, the SAR logic circuit inputs the conversion result into the digital filter weight calculation circuit, calculates the weight coefficient of the capacitor to be calibrated and incorporates the capacitor into the calibration CDAC, and then calibrates in sequence towards the higher bits.

[0018] Furthermore, the sum of the weight coefficients for calibrating CDAC is greater than the weight coefficient of the capacitance to be calibrated.

[0019] Furthermore, the CDAC self-calibration method reuses a noise shaping filter circuit, a comparator, and a SAR logic circuit to form a noise shaping successive approximation analog-to-digital converter (Z-ADC) for calibration without adding any additional circuits.

[0020] The CDAC self-calibration method of the present invention reuses the capacitors and redundant capacitors in the lower section of the capacitor array, a noise shaping filter circuit, a comparator, and a SAR logic circuit as a Z-ADC with ideal weight coefficients to quantize the voltage change generated by the capacitor to be calibrated. To improve the accuracy of the calibration, the present invention performs multiple resets and quantizations on the same capacitor to be calibrated, which is equivalent to oversampling. Combined with noise shaping technology, this greatly suppresses the quantization noise within the bandwidth and ensures the accuracy of the calibration. After completing the capacitance calibration of the current position, the present invention incorporates it into the Z-ADC as the highest position, and calibrates the higher positions in sequence until the highest position.

[0021] After calibration, the present invention can obtain the true weight of the capacitor array in a noise-shaping successive approximation ADC, thereby improving linearity and facilitating high-precision design. Compared with traditional self-calibration techniques based on SAR ADCs, the present invention utilizes oversampling and noise-shaping techniques through a reused Z-ADC to more effectively suppress quantization noise within the bandwidth in calibration mode, thereby improving calibration accuracy and being more suitable for situations where the CDAC has a small number of bits. In calibration mode, the capacitor array, noise-shaping filter circuit, comparator, and SAR logic circuit can all be reused, eliminating the need to add additional circuitry to the ADC. Therefore, the present invention can ensure calibration performance while saving chip area and cost, thereby improving ADC accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a structural block diagram of the noise shaping successive approximation analog converter of the present invention.

[0023] Figure 2 Schematic diagram of the process of the CDAC self-calibration method of the present invention.

[0024] Figure 3 FIG. 4 is a schematic diagram of CDAC self-calibration based on a 10-bit noise-shaping successive approximation analog-to-analog converter according to an embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram of the dynamic performance of the ADC before calibration in an embodiment of the present invention.

[0026] Figure 5 FIG. 1 is a schematic diagram of the dynamic performance of the ADC after calibration in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] The CDAC self-calibration method of the present invention is based on Figure 1The noise-shaping successive approximation analog-to-digital converter (ADC) shown includes a CDAC, a noise-shaping filter circuit, a comparator, a successive approximation logic circuit, a calibration control circuit, and a digital filter weight calculation circuit. The ADC performs calibration in calibration mode and normal ADC conversion in conversion mode. The upper plate of the CDAC is connected to the input of the comparator through the noise-shaping filter circuit, and the lower plate is connected to the successive approximation logic circuit of each bit. The CDAC requires the addition of redundant capacitors, with a total of N bits of bit capacitors and redundant capacitors. In calibration mode, the lower bit capacitors and redundant capacitors are reused for a total of i-1 bits (i-1 < N) and regarded as a CDAC with an ideal weight coefficient, and the sum of the weight coefficients of the ideal CDAC is ensured to be greater than the weight of the capacitor to be calibrated. In calibration mode, the present invention reuses the noise-shaping filter circuit, the comparator, and the successive approximation logic circuit to form a Z-ADC for calibration, without the need for additional additions. The conversion result is input into the digital filter weight calculation circuit to calculate the weight coefficient of the capacitor to be calibrated, and the bit capacitor is incorporated into the ideal noise-shaping successive approximation ADC, and calibrated in sequence towards the higher bits. The specific process of the CDAC self-calibration method of the present invention is as follows:

[0029] S1: Initial calibration CDAC selects C1, C2, ..., C i-1 The i-1 lowest-order capacitors, C i-1 is the redundant capacitor, whose weight coefficient is equal to C i-2 The i-1-bit capacitor, noise shaping filter circuit, comparator and successive approximation logic form an ideal noise shaping successive approximation analog-to-digital converter, denoted as Z-ADC, which is used to calibrate the capacitor C to be calibrated. i ;

[0030] S2.1: Switch C i The lower plate of the CDAC is "1" (i.e. high potential), which makes the upper plate of the entire CDAC appear to represent C i Voltage change of weight coefficient +V i .

[0031] S3.1: Use Z-ADC to convert +V i Quantized into digital code.

[0032] S4.1: Repeat steps S2.1 to S3.1 for a total of K times, and store the digital code obtained in these K cycles into a K×(i-1) matrix DOUT in the calibration digital circuit i,set1 , the weight coefficient matrix corresponding to Z-ADC is defined as W=[w i-1 ,w i-2 ,…,w1] T , perform matrix multiplication to get C i The coefficient calibration matrix D i,set1 =DOUTi,set1 ×W, that is, C i The weight coefficients of the K lower plates are set to "1".

[0033] S2.2: Switch C i The lower plate of the CDAC is at "0" (i.e., ground potential), which makes the upper plate of the entire CDAC appear to represent C i Voltage change of weight coefficient -V i .

[0034] S3.2: Using Z-ADC to convert -V i Quantized into digital code.

[0035] S4.2: Repeat steps S2.2 to S3.2 for a total of K times, and store the digital code obtained in these K cycles into a K×(i-1) matrix DOUT in the calibration digital circuit i,set0 , the weight coefficient matrix corresponding to Z-ADC is defined as W=[w i-1 ,w i-2 ,…,w1] T , perform matrix multiplication to get C i The coefficient calibration matrix D i,set0 =DOUT i,set0 ×W, that is, C i The weight coefficients of the K lower plates are set to "0".

[0036] S5: Execute D i,set1 -D i,set0 , digitally filter the difference of these K weight coefficients and then average them to get C i The true weight w i , thus completing the current capacitor C to be calibrated i Calibration; this method of "setting to 1 first, then to 0 and then taking the difference" eliminates the influence of the comparator's offset voltage on the calibration accuracy.

[0037] S6: Let i = i + 1, and then determine whether i > N: If so, use W as the final weight coefficient matrix, complete the calibration, and exit the calibration mode; if not, set C i Incorporate Z-ADC into its highest bit, and convert w i Incorporate the matrix W to form a new calibration circuit, and return to step S2.1 to start the next bit of calibration.

[0038] Example

[0039] The present invention is applied to an ADC scenario such as Figure 3 As shown, it includes 5 modules: N = 10 bits of CDAC (including 9 bits of binary capacitance and 1 bit of redundant capacitance, divided into 2 sections and using bridge capacitance C bConnection), noise shaping filter circuit, comparator, successive approximation logic circuit, digital filter weight calculation output circuit. In conversion mode, the ADC INPUT Perform normal conversion operation, and the residual voltage V on the upper plate after each quantization is RES , and is handed over to the noise shaping filter circuit for integration, summation and other operations, and then output to the comparator for comparison to obtain the digital code of the bit. The digital code controls the successive approximation logic circuit to switch the lower plate of the capacitor corresponding to CDAC, thereby generating a new V RES , and a new cycle begins; after completing 10 conversions, the 10-bit digital code is calculated through the digital filter weight output circuit and output D[10:1].

[0040] In calibration mode, the ADC no longer samples V INPUT signal, and the execution is as follows Figure 2 The process shown in the figure includes:

[0041] Step 1: Since the weight coefficients of the low-order capacitors have little impact on the overall ADC linearity, they can be considered to have ideal weight coefficients. Therefore, in this embodiment, the initial CDAC calibration uses the four lowest-order capacitors: C1, C2, C3, and C4. C4 is a redundant capacitor with a weight coefficient equal to C3. These four capacitors, a noise-shaping filter circuit, a comparator, and a successive approximation logic circuit form an ideal noise-shaping successive approximation analog-to-digital converter, denoted as Z-ADC, which is used to calibrate the capacitor to be calibrated, C5, where i = 5.

[0042] Step 2.1: Switch C i The lower plate is "1" (ie V REF ), so that the upper plate of CDAC appears to represent C i Voltage change of weight coefficient +V i .

[0043] Step 2.2: Use Z-ADC to convert +V i Quantized into digital code.

[0044] Step 2.3: Repeat steps 2.1 to 2.2 for a total of K = 512 times, and store the digital code obtained from these 512 cycles into a K × (i-1) matrix DOUT in the calibration digital circuit. i,set1 , the weight coefficient matrix corresponding to Z-ADC is defined as W=[w i-1 ,w i-2 ,…,w1] T , perform matrix multiplication to get C i The coefficient calibration matrix D i,set1 =DOUT i,set1 ×W, that is, C iThe weight coefficients of the K lower plates are set to "1".

[0045] Step 3.1: Switch C i The lower plate of the CDAC is "0" (i.e. GND), which makes the upper plate of the CDAC appear to represent C i Voltage change of weight coefficient -V i .

[0046] Step 3.2: Use Z-ADC to convert -V i Quantized into digital code.

[0047] Step 3.3: Repeat steps 3.1 to 3.2 for a total of K = 512 times, and store the digital code obtained from these 512 cycles into a K × (i-1) matrix DOUT in the calibration digital circuit. i,set0 , the weight coefficient matrix corresponding to Z-ADC is defined as W=[w i-1 ,w i-2 ,…,w1] T , perform matrix multiplication to get C i The coefficient calibration matrix D i,set0 =DOUT i,set0 ×W, that is, C i The weight coefficients of the K lower plates are set to "0".

[0048] Step 4: Execute D i,set1 -D i,set0 , digitally filter the difference of these K weight coefficients and then average them to get C i The true weight w i , thus completing the current capacitor C to be calibrated i Calibration; this method of "setting to 1 first, then to 0 and then taking the difference" eliminates the influence of the comparator's offset voltage on the calibration accuracy.

[0049] Step 5: Let i = i + 1, and then determine whether i > N: If so, use W as the final weight coefficient matrix, complete the calibration, and exit the calibration mode; if not, set C i Incorporate Z-ADC into its highest bit, and convert w i Incorporate the matrix W to form a new calibration circuit and return to step 2.1 to start the next capacitor C i+1 Calibration of weight coefficients.

[0050] Figure 4 and Figure 5 The comparison results of the dynamic performance of the ADC before and after calibration are given. Under the condition that the relative mismatch error of the capacitor is 0.1%, the signal-to-noise-and-distortion ratio (SNDR) of the ADC before calibration is 64.21dB. Figure 4 As shown in the figure, the total harmonic distortion (THD) is dominant and affects the accuracy. Figure 5 The dynamic performance results after using the CDAC self-calibration technique of the present invention show a SNDR of 85.40dB, achieving 14-bit accuracy, and a THD of -99.20dB. This shows that in calibration mode, the noise shaping technique effectively suppresses in-band quantization noise, meeting the calibration accuracy requirements. Furthermore, the CDAC self-calibration method of the present invention significantly reuses existing ADC circuitry, eliminating the need for additional circuitry. This reduces area and circuit overhead while maintaining performance.

[0051] The above description of the embodiments is intended to facilitate understanding and application of the present invention by those skilled in the art. It is apparent that those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without requiring creative effort. Therefore, the present invention is not limited to the above embodiments. Any improvements or modifications made by those skilled in the art based on the disclosure of the present invention should fall within the scope of protection of the present invention.

Claims

1. A CDAC self-calibration method based on a noise shaping successive approximation analog-to-digital converter (A / D converter), comprising the following steps: (1) Initially, the lowest i-1 capacitors C1, C2, ..., C i-1 Considered as a CDAC with ideal weight coefficients, it is denoted as calibration CDAC, where C i-1 is a redundant capacitor, and the rest are bit capacitors, i-1<N, N is the number of bits of the noise shaping successive approximation analog-to-digital converter; (2) The calibration CDAC, noise shaping filter circuit, comparator and SAR logic circuit are combined to form an ideal noise shaping successive approximation analog-to-digital converter, denoted as Z-ADC, which is used to calibrate the capacitor C in the capacitor array. i ; (3) Switch C i The lower plate of the capacitor is at high potential, and the Z-ADC is used to calibrate it to obtain C i The weight coefficient calibration matrix D i,set1 ; (4) Switch C i The lower plate of the CMOS is at ground potential, and the Z-ADC is used to calibrate it to obtain C i The weight coefficient calibration matrix D i,set0 ; (5) D i,set1 -D i,set0 The result is digitally filtered and averaged to obtain C i The true weight coefficient w i , thus completing the capacitor C i calibration; (6) Let i = i + 1, and determine whether i > N: If so, the weight coefficient matrix W corresponding to Z-ADC is used as the final weight coefficient matrix, the calibration is completed, and the calibration mode is exited; if not, C i Incorporate into the calibration CDAC, w i Incorporate the weight coefficient matrix W and return to step (3) to start the next calibration.

2. The CDAC self-calibration method according to claim 1, wherein: The noise-shaping successive approximation analog-to-digital converter includes a capacitor array, a noise-shaping filter circuit, a comparator, a SAR logic circuit, a calibration control circuit, and a digital filter weight calculation circuit. The analog-to-digital converter has two operating modes, namely a calibration mode and a conversion mode. In the calibration mode, the ADC performs calibration work, and in the conversion mode, the ADC performs normal analog-to-digital conversion work.

3. The CDAC self-calibration method according to claim 2, wherein: The specific implementation of step (3) is as follows: first switch C i The lower plate of the capacitor is 1, that is, high potential, so that the upper plate of the entire capacitor array appears to represent C i Voltage change of weight coefficient +V i , use Z-ADC to convert +V i Quantize into digital code; repeat the above process for K times, and store the digital code obtained in these K cycles into a K×(i-1) size matrix DOUT in the calibration control circuit i,set1 , K is a natural number greater than 1; Then we get C by matrix multiplication i The weight coefficient calibration matrix D i,set1 =DOUT i,set1 ×W,W=[w i-1 ,w i-2 ,…,w1] T , that is, C i The weight coefficient when the K-th lower plate is set to 1.

4. The CDAC self-calibration method according to claim 2, wherein: The specific implementation of step (4) is as follows: first switch C i The lower plate of the capacitor is at 0, that is, the ground potential, so that the upper plate of the entire capacitor array appears to represent C i Voltage change of weight coefficient -V i , use Z-ADC to convert -V i Quantize into digital code; repeat the above process for K times, and store the digital code obtained in these K cycles into a K×(i-1) size matrix DOUT in the calibration control circuit i,set0 , K is a natural number greater than 1; Then we get C by matrix multiplication i The weight coefficient calibration matrix D i,set0 =DOUT i,set0 ×W,W=[w i-1 ,w i-2 ,…,w1] T , that is, C i The weight coefficient when the lower plate is set to 0 for the Kth time.

5. The CDAC self-calibration method according to claim 2, wherein: The CDAC self-calibration method reuses the noise shaping filter circuit in the noise shaping successive approximation analog-to-digital converter to suppress the quantization noise in the calibration mode.

6. The CDAC self-calibration method according to claim 2, wherein: The upper plate of the calibration CDAC is connected to the input of the comparator through a noise shaping filter circuit. The comparison result output by the comparator controls the potential connection of the lower plate of the calibration CDAC through the SAR logic circuit. At the same time, the SAR logic circuit inputs the conversion result into the digital filter weight calculation circuit, calculates the weight coefficient of the capacitor to be calibrated, and incorporates the capacitor into the calibration CDAC, and then calibrates in sequence towards the higher bits.

7. The CDAC self-calibration method according to claim 6, wherein: The sum of the weight coefficients for calibrating CDAC is greater than the weight coefficient of the capacitance to be calibrated.

8. The CDAC self-calibration method according to claim 2, wherein: The CDAC self-calibration method reuses a noise shaping filter circuit, a comparator, and a SAR logic circuit to form a noise shaping successive approximation analog-to-digital converter (Z-ADC) for calibration without adding any additional circuits.

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