Interface circuit for multiphase data conversion, conversion method and integrated circuit

Abstract

The invention discloses a multi-phase data conversion interface circuit, a conversion method and an integrated circuit, and the interface circuit comprises a first conversion circuit which is connected between a first port and a register circuit, and is configured to convert first data into second data, the first data has a first phase number and a first indication signal, the second data has a second phase number and a second indication signal, and the first phase number is greater than the second phase number; the first data volume is equal to the second data volume; the register circuit is coupled with the second conversion circuit, transmits second data based on preset register configuration and converts the second indication signal into a third indication signal, and the preset register configuration is determined based on the write clock signal of the first conversion circuit and the read clock signal of the second conversion circuit; the second conversion circuit is configured to convert the second data into third data and output the third data through the second port, the third data has a third phase number and a fourth indication signal, and the third data volume of the third data is equal to the second data volume. The method and the device have the technical effect of improving the flexibility of cross-clock conversion of data transmission.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of circuit technologies, and in particular, to an interface circuit for multiphase data conversion, a conversion method, and an integrated circuit. Background Art

[0002] With the rapid development of wireless communication technologies, the continuous popularization of technologies such as fifth generation (5G) communication technology, millimeter-wave communication, and carrier aggregation has greatly increased the demand for signal bandwidth and data rate, thereby promoting the rapid evolution of the sampling rate and data bandwidth of high-speed analog-to-digital converter (ADC) and digital-to-analog converter (DAC) chips. Therefore, the problem of data conversion and transmission between different sampling rates deserves attention. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide an interface circuit for multiphase data conversion, a conversion method, and an integrated circuit, in order to improve the flexibility of data transmission across clock conversions. In a first aspect, an interface circuit for multiphase data conversion is provided, including: a first conversion circuit, a register circuit, and a second conversion circuit; the first conversion circuit is connected between a first port and the register circuit and is configured to convert a first data into a second data, where the first data has a first number of phases and a first indication signal, and the second data has a second number of phases and a second indication signal, where the first data volume of the first data is determined based on the first number of phases, the first indication signal, and the write clock signal of the first conversion circuit, the second data volume of the second data is determined based on the second number of phases, the second indication signal, and the write clock signal, and the first data volume is equal to the second data volume; the register circuit is coupled to the second conversion circuit and is configured to transmit the second data based on a preset register configuration, and convert the second indication signal into a third indication signal, where the preset register configuration is determined based on the write clock signal of the first conversion circuit and the read clock signal of the second conversion circuit; the second conversion circuit is coupled to a second port and is configured to convert the second data into a third data and output the third data through the second port, where the third data has a third number of phases and a fourth indication signal, and where the third data volume of the third data is equal to the second data volume. Wherein, the first indication signal is determined based on the data valid indication of the pre-stage circuit of the interface circuit, the second indication signal is determined based on the first number of phases, the third number of phases, and the first indication signal; the third indication signal is determined based on the preset register configuration; the fourth indication signal is determined based on the third indication signal, the second number of phases, and the third number of phases.

[0004] During the above data conversion process, there is no need to adjust the clock signal frequencies of the data input end and the data output end. According to the number of phases required when outputting data, the number of phases and the indication signal are adjusted through the first conversion circuit and the second conversion circuit, and the preset configuration parameters are combined with the register circuit for data transmission, reducing the requirements for the user clock, ensuring that the total amount of data remains unchanged, ensuring the integrity of the data, and improving the convenience and flexibility of data transmission at the user interface.

[0005] Optionally, the data type of the first data includes one or all of in-phase data or quadrature data. The first conversion circuit includes: a first conversion module and an interleaving module; the first conversion module, connected between the first port and the interleaving module, is configured to convert the first data into the second data when the first data includes multiple data types; the interleaving module, coupled to the register circuit, is configured to adjust the in-phase data and the quadrature data into the first data format.

[0006] Optionally, the first conversion circuit further includes: a second conversion module and a first selection module; the second conversion module, connected between the first port and the first selection module, is configured to convert the first data into the second data when the first data is in-phase data; the first selection module, connected between the interleaving module and the register circuit, is configured to select one or more of the first conversion module, the second conversion module, or the interleaving module based on the data type selection signal, where the data type selection signal is determined based on the data type of the first data.

[0007] Optionally, the second conversion circuit includes: a third conversion module, a deinterleaving module, and a second selection module; the third conversion module, connected between the register circuit and the second selection module, is configured to convert the second data into the third data; the deinterleaving module, connected between the third conversion module and the second selection module, is configured to adjust the first data format into the second data format; the second selection module, coupled to the second port, is configured to select the deinterleaving module based on the data type selection signal.

[0008] Optionally, the signal frequencies of the read clock signal and the write clock signal are the same or different.

[0009] Optionally, the signal values of the first indication signal, the second indication signal, the third indication signal, and the fourth indication signal are less than or equal to 1.

[0010] Optionally, the preset register configuration includes the number of valid signals and the number of read clock signal cycles, and the third indication signal is determined based on the ratio of the number of valid signals to the number of read clock signal cycles.

[0011] Second aspect, a polyphase data conversion method is provided for the interface circuit of polyphase data conversion provided by the first aspect. The polyphase data conversion method includes: obtaining first data, where the first data includes a first number of phases and a first indication signal, and the first indication signal is determined based on the application scenario of the pre-stage circuit of the interface circuit; converting the first data into second data, where the second data includes a second number of phases and a second indication signal; transmitting the second data based on a preset register configuration, and converting the second indication signal into a third indication signal based on a write clock signal and a read clock signal; converting the second data into third data, where the third data includes a third number of phases and a fourth indication signal; outputting the third data; wherein, the first data volume of the first data, the second data volume of the second data, and the third data volume of the third data are equal.

[0012] Optionally, the first number further includes: obtaining a data type selection signal of the first data; gating a first selection module or a second selection module of the interface circuit for polyphase data conversion based on the data type selection signal.

[0013] Third aspect, an integrated circuit is provided, including: the interface circuit for polyphase data conversion of the first aspect. Description of the Drawings

[0014] The following briefly introduces the drawings used in the description of the embodiments of the present disclosure: Figure 1 Shows a schematic connection structure diagram of an ADC / DAC chip and a digital processing chip provided in some embodiments of the present application; Figure 2 Shows a schematic integrated structure diagram of an ADC / DAC chip and an SoC chip provided in some embodiments of the present application; Figure 3 Shows a schematic diagram of 6-phase in-phase component data provided in some embodiments of the present application; Figure 4 Shows a schematic circuit structure diagram of an interface circuit for polyphase data conversion provided in some embodiments of the present application; Figure 5 Shows a schematic circuit structure diagram of another interface circuit for polyphase data conversion provided in some embodiments of the present application; Figure 6 Shows a schematic data format diagram of I / Q data after conversion by the first conversion module provided in some embodiments of the present application; Figure 7 Shows a schematic data format diagram of I / Q data after interleaving by the interleaving module provided in some embodiments of the present application; Figure 8 Shows a schematic data format diagram of I / Q data after conversion by the third conversion module provided in some embodiments of the present application; Figure 9The figure shows a schematic diagram of the data format of the I / Q data after deinterleaving by the deinterleaving module provided in some embodiments of the present application; Figure 10 The figure shows a schematic flowchart of a control method for polyphase conversion provided in some embodiments of the present application. Detailed implementation manners

[0015] To more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will describe the example embodiments of the present disclosure with reference to the accompanying drawings. The accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings, and other embodiments can be obtained. Adjustments and improvements made without departing from the concept of the present disclosure fall within the protection scope of the present disclosure.

[0016] For the sake of simplicity of the drawings, each drawing only schematically shows the parts related to the embodiments, and they do not represent the actual structure of the product. In addition, for the sake of simplicity and easy understanding of the drawings, in some drawings, parts with the same structure or function are only schematically shown, and there may actually be more or fewer parts with the same structure or function.

[0017] In the present disclosure, unless otherwise clearly specified and limited, ordinal numbers, such as "first", "second", etc., are only used to distinguish and describe related objects, and cannot be understood as indicating or implying the relative importance or order between related objects; in addition, they do not represent the quantity of related objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between related objects, which means the "or" relationship between related objects. "And / or" is used to describe the relationship between related objects, which includes any combination relationship between related objects. For example, "a and / or b" includes: "a alone", "b alone", or "a and b". "One or more" or "at least one" among multiple objects refers to any object or any combination of multiple objects. For example, "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "a1 alone", "a2 alone", "a3 alone", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0018] With the rapid development of wireless communication technologies, technologies such as fifth-generation communication technology, millimeter-wave communication, and carrier aggregation continue to spread, the demand for signal bandwidth and data rate has increased significantly, which has promoted the rapid evolution of the sampling rate and data bandwidth of high-speed analog-to-digital converters and digital-to-analog converter chips. Figure 1 The figure shows a schematic connection structure diagram of an ADC / DAC chip and a digital processing chip provided in some embodiments of the present application. Please refer to Figure 1, ANA is the analog part of the ADC / DAC chip, and DIG LOGIC is the digital part of the ADC / DAC chip; the AXIS interface is a high-speed data stream interface; JESD is a transmission protocol; SDS TX / RX is a serial-to-parallel / parallel-to-serial transmit and receive module; USER LOGIC is the digital signal processing logic of the user in the SoC chip. Among them, the DIG LOGIC digital part in the ADC / DAC chip mainly implements important functions such as Digital DownConverter (DDC) and Digital Up Converter (DUC) in communication systems for signal sampling rate conversion and frequency conversion, so as to reduce the user data rate, generate I / Q quadrature signals, and improve the subsequent processing efficiency. However, taking the analog-to-digital conversion process with a sampling rate of 6 GHz and 16 bits as an example, the data volume of a single channel reaches 96 Gb. If a 12 Gbps transmit and receive module is used, at least 8 channels (lanes) are required to complete the transmission, and complex debugging work of the JESD protocol or SDS needs to be completed. At the same time, the AXIS interface needs to perform operations such as data bit width and clock conversion with the JESD protocol and SDS, and the transmit and receive modules also need to be finally converted into the data received or sent by the user through a hardware path, and the overall process is relatively complex.

[0019] On the other hand, with the development of advanced processes such as Chip on Wafer on Substrate (CoWoS) technology, it is easier to achieve larger chip scales and more complex heterogeneous integration. Such designs can greatly simplify the interface and connection design. Figure 2 shows a schematic diagram of the integrated structure of an ADC / DAC chip and an SoC chip provided in some embodiments of the present application. When adopting Figure 2 the shown integration scheme, the digital interface of the ADC / DAC chip will be directly connected to the digital interface of the SoC chip, saving the conversion relationship between the protocol and SDS. Therefore, the ADC / DAC chip only needs to implement the AXIS interface conversion with the SoC. In order to reduce subsequent logic processing and facilitate user use, the interface conversion logic is generally implemented inside the ADC / DAC chip.

[0020] However, the digital logic inside the high-speed ADC / DAC chip is limited by the clock of the digital circuit and is generally achieved by increasing the data parallelism and reducing the clock frequency. For example, for an analog-to-digital conversion of 3 GSPS, if the chip processes each sampling point individually, a digital clock of 3 GHz is required, and the existing process level cannot meet this requirement; if multiple sampling points are arranged in sequence as a data block, for example, when including 6 sampling points, the requirement for the digital clock can be reduced to 500 MHz, and this clock frequency can be achieved through hardware.Figure 3 A schematic diagram of six in-phase component data provided in some embodiments of the present application is shown. The I0 phase to the I5 phase are arranged in sequence from right to left. Among them, each sampling point can be called one-phase (samples) data. Therefore, "multiple phases" in the present application can refer to data formed by arranging multiple sampling data together. In the interface design of the prior art, for example, a scheme with an optional number of phases is adopted to determine the clock frequency of the data. Among them, the data valid indication signal is always high and cannot be configured by the user. For example, one with an optional parallelism of 4 to 12. At this time, the clock that the user needs to provide is one of CLK = FS / N (4 to 12). When the user changes the sampling rate, it may be necessary to change the logical clock frequency of the user. When the user changes the sampling rate, if the number of phases remains unchanged, the received logical clock frequency needs to be changed; if the number of phases is reconfigured, a suitable logical clock needs to be set, and the received data bit width of the user will change accordingly, and the receiving logic needs to be modified. Adopting an independent I / Q interface and a configurable number of phases design requires a large number of interfaces to be reserved, resulting in low interface utilization. The number of configurable phase selections is relatively small. Coupled with the unused data valid signal (always high), the user needs to provide a matching clock frequency according to the sampling rate and the number of phases, resulting in poor flexibility of the data interface. The present application converts the high-speed data interface inside the ADC / DAC into a high-speed interface for the user, mainly including the number of phases and the clock domain. This interface circuit can efficiently complete the conversion of in-phase component (I) or in-phase / quadrature component (I / Q) signals, and combined with different data valid indications that can be generated by the register configuration parameters, reduces the requirements for the user's clock. Only through a set of configurations can the change of the sampling rate and the cross-clock conversion of the high-speed interface be completed while maximizing the retention of the user's original logic design. Improve the convenience and flexibility of data transmission.

[0021] Figure 4The figure shows a schematic circuit diagram of an interface circuit for multi-phase data conversion provided in some embodiments of the present application. The interface circuit 400 for multi-phase data conversion includes: a first conversion circuit 410, a register circuit 420, and a second conversion circuit 430; the first conversion circuit 410 is connected between the first port IN and the register circuit 420 and is configured to convert the first data into the second data, where the first data has a first number of phases and a first indication signal, and the second data has a second number of phases and a second indication signal. Among them, the first data volume of the first data is determined based on the first number of phases, the first indication signal, and the write clock signal of the first conversion circuit, and the second data volume of the second data is determined based on the second number of phases, the second indication signal, and the write clock signal. The first data volume is equal to the second data volume; the register circuit 420 is coupled to the second conversion circuit 430 and is configured to transmit the second data based on a preset register configuration and convert the second indication signal into a third indication signal. The preset register configuration is determined based on the write clock signal of the first conversion circuit and the read clock signal of the second conversion circuit; the second conversion circuit 430 is coupled to the second port OUT and is configured to convert the second data into the third data and output the third data through the second port, where the third data has a third number of phases and a fourth indication signal, and the third data volume of the third data is equal to the second data volume. Among them, the first indication signal is determined based on the data valid indication of the pre-stage circuit of the interface circuit, the second indication signal is determined based on the first number of phases, the third number of phases, and the first indication signal; the third indication signal is determined based on the preset register configuration; the fourth indication signal is determined based on the third indication signal, the second number of phases, and the third number of phases.

[0022] In the above interface circuit for multi-phase data conversion, the first data may be data obtained by multiple sampling points and arranged in sequence. For example, if the data is determined by four sampling points, the first data may be 4-phase. The specific number of sampling points may be determined based on the hardware design of the interface circuit to reduce the requirements for the digital clock. For example, if 8 sampling points are designed, the first data may have a phase number less than or equal to 8, which is not specifically limited here. The first conversion circuit 410 may adjust the first phase number of the first data to match the parameters such as the phase number and clock of the data (such as the third data) to be output. For example, when the phase number of the first data is 4 phases and the third data to be output is 6 phases, the first phase number of the first data may be adjusted to 8 phases by the first conversion circuit 410. In this process, the first indication signal is converted into the second indication signal. For example, when the valid indication of the first indication signal is 1, when the conversion from 4 phases to 8 phases is performed, the valid indication of the second indication signal generated by the conversion is 1 / 2. When the write clock signal remains unchanged, the change of the indication signal ensures that the total amount of data remains unchanged, that is, the second data amount is still equal to the first data amount. The indication signal is used to indicate the data validity indication. The indication signal is used to indicate whether the current data is valid, for example, the data validity indication is valid at a high level. When the indication signal is always high, it indicates that the data is continuously valid, that is, the data is valid at all clock trigger edges; for example, when the indication signal is 1 / 2, it indicates that one clock trigger edge is valid (high level) every 2 clock cycles, and the corresponding data is also valid at this time. Other typical values ​​such as 1 / 3, 1 / 4, and 1 / 8 may exist. The first indication signal is determined by the previous stage circuit of the interface circuit 400 in the user's usage scenario. For example, if the customer adopts the extraction by 2 processing method after ADC sampling, the data validity indication is generally 1 / 2, when it is extracted by 8, it is 1 / 8, and when it is directly output without extraction, it is always high. In the process of data transmission, there may be a situation where the write clock frequency is different from the read clock frequency. In order to ensure the complete transmission of the input data, the register circuit 420 can match the clock frequencies of the write clock and the read clock through the preset register configuration to temporarily store the second data. For example, the selected 8-phase second data can be written into the register circuit 420 under the action of the write clock signal, and then the 8-phase data can be read out under the action of the read clock signal according to the preset register configuration. Among them, the preset register configuration may include an effective number and a cycle number, that is, how many times to read in how many read clock cycles. For example, when the effective number is configured to be x and the cycle number is y, x times of reading are performed in y read clock cycles. At this time, the effective indication of the second indication signal changes to the effective number / cycle number, that is, x / y, to form a third indication signal and continue to transmit to the next stage. For example, in order to achieve complete data transmission, the second data of 8 phases, the signal frequency of the write clock signal is 300MHz, and the effective value of the second indication signal is 1 / 2, the second data volume can be expressed as 300×8×1 / 2=1200.To ensure that the data transmission volume remains unchanged, when the signal frequency of the read clock signal is 200 MHz, the second indication signal is converted into the third indication signal through preset register configuration, and the effective value is adjusted to 3 / 4, so that the data transmission volume of 300×8×1 / 2 = 200×8×3 / 4 is matched, realizing the complete transmission of the second data and entering the second conversion circuit 430. In the second conversion circuit 430, since 6-phase third data needs to be output and the total amount of data needs to be kept unchanged, when the second conversion circuit 430 is used for conversion, the clock signal remains unchanged in this circuit, and the number of phases is adjusted from 8 phases to 6 phases. Correspondingly, the third indication signal needs to be adjusted to the fourth indication signal. For example, its effective value is set to always high (i.e., 1), satisfying the data transmission volume of 200×8×3 / 4 = 200×6×1, so as to realize the conversion from 4-phase input to 6-phase output and ensure that the total amount of data remains unchanged during the conversion process. The fourth indication signal can be determined according to the third indication signal, the number of phases during data output, and the intermediate number of phases during the conversion process, but the effective value needs to be less than or equal to 1. For example, when the third indication signal is 3 / 4, the number of phases during output is 6, and the intermediate number of phases is 8, the effective value of the fourth indication signal is (3 / 4)×(8 / 6)=1. The register circuit of the present application can be a register circuit based on the first in first out (FIFO) structure, which can support independent read and write clocks, automatically generate a read enable signal by configuring the valid number and the number of cycles, and output the read enable signal after synchronizing it with the read data (the synchronized read enable signal is the output third indication signal), so that the register circuit supports generating a read enable signal according to any valid number and number of cycles. During the above data conversion process, there is no need to adjust the clock signal frequency of the data input end and the data output end. According to the number of phases required during data output, the number of phases and the indication signal are adjusted through the first conversion circuit and the second conversion circuit, and the data is transmitted in combination with the preset configuration parameters of the register circuit, reducing the requirements for the user clock, ensuring that the total amount of data remains unchanged, ensuring the integrity of the data, and improving the convenience and flexibility of data transmission at the user interface. The above embodiments can reuse the data interface. For example, when only transmitting I-channel signals, the interface can be configured to output all phases as I-channel; when transmitting I / Q two-channel signals at the same time, it can be configured that I / Q each occupies half of the transmission bit width, so that the interface utilization rate reaches 100%. In some embodiments, the above data transmission method is not limited to inputting the first data from the first port and outputting the third data from the second port, but can also input the first data from the second port and output the third data from the first port to realize bidirectional data transmission, which is not specifically limited herein.

[0023] In some embodiments of the present application, the data type of the first data includes one or all of in-phase data and quadrature data. Figure 5The figure shows a schematic circuit diagram of another interface circuit for multiphase data conversion provided in some embodiments of the present application. The interface circuit 500 for multiphase data conversion includes a first conversion circuit 510, a register circuit 520, and a second conversion circuit 530. Among them, the first conversion circuit 510 includes: a first conversion module and an interleaving module; the first conversion module is connected between the first port and the interleaving module and is coupled to the first indication signal, and is configured to convert the first data into the second data when the first data includes multiple data types; the interleaving module is coupled to the register circuit and is configured to adjust the in-phase data and the quadrature data into the first data format.

[0024] In the above embodiments, an interleaving module can be provided in the first conversion circuit 510 of the interface circuit 500 for multiphase data conversion to interleave the input data, thereby ensuring data alignment. The interleaving module can make the in-phase data and the quadrature data I / Q appear in pairs within each clock cycle, ensuring their synchronization throughout the signal processing chain. If not interleaved, the in-phase data I and the quadrature data Q may be processed separately in different clock cycles, resulting in phase misalignment. Interleaving can improve the parallelism of the data stream, making the data evenly distributed among multiple phases, which is helpful for subsequent parallel processing. The interleaved I / Q data can be stored and accessed in a fixed pattern, reducing the complexity of out-of-order access.

[0025] In some embodiments, the first conversion circuit further includes: a second conversion module and a first selection module; the second conversion module is connected between the first port and the first selection module and is coupled to the first indication signal, and is configured to convert the first data into the second data when the first data is in-phase data; the first selection module is connected between the interleaving module and the register circuit and is configured to select one or more of the first conversion module, the second conversion module, or the interleaving module based on the data type selection signal, where the data type selection signal is determined based on the data type of the first data.

[0026] The data type selection signal can instruct the first selection module to make a selection output according to different types of input data, so that the interface circuit 500 for multiphase data conversion can either process the in-phase data I alone or process the in-phase data I and the quadrature data Q simultaneously. For example, when the data type selection signal indicates that the input signal is the in-phase data I, the first selection module can select the second conversion module to output the converted in-phase second data. Or when the data type selection signal indicates that both the in-phase data I and the quadrature data Q exist in the output signal, the first selection module can select the first conversion module and the interleaving module to output the converted second data with in-phase and quadrature components, so as to improve the universality of data transmission applications.

[0027] In some embodiments, the second conversion circuit includes: a third conversion module, a deinterleaving module and a second selection module; the third conversion module is connected between the register circuit and the second selection module, and is configured to convert the second data into third data; the deinterleaving module is connected between the third conversion module and the second selection module, and is configured to adjust the first data format to the second data format; the second selection module is coupled to the second port, and is configured to select the deinterleaving module based on the data type selection signal.

[0028] The interface circuit 500 for multi-phase data conversion is provided with an interleaving module and a deinterleaving module, which can cooperate with each other. For example, when the number of phases of the third data output by the conversion is not a multiple of the number of phases of the first data input, there may be multiple arrangement formats on the output side, so that the I / Q two-way signal cannot be correctly deciphered. Taking the input of 4 phases and the output of 6 phases as an example, Figure 6 A schematic diagram of the data format of I / Q data after conversion by the first conversion module provided in some embodiments of the present application is shown, where data I0 to data I3 are arranged from right to left, and data Q0 to data Q3 are arranged from right to left starting from data I3. Figure 7 The data format diagram of the I / Q data after interleaving by the interleaving module provided in some embodiments of the present application is shown. After interleaving, the data In and the data Qn are arranged in an interlaced manner, and after the data is adjusted by the register circuit, the above data format is still maintained, so that the in-phase data and the orthogonal data I / Q appear in pairs in each clock cycle, ensuring their synchronization in the entire signal processing chain. Figure 8 A schematic diagram of the data format of I / Q data after conversion by the third conversion module provided in some embodiments of the present application is shown. After conversion, 8-phase data is converted into 6-phase data, the data phase conversion is completed, and the interleaving state continues to be maintained. Figure 9 The data format diagram of the I / Q data after deinterleaving by the deinterleaving module provided in some embodiments of the present application is shown. The deinterleaving module restores the order of data I0 to data I2 from right to left, and data Q0 to data Q2 from data I2 from right to left, to complete the deinterleaving. Among them, the reason for the interleaving of input and output is that during the conversion process of the multi-phase conversion switching circuit, when the number of phases of the output data is not a multiple of the number of phases of the input data, multiple arrangement formats may be generated on the output side, making it impossible to correctly decode the I / Q two-way signal.

[0029] In some embodiments, the signal frequencies of the read clock signal and the write clock signal are the same or different. According to the clock requirements of the subsequent circuit of the interface circuit, there may be differences between the read clock signal and the write clock signal. For example, the operating clock of the ASIC circuit in the front stage of the interface circuit is faster (such as 300 MHz), while when the ASIC circuit is converted to the SoC / FPGA circuit, the operating clock is slower (such as 200 MHz). The solution of the present application can avoid the situation where the clock signal frequency of the subsequent circuit needs to be adjusted during the phase number conversion process. Further, when the user changes the sampling rate, if the phase number remains unchanged, the logical clock frequency received needs to be changed; and if the phase number is reconfigured, a suitable clock is required, and the received data bit width of the user will change, and the receiving logic still needs to be modified.

[0030] Figure 10 The flowchart of a control method for polyphase conversion provided in some embodiments of the present application is shown. This method is used to control the interface circuit for polyphase data conversion provided in the above embodiments. The control method includes: S1010: Obtain first data, where the first data includes a first phase number and a first indication signal, and the first indication signal is determined based on the application scenario of the front-stage circuit of the interface circuit; S1020: Convert the first data into second data, where the second data includes a second phase number and a second indication signal; S1030: Transmit the second data based on a preset register configuration, and convert the second indication signal into a third indication signal based on the write clock signal and the read clock signal; S1040: Convert the second data into third data, where the third data includes a third phase number and a fourth indication signal; S1050: Output the third data; where the first data volume of the first data, the second data volume of the second data, and the third data volume of the third data are equal.

[0031] Before data conversion is performed through the interface circuit for polyphase data conversion, the data volume Data of the first data 1 can be represented by Formula 1:

[0032] where WR_CLK represents the signal frequency of the write clock signal, NPH 0 represents the input phase number, and VLD 0 represents the valid value of the first indication signal of the input data. After being adjusted by the first conversion circuit, the data volume Data of the second data 2 can be represented by Formula 2:

[0033] where NPH 1Indicates the number of phases after adjustment by the first conversion circuit, VLD 1 Indicates the effective value of the second indication signal. When writing to the register circuit, the data volume Data of the second data 2 Can also be expressed by Formula 3:

[0034] Wherein, RD_CLK represents the signal frequency of the read clock signal, VLD 2 Indicates the effective value of the third indication signal. And after the number of phases is converted by the second conversion circuit, the third data Data 3 Can be expressed by Formula 4:

[0035] Wherein, NPH 2 Indicates the number of phases after adjustment by the second conversion circuit, VLD 3 Indicates the effective value of the fourth indication signal. The data volumes of the above Formulas 1 to 4 are equal, so there is Formula 5:

[0036] Wherein, in the first data Data 0 The data volume and the number of phases NPH of the output third data 2 Given, the signal frequency RD_CLK of the read clock signal and the effective value VLD of the fourth indication signal 3 Can be arbitrarily matched to achieve the conversion and transmission of polyphase data. Through the above conversion method, without adjusting the frequency of the user clock signal, the indication signal is determined according to the input and output phase number changes and the read and write clock signals, and the data is transmitted in combination with the preset configuration parameters of the register circuit, reducing the requirements for the user clock and improving the convenience and flexibility of the user interface data transmission.

[0037] In some embodiments, it further includes: obtaining a data type selection signal of the first data; based on the data type selection signal, selecting the first selection module or the second selection module of the interface circuit for polyphase data conversion.

[0038] According to the data type of the first data, for example, when the first data includes in-phase and quadrature data, the first selection module and the second selection module in the interface circuit for polyphase data conversion are controlled by the data type selection signal to select the corresponding data transmission branch to complete the data transmission.

[0039] Based on the same technical concept, the present application also provides an integrated circuit, including: the interface circuit for polyphase data conversion provided in the above embodiments.

[0040] In the above embodiments, the descriptions of the respective embodiments each have their own focuses. For parts that are not described or recorded in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. An interface circuit for multi-phase data conversion, characterized in that: include: a first conversion circuit, a register circuit, and a second conversion circuit; The first conversion circuit is connected between the first port and the register circuit, and is configured to convert the first data into the second data, wherein the first data has a first phase number and a first indication signal, and the second data has a second phase number and a second indication signal, wherein a first data amount of the first data is determined based on the first phase number, the first indication signal, and a write clock signal of the first conversion circuit, and a second data amount of the second data is determined based on the second phase number, the second indication signal, and the write clock signal, and the first data amount is equal to the second data amount; The register circuit is coupled to the second conversion circuit and is configured to transmit the second data and convert the second indication signal into a third indication signal based on a preset register configuration, wherein the preset register configuration is determined based on a write clock signal of the first conversion circuit and a read clock signal of the second conversion circuit; The second conversion circuit is coupled to the second port and configured to convert the second data into third data and output the third data through the second port, wherein the third data has a third phase number and a fourth indication signal, wherein a third data amount of the third data is equal to the second data amount; Among them, the first indication signal is determined based on the valid indication of the previous-stage circuit data of the interface circuit, the second indication signal is determined based on the first phase number, the third phase number and the first indication signal; the third indication signal is determined based on the preset registration configuration; the fourth indication signal is determined based on the third indication signal, the second phase number and the third phase number.

2. The multi-phase data conversion interface circuit according to claim 1, characterized in that: The data type of the first data includes one or both of in-phase data and orthogonal data, and the first conversion circuit includes: a first conversion module and an interleaving module; The first conversion module is connected between the first port and the interleaving module, and is configured to convert the first data into the second data when the first data includes multiple data types; The interleaving module is coupled to the register circuit and is configured to adjust the in-phase data and the orthogonal data into a first data format.

3. The multi-phase data conversion interface circuit according to claim 2, characterized in that: The first conversion circuit further includes: a second conversion module and a first selection module; The second conversion module is connected between the first port and the first selection module, and is configured to convert the first data into the second data when the first data is in-phase data; The first selection module is connected between the interleaving module and the register circuit, and is configured to select one or more modules of the first conversion module, the second conversion module or the interleaving module based on a data type selection signal, wherein the data type selection signal is determined based on the data type of the first data.

4. The multi-phase data conversion interface circuit according to claim 3, characterized in that: The second conversion circuit includes: a third conversion module, a de-interleaving module and a second selection module; The third conversion module is connected between the register circuit and the second selection module, and is configured to convert the second data into the third data; The deinterleaving module is connected between the third conversion module and the second selection module, and is configured to adjust the first data format to a second data format; The second selection module, coupled to the second port, is configured to select the deinterleaving module based on the data type selection signal.

5. The multi-phase data conversion interface circuit according to any one of claims 1 to 4, characterized in that: The signal frequencies of the read clock signal and the write clock signal are the same or different.

6. The multi-phase data conversion interface circuit according to any one of claims 1 to 4, characterized in that: The signal values ​​of the first indication signal, the second indication signal, the third indication signal and the fourth indication signal are less than or equal to 1.

7. The multi-phase data conversion interface circuit according to any one of claims 1 to 4, characterized in that: The preset registration configuration includes a signal validity number and a read clock signal cycle number, and the third indication signal is determined based on a ratio of the signal validity number to the read clock signal cycle number.

8. A multi-phase data conversion method, characterized in that: An interface circuit for multi-phase data conversion according to any one of claims 1 to 7, wherein the multi-phase data conversion method comprises: Acquire first data, where the first data includes a first phase number and a first indication signal, where the first indication signal is determined based on an application scenario of a previous stage circuit of the interface circuit; converting the first data into second data, wherein the second data includes a second phase number and a second indication signal; transmitting the second data based on a preset register configuration, and converting the second indication signal into a third indication signal based on a write clock signal and a read clock signal; converting the second data into third data, wherein the third data includes a third phase number and a fourth indication signal; outputting the third data; The first data amount of the first data, the second data amount of the second data, and the third data amount of the third data are equal.

9. The multi-phase data conversion method according to claim 8, characterized in that: Also includes: Acquire a data type selection signal of the first data; The first selection module or the second selection module of the multi-phase data conversion interface circuit is selected based on the data type selection signal.

10. An integrated circuit, characterized in that: include: The interface circuit for multi-phase data conversion according to any one of claims 1 to 7.

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