Low latency delta-sigma modulator
By adopting low-latency Δ-Σ modulator topology and related circuits in the control system, the problem of delay of isolation modulators and isolation amplifiers in the prior art is solved, high-speed and low-latency data transmission is achieved, and system performance is improved.
Patent Information
- Application Number
- CN202411642487.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-30
- Filing Date
- 2024-11-18
- Publication Date
- 2025-05-30
AI Technical Summary
In existing control systems, the delays of the isolation modulator and isolation amplifier have an impact on system performance and it is challenging to increase the component clock rate.
Using low-latency Δ-Σ modulator topology and related circuits, high-speed and low-latency data transmission is achieved through a combination of multi-bit analog-to-digital conversion circuit system, interpolation and filter circuit system, and digital Δ-Σ modulator.
Effectively reduces the system's delay, improves the speed of data transmission and available bandwidth, while avoiding the challenge of increasing clock rate.
Smart Images
Figure CN120074528A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure generally relates to a modulator, and more particularly, to a low-latency delta-sigma modulator. Background Art
[0002] Control systems rely on different components and interfaces to relay data and / or control signals between sensors, controllers, and controlled components. In some instances, the sensors, controllers, and controlled components reside in different voltage domains. Example components that can be used in a control system to facilitate the transmission of data and / or control signals include isolation modulators and isolation amplifiers. The latency of the isolation modulators and isolation amplifiers affects the performance of the associated control system, and it is challenging to increase only the clock rate of the associated components due to more demanding setup requirements. Summary of the Invention
[0003] In an instance, a circuit includes: a multi-bit analog-to-digital conversion circuitry; an interpolation circuit; a filter; and a digital delta-sigma modulator. The multi-bit analog-to-digital conversion circuitry has a first terminal and a second terminal. The interpolation circuit has a first terminal and a second terminal. The first terminal of the interpolation circuit is coupled to the second terminal of the multi-bit analog-to-digital conversion circuitry. The filter has a first terminal and a second terminal. The first terminal of the filter is coupled to the second terminal of the interpolation circuit. The digital delta-sigma modulator has a first terminal and a second terminal. The first terminal of the digital delta-sigma modulator is coupled to the second terminal of the filter.
[0004] In another instance, a circuit includes: a multi-bit delta-sigma modulator having a first terminal and a second terminal; an interpolation circuit having a first terminal and a second terminal; a filter having a first terminal and a second terminal; a digital delta-sigma modulator having a first terminal and a second terminal; and an isolation circuitry having a first terminal and a second terminal. The first terminal of the interpolation circuit is coupled to the second terminal of the multi-bit delta-sigma modulator. The first terminal of the filter is coupled to the second terminal of the interpolation circuit. The first terminal of the digital delta-sigma modulator is coupled to the second terminal of the filter. The first terminal of the isolation circuitry is coupled to the second terminal of the digital delta-sigma modulator.
[0005] In yet another instance, a circuit includes: a multi-bit analog-to-digital conversion circuitry; an interpolation circuit coupled to the multi-bit analog-to-digital conversion circuitry; a filter coupled to the interpolation circuit; and a digital delta-sigma modulator coupled to the filter. The multi-bit analog-to-digital conversion circuitry is configured to convert an analog input signal into a multi-bit signal. The interpolation circuit is configured to interpolate the multi-bit signal to generate an interpolated signal. The filter is configured to filter the interpolated signal to generate a filtered signal. The digital delta-sigma modulator is configured to digitize the filtered signal. Brief Description of the Drawings
[0006] Figure 1A A block diagram for showing an example Δ-Σ modulator circuit.
[0007] Figure 1B A block diagram for showing another example Δ-Σ modulator circuit.
[0008] Figure 2 A block diagram for showing an example isolation modulator circuit.
[0009] Figure 3 A block diagram for showing an example isolation amplifier circuit.
[0010] Figure 4 A block diagram for showing another example isolation amplifier circuit.
[0011] Figure 5 A graph for showing the full-scale step response of an example isolation amplifier circuit.
[0012] Figure 6 A block diagram for an example system.
[0013] Figure 7 A flowchart for showing an example Δ-Σ modulator method. Detailed Description
[0014] The same reference numerals or other reference designators are used in the drawings to designate the same or similar features. Such features may be the same or similar in function and / or structure.
[0015] Low-latency Δ-Σ modulator topologies and related circuits are described herein. Figure 1A A block diagram for showing an example Δ-Σ modulator circuit 100A. The Δ-Σ modulator circuit 100A has a first terminal 102 and a second terminal 104. The Δ-Σ modulator circuit 100A includes a multi-bit analog-to-digital conversion circuit system 106, an interpolation and filter circuit system 114, and a digital Δ-Σ modulator 122. The multi-bit analog-to-digital conversion circuit system 106 has a first terminal 108, a second terminal 110, and a third terminal 112. In some examples, the multi-bit analog-to-digital conversion circuit system 106 includes an Nth-order m-bit Δ-Σ modulator 113. The interpolation and filter circuit system 114 has a first terminal 116, a second terminal 118, and a third terminal 120. The digital Δ-Σ modulator 122 has a first terminal 124 and a second terminal 126.
[0016] The first terminal 102 of the Δ-Σ modulator circuit 100A is coupled to the first terminal 108 of the multi-bit analog-to-digital conversion circuit system 106. The second terminal 110 of the multi-bit analog-to-digital conversion circuit system 106 is coupled to a clock generator (not shown) and receives a clock signal CLK. The third terminal 112 of the multi-bit analog-to-digital conversion circuit system 106 is coupled to the first terminal 116 of the interpolation and filter circuit system 114. The second terminal 118 of the interpolation and filter circuit system 114 is coupled to a clock generator or a multiplier (not shown) and receives an interpolation clock signal (e.g., CLK*L), where L is an integer greater than 1. The third terminal 120 of the interpolation and filter circuit system 114 is coupled to the first terminal 124 of the digital Δ-Σ modulator 122. The second terminal 126 of the digital Δ-Σ modulator 122 is coupled to the second terminal 104 of the Δ-Σ modulator circuit 100A.
[0017] The multi-bit analog-to-digital conversion circuit system 106 operates to: receive an analog input signal at the first terminal 108; receive CLK at the second terminal 110; and output a modulated signal in response to the analog input signal CLK and the multi-bit analog-to-digital conversion operation. In some instances, the analog-to-digital conversion operation is performed by an Nth-order m-bit Δ-Σ modulator 113.
[0018] An example first-order Δ-Σ modulator includes a subtraction block, an integrator, a comparator, and a 1-bit digital-to-analog converter (DAC). The first-order Δ-Σ modulator operates based on an input clock (e.g., CLK herein), which determines the sampling interval of the input. The modulation loop begins with integrating the difference between the input sample and the 1-bit DAC. The comparator determines the next modulator output based on the integrator value. Depending on the output state of the comparator, the 1-bit DAC generates a voltage equal to the positive or negative reference voltage of the first-order Δ-Σ modulator. If the modulator output is 1, the reference voltage is subtracted from the input. If the output is 0, the reference voltage is added to the input voltage.
[0019] At each modulator clock pulse, the modulator completes a full cycle and generates a new output. As the modulator clock continues to run, each modulator clock pulse generates another modulator output pulse. The resulting output bit stream becomes a representation of the input voltage proportional to the reference voltage. When the analog input signal approaches the positive range threshold, the bit stream of the modulator approaches a 1s density of 100%. Conversely, when the analog input signal approaches the negative range threshold, the 1s density of the bit stream approaches 0%. When the analog input signal is 0V, the 1s density is 50%.
[0020] A single-bit modulator suffers from undesirable quantization noise. Adding an integrator before the comparator as in the above example provides first-order shaping of the quantization noise. The useful bandwidth obtained with a first-order single-bit modulator is very limited. Increasing the order of the modulator by adding more integrators is one way to increase the available bandwidth. An Nth-order modulator provides Nth-order shaping of the quantization noise. An example m-bit quantizer has 2^m comparators. Using more levels in the quantizer instead of a single comparator directly reduces the quantization noise. Whenever the number of comparators is doubled, the quantization noise drops by 6 dB. Compared to a single-bit modulator clocked at the same frequency, a multi-bit modulator allows a more useful bandwidth. In some examples, the Nth-order m-bit Δ-Σ modulator 113 can be a third-order 5-bit Δ-Σ modulator.
[0021] The interpolation and filter circuitry 114 operates to: receive the modulated signal at a first terminal 116; receive an interpolation clock signal at a second terminal 118; interpolate the modulated signal in response to the interpolation clock signal to obtain an interpolation result; filter the interpolation result using a low-pass filter (LPF) to obtain a filtered result; and provide the filtered result at a third terminal 120. Upsampling the signal by an interpolation factor L creates unwanted images in the spectrum. The LPF removes these images. However, the LPF increases the delay, so there is a trade-off between image rejection and delay in the modulator. The digital Δ-Σ modulator operates to: receive the filtered result at a first terminal 124; digitize the filtered result to provide a digital output; and provide the digital output at a second terminal 126. The digital output is provided to the second terminal 104 of the Δ-Σ modulator circuit 100A. In some examples, the digital output is a stream of 1-bit digital values. Utilizing the Δ-Σ modulator circuit 100A, the combination of the multi-bit analog-to-digital conversion circuitry 106, the interpolation and filter circuitry 114, and the digital Δ-Σ modulator 122 provides a high-speed (low-latency) Δ-Σ modulator, where the speed has been increased by a factor of L without increasing the CLK.
[0022] Figure 1B FIG. shows a block diagram of another example Δ-Σ modulator circuit 100B. The Δ-Σ modulator circuit 100B has Figure 1A the first terminal 102 and the second terminal 104 described in. The Δ-Σ modulator circuit 100B includes a multi-bit analog-to-digital conversion circuitry 128, an interpolation and filter circuitry 114, and a digital Δ-Σ modulator 122. The multi-bit analog-to-digital conversion circuitry 128 has a first terminal 130, a second terminal 132, and a third terminal 134. In some examples, the multi-bit analog-to-digital conversion circuitry 128 includes a Nyquist rate analog-to-digital converter (ADC) 135. The interpolation and filter circuitry 114 has Figure 1AThe first terminal 116, second terminal 118, and third terminal 120 described in Figure 1A The first terminal 124 and second terminal 126 described in
[0023] The first terminal 102 of the Δ-Σ modulator circuit 100B is coupled to the first terminal 130 of the multi-bit analog-to-digital conversion circuit system 128. The second terminal 132 of the multi-bit analog-to-digital conversion circuit system 128 is coupled to a clock generator (not shown) and receives CLK. The third terminal 134 of the multi-bit analog-to-digital conversion circuit system 128 is coupled to the first terminal 116 of the interpolation and filter circuit system 114. The second terminal 118 of the interpolation and filter circuit system 114 is coupled to a clock generator or a multiplier (not shown) and receives an interpolation clock signal (e.g., CLK*L), where L is an integer greater than 1. The third terminal 120 of the interpolation and filter circuit system 114 is coupled to the first terminal 124 of the digital Δ-Σ modulator 122. The second terminal 126 of the digital Δ-Σ modulator 122 is coupled to the second terminal 104 of the Δ-Σ modulator circuit 100B.
[0024] The multi-bit analog-to-digital conversion circuit system 128 operates to: receive an analog input signal at the first terminal 130; receive CLK at the second terminal 132; and output a modulated signal in response to the analog input signal, CLK, and a multi-bit analog-to-digital conversion operation. In some instances, the analog-to-digital conversion operation is performed by the Nyquist rate ADC 135.
[0025] An example Nyquist rate ADC 135 can be a successive approximation (SAR) ADC that includes a sample-and-hold circuit, an analog comparator, a successive approximation register, and an N-bit search digital-to-analog converter (DAC). During the sampling phase, the sample-and-hold circuit charges a capacitor to the analog input signal level within a target resolution (e.g., half of the least significant bit resolution). After the sampling phase, the sample-and-hold circuit provides the sampled voltage to the first terminal (e.g., non-inverting terminal) of the analog comparator. The second terminal of the analog comparator receives the output of the N-bit search DAC. The N-bit search DAC and the analog comparator continuously compare the sampled voltage with the output of the N-bit search DAC output (e.g., most significant to least significant), where the comparison results are stored in the successive approximation register. The Nyquist rate ADC 135 in the above example provides an N-bit output in one CLK cycle. Thus, the internal SAR search uses a clock faster than CLK. In other instances, the Nyquist rate ADC 135 can be any other Nyquist rate ADC architecture that provides N-bit data in one CLK cycle.
[0026] Figure 1B The interpolation and filter circuit system 114 and the digital Δ-Σ modulator 122 in Figure 1AOperate as described. The digital output from the digital Δ-Σ modulator 122 is provided to the second terminal 104 of the Δ-Σ modulator circuit 100B. Using the Δ-Σ modulator circuit 100B, the combination of the multi-bit analog-to-digital conversion circuit system 128, the interpolation and filter circuit system 114, and the digital Δ-Σ modulator 122 provides a high-speed (low latency) single-bit modulator, where the speed has been increased by a factor of L without increasing the CLK.
[0027] In some instances, the Δ-Σ modulator circuit 100A or 100B can be part of an isolation modulator circuit. In other instances, the Δ-Σ modulator circuit 100A or 100B can be part of an isolation amplifier circuit.
[0028] Figure 2 Block diagram showing an example isolation modulator circuit 200. The isolation modulator circuit 200 has a first terminal 202 and a second terminal 204. The isolation modulator circuit 200 includes the Δ-Σ modulator circuit 100A or 100B and the digital isolator circuit system 206. The Δ-Σ modulator circuit 100A or 100B has Figure 1A and 1B the first terminal 102 and the second terminal described in. The digital isolator circuit system 206 has a first terminal 208 and a second terminal 210.
[0029] The first terminal 202 of the isolation modulator circuit 200 is coupled to the first terminal 102 of the Δ-Σ modulator circuit 100A or 100B. The second terminal 104 of the Δ-Σ modulator circuit 100A or 100B is coupled to the first terminal 208 of the digital isolator circuit system 206. The second terminal 210 of the digital isolator circuit system 206 is coupled to the second terminal 204 of the isolation modulator circuit 200.
[0030] In operation, the isolation modulator circuit 200 operates to: receive an analog input signal at the first terminal 202; provide a digital output based on the analog input signal and the operation of the Δ-Σ modulator circuit 100A or 100B; and isolate the digital output from the voltage domain of the isolation modulator circuit 200 using the digital isolator circuit system 206. In some instances, the digital output is a stream of 1-bit digital values.
[0031] In some instances, the isolation modulator circuit 200 is a stand-alone integrated circuit (IC). In other instances, the isolation modulator circuit 200 can be part of an IC that includes sensing components, signal conditioning circuits (e.g., gain amplifiers and graphics fidelity filters), or other components.
[0032] Figure 3FIG. is a block diagram showing an example isolation amplifier circuit 300. The isolation amplifier circuit 300 has a first terminal 302 and a second terminal 304. The isolation amplifier circuit 300 includes a Δ-Σ modulator circuit 100A or 100B, a digital isolator circuit system 206, and a DAC and LPF circuit system 306. The Δ-Σ modulator circuit 100A or 100B has Figure 1A and 1B the first terminal 102 and the second terminal described in Figure 2 . The digital isolator circuit system 206 has
[0033] the first terminal 208 and the second terminal 210 described in
[0034] . The DAC and LPF circuit system 306 has a first terminal 308 and a second terminal 310.
[0035] The first terminal 302 of the isolation amplifier circuit 300 is coupled to the first terminal 102 of the Δ-Σ modulator circuit 100A or 100B. The second terminal 104 of the Δ-Σ modulator circuit 100A or 100B is coupled to the first terminal 208 of the digital isolator circuit system 206. The second terminal 210 of the digital isolator circuit system 206 is coupled to the first terminal 308 of the DAC and LPF circuit system 306. The second terminal 310 of the DAC and LPF circuit system 306 is coupled to the second terminal 304 of the isolation amplifier circuit 300.
[0036] Figure 4 FIG. is a block diagram showing another example isolation amplifier circuit 300A. The isolation amplifier circuit 300A is an example of the isolation amplifier circuit 300. As shown, the isolation amplifier circuit 300A has Figure 3The first terminal 302 and the second terminal 304 described in Figure 1A . The multi-bit analog-to-digital conversion circuit system 106A in Figure 4 is an example of the multi-bit analog-to-digital conversion circuit system 106 in Figure 1A . In the example of Figure 1A , the multi-bit analog-to-digital conversion circuit system 106A includes a third-order 5-bit Δ-Σ modulator 113A. The third-order 5-bit Δ-Σ modulator 113A is an example of the Nth-order m-bit Δ-Σ modulator 113 in Figure 1A . The interpolation circuit system 402 and the filter circuit system 406 are example components of the interpolation and filter circuit system 114A. The interpolation and filter circuit system 114A is an example of the interpolation and filter circuit system 114 in Figure 4 . The digital Δ-Σ modulator 122A is an example of the digital Δ-Σ modulator 122 in
[0037] As shown, the multi-bit analog-to-digital conversion circuit system 106A has a first terminal 108, a second terminal 110, and a third terminal 112 described in Figure 1A . The interpolation circuit system 402 has a first terminal 116, a second terminal 118, and a third terminal 404. The filter circuit system 406 has a first terminal 408 and a third terminal 120. The digital Δ-Σ modulator 122A has a first terminal 124 and a second terminal 126. The digital isolator circuit system 206 has a first terminal 208 and a second terminal 210. The DAC and LPF circuit system 306 has a first terminal 308 and a second terminal 310.
[0038] In Figure 4 's example, the first terminal 302 of the isolation amplifier circuit 300A is coupled to the first terminal 108 of the multi-bit analog-to-digital conversion circuit system 106A. The second terminal 110 of the multi-bit analog-to-digital conversion circuit system 106A is coupled to a clock generator (not shown) and receives CLK. In Figure 4 's example, CLK = 12.8 MHz. The third terminal 112 of the multi-bit analog-to-digital conversion circuit system 106A is coupled to the first terminal 116 of the interpolation circuit system 402. The second terminal 118 of the interpolation circuit system 402 is coupled to a clock generator or a multiplier (not shown) and receives CLK*L. In Figure 4In an example, L = 8 and CLK * 8 = 102.4 MHz. The third terminal of the interpolation circuit system 402 is coupled to the first terminal 408 of the filter circuit system 406. In some examples, the filter circuit system 406 is a sinc1 filter. As used herein, a sinc1 filter refers to a moving average filter. In other examples, the filter circuit system 406 can be of higher order to provide better image rejection. The third terminal 120 of the filter circuit system 406 is coupled to the first terminal 124 of the digital Δ-Σ modulator 122A. The second terminal 126 of the digital Δ-Σ modulator 122A is coupled to the first terminal 208 of the digital isolator circuit system 206. The second terminal 210 of the digital isolator circuit system 206 is coupled to the first terminal 308 of the DAC and LPF circuit system 306. The second terminal 310 of the DAC and LPF circuit system 306 is coupled to the second terminal 304 of the isolation amplifier circuit 300A.
[0039] The isolation amplifier circuit 300A operates to: receive an analog input signal at the first terminal 302; convert the analog input signal to a modulated signal using the multi-bit analog-to-digital conversion circuit system 106A; and interpolate the modulated signal using the interpolation circuit system 402 to obtain an interpolation result. The isolation amplifier circuit 300A also operates to: filter the interpolation result using the filter circuit system 406 to obtain a filtered result; convert the filtered result to a digital output using the digital Δ-Σ modulator 122A; isolate the digital output using the digital isolator circuit system 206; amplify and filter the isolated digital stream using the DAC and LPF circuit system 306; and provide the amplified and filtered result from the DAC and LPF circuit system 306 to the second terminal 304 as the output of the isolation amplifier circuit 300A.
[0040] In some scenarios, the incoming bit stream to the DAC and LPF circuit system 306 has quantization noise at high frequencies. The LPF of the DAC and LPF circuit system 306 is used to filter this quantization noise. The order of the LPF can be selected to be one order higher than the order of the noise shaping of the incoming bit stream. In some examples, the LPF can be a combination of a continuous-time filter or a switched-capacitor filter followed by a continuous-time filter.
[0041] In some instances, the Δ-Σ modulator circuit 100A or 100B provides a single-bit modulator output at a high frequency to increase the available bandwidth. The multi-bit modulator output of the Δ-Σ modulator circuit 100A or 100B requires multiple digital isolators, which increases the cost. By combining the multi-bit A / D conversion circuit system 106 or 128 with the interpolation and filter circuit system 114 and the digital Δ-Σ modulator 122, a low-cost high-speed Δ-Σ modulator with available bandwidth is achieved. Without limitation, in some instances, the number of bits for the Nth-order m-bit Δ-Σ modulator 113 can be from 2 to 5. With a higher number of bits of the Nth-order m-bit Δ-Σ modulator 113, the available bandwidth increases. With a higher order of the Nth-order m-bit Δ-Σ modulator 113, the available bandwidth can also be increased by shaping the quantization noise. Without limitation, for stability, the Nth-order m-bit Δ-Σ modulator 113 can be a 5th-order or lower m-bit Δ-Σ modulator.
[0042] The interpolation factor L can vary depending on the number of bits provided by the multi-bit A / D conversion circuit system 106 and the order of noise shaping used by the digital Δ-Σ modulator 122. As the number of bits provided by the multi-bit A / D conversion circuit system 106 increases and as lower-order noise shaping is used in the digital Δ-Σ modulator 122, L increases. There are also practical limitations on the digital isolator data rate, which may set an upper limit on L. As an example, for a 3rd-order 5-bit Δ-Σ modulator, L = 8 may limit the useful bandwidth of both the analog and digital components of the Δ-Σ modulator. In the case of L = 16, the effect of the digital Δ-Σ modulator 122 on the quantization noise is negligible, and the useful bandwidth is limited only by the analog modulator (e.g., the Nth-order m-bit Δ-Σ modulator 113). The choice of the interpolation factor L and the filter can vary depending on the specific image rejection goal. Higher-order interpolation and filters provide better image rejection but add more delay. Additional image rejection can be obtained using low-pass filtering after the digital isolator circuit system 206. The image rejection performance of the Δ-Σ modulator circuit 100A is improved compared to the Δ-Σ modulator circuit 100B.
[0043] Figure 5 To illustrate an example full-scale step response graph 500 of an isolation amplifier circuit (e.g., Figure 3 isolation amplifier circuit 300 of Figure 4 or isolation amplifier circuit 300A of Figure 5In an example, the isolation amplifier circuit provides differential mode amplification as well as common mode rejection and isolation. The goal of using the Δ-Σ modulator circuit 100A or 100B together with an isolation modulator or an isolation amplifier is to reduce the time delay or latency (improve the bandwidth) while maintaining the target SNR.
[0044] Figure 6 FIG. 600 is a block diagram of an example system 600. As shown, the system 600 includes a monitored component 602, an isolation amplifier circuit 300B, a controller 608, and a digital isolator circuit 620. The isolation amplifier circuit 300B is an example of the isolation amplifier circuit 300 in Figure 3 or the isolation amplifier circuit 300A in Figure 4 . The monitored component 602 has a first terminal 604 and a second terminal 606. The isolation amplifier circuit 300B has a first terminal 302 and a second terminal 304. The controller 608 has a first terminal 610 and a second terminal 612. The digital isolator circuit 620 has a first terminal 622 and a second terminal 624. In an example of Figure 6 , the monitored component 602 and the isolation amplifier circuit 300B are part of a high voltage domain 614 (e.g., the ground of the high voltage domain 614 can differ from the ground of the low voltage domain 616 by 1 kV), and the controller 608 is part of the low voltage domain 616 (e.g., 3 to 5 V). The isolation amplifier circuit 300B and the digital isolator circuit 620 provide a signaling interface between the high voltage domain 614 and the low voltage domain 616.
[0045] As shown, the first terminal 604 of the monitored component 602 is coupled to the second terminal 624 of the digital isolator circuit 620. The second terminal 606 of the monitored component 602 is coupled to the first terminal 302 of the isolation amplifier circuit 300B. The second terminal 304 of the isolation amplifier circuit 300B is coupled to the first terminal 610 of the controller 608. The second terminal 612 of the controller 608 is coupled to the first terminal 622 of the digital isolator circuit 620.
[0046] The monitored component 602 operates to: receive a control signal (CS2, which is based on CS1) at the first terminal 604; perform an operation in response to CS2; and provide a first sense signal (e.g., V_Isense1) at the second terminal 606. Due to the high voltage domain 614 and the low voltage domain 616, CS2 is provided to the monitored component 602 via the digital isolator circuit 620. During the operation of the monitored component based on CS2, the monitored component 602 generates a first sense signal (e.g., V_Isense1) at the second terminal 606. The first sense signal can be a current sense signal or a voltage sense signal. In some examples, the first sense signal is combined with a common mode voltage (depending on the common mode voltage). In Figure 6In an example, the first sensed signal from the monitored component 602 is within the voltage supply range of the isolation amplifier circuit 300B.
[0047] The isolation amplifier circuit 300B operates to: receive the first sensed signal at the first terminal 302; isolate the first sensed signal from the high voltage domain 614 to the low voltage domain 616; and amplify the first sensed signal in the low voltage domain 616, thereby generating a second sensed signal (e.g., V_Isense2) based on the first sensed signal. In Figure 6 an example, the second sensed signal is transmitted to the controller 608 in the low voltage domain 616. The controller 608 operates to: receive the second sensed signal at the first terminal 610; adjust the control signal (CS1) based on the second sensed signal; and provide the adjusted CS1 at the second terminal 612. The digital isolator circuit 620 operates to: receive CS1 at the first terminal 622; isolate CS1 from the low voltage domain 616 to the high voltage domain 614, thereby generating CS2 based on CS1; and provide CS2 in the high voltage domain 614 to the monitored component 602. Over time, the control of the monitored component 602 is adjusted as needed. In some examples, the monitored component 602 is a motor, and the control signals (e.g., CS1 and / or CS2) from the controller 608 are the currents of the motor, where the control signals (e.g., CS1 and / or CS2) are adjusted in response to load, temperature, and / or other parameters.
[0048] In some examples, the first and second sensed signals (e.g., V_Isense1 and / or V_Isense2) provide phase current information, and the control signals (e.g., CS1 and / or CS2) are pulse width modulation (PWM) control signals or resulting power signals in response to the phase current being monitored. During control operation, the delay in monitoring the phase current affects the motor regulation loop. Using an isolation modulator with a lower time delay (higher speed) (e.g., Figure 2 the isolation modulator circuit 200 in Figure 3 or an isolation amplifier (e.g., Figure 4 the isolation amplifier circuit 300 or
[0049] Figure 7 FIG. 700 is a flowchart illustrating an example method 700. The method 700 may be performed by a Δ-Σ modulator (e.g., Figure 1A the Δ-Σ modulator circuit 100A in Figure 1Bexecuted by the Δ-Σ modulator circuit 100B) in or related products (e.g., isolation modulator or isolation amplifier). In Figure 7 In an example, method 700 includes converting an analog input signal to a multi-bit modulation signal in response to a first clock at block 702. At block 704, the multi-bit modulation signal is interpolated in response to a second clock to generate an interpolated signal. The second clock has a higher frequency than the first clock. At block 706, the interpolated signal is filtered to provide a filtered signal. At block 708, the filtered signal is noise shaped using a digital Δ-Σ modulator to provide a digital output.
[0050] In some examples, a circuit includes: a multi-bit analog-to-digital conversion circuit system (e.g., Figure 1A the multi-bit analog-to-digital conversion circuit system 106 in Figure 1B the multi-bit analog-to-digital conversion circuit system 128 in or related circuit systems); an interpolation circuit (e.g., Figure 1A and 1B a portion of the interpolation and filter circuit system 114 in, or Figure 4 the interpolation circuit system 402 in); a filter (e.g., Figure 1A and 1B a portion of the interpolation and filter circuit system 114 in, or Figure 4 the filter circuit system 406 in); and a digital Δ-Σ modulator (e.g., Figure 1A and 1B the digital Δ-Σ modulator 122 in or Figure 4 the digital Δ-Σ modulator 122A in). The multi-bit analog-to-digital conversion circuit system has a first terminal (e.g., Figure 1A the first terminal 108 in or Figure 1B the first terminal 130 in) and a second terminal (e.g., Figure 1A the third terminal 112 in or Figure 1B the third terminal 134 in). The interpolation circuit has a first terminal (e.g., Figure 4 the first terminal 116 in) and a second terminal (e.g., Figure 4 the third terminal 404 in). The first terminal of the interpolation circuit is coupled to the second terminal of the multi-bit analog-to-digital conversion circuit system. The filter has a first terminal (e.g., Figure 4 the first terminal 408 in) and a second terminal (e.g., Figure 4 the third terminal 120 in). The first terminal of the filter is coupled to the second terminal of the interpolation circuit. The digital Δ-Σ modulator has a first terminal (e.g., Figure 1A , 1B and 4 the first terminal 124 in) and a second terminal (e.g., Figure 1A , 1Band the second terminal 126 in 4). The first terminal of the digital Δ-Σ modulator is coupled to the second terminal of the filter.
[0051] In some examples, the multi-bit analog-to-digital conversion circuit system includes an Nth-order m-bit Δ-Σ modulator (e.g., Figure 1A the Nth-order m-bit Δ-Σ modulator 113 in ). Where N and m are integers greater than 1. In some examples, the Δ-Σ modulator is a 3rd-order 5-bit Δ-Σ modulator, and the digital Δ-Σ modulator is a 2nd-order 1-bit digital Δ-Σ modulator. In some examples, the multi-bit analog-to-digital conversion circuit system includes a Nyquist-rate ADC that provides a multi-bit output in one clock cycle (e.g., Figure 1B the Nyquist-rate ADC 135 in ). In some examples, the Nyquist-rate ADC is a SAR ADC. Without limitation, the multi-bit analog-to-digital conversion circuit system can be timed at a rate of 10Mhz to 20MHz, while the interpolation circuit is timed at a rate of 80MHz to 160MHz.
[0052] In some examples, the circuit includes an isolation circuit system having a first terminal (e.g., Figures 2 to 4 the first terminal 208 in ) and a second terminal (e.g., Figures 2 to 4 the second terminal 210 in ). (e.g., Figures 2 to 4 the digital isolator circuit system 206 in ). The first terminal of the isolation circuit system is coupled to the second terminal of the digital Δ-Σ modulator. In some examples, the isolation circuit system is coupled to the digital Δ-Σ modulator to isolate the digital output of the digital Δ-Σ modulator between different ground potentials.
[0053] In some examples, the multi-bit analog-to-digital conversion circuit system, the interpolation circuit, the filter, the digital Δ-Σ modulator, and the isolation circuit system are components of an independent isolated modulator integrated circuit. In some examples, the circuit includes a DAC and LPF circuit system having a first terminal (e.g., Figure 3 and 4 the first terminal 308 in ) and a second terminal (e.g., Figure 3 and 4 the second terminal 310 in ). (e.g., Figure 3 and 4 the DAC and LPF circuit system 306 in ). The first terminal of the DAC and LPF circuit system is coupled to the second terminal of the isolation circuit system. In some examples, the DAC and LPF circuit system converts the digital output from the digital isolation circuit system into a filtered analog signal. In some examples, the multi-bit analog-to-digital conversion circuit system, the interpolation circuit, the filter, the digital Δ-Σ modulator, the isolation circuit system, and the digital-to-analog converter and low-pass filter circuit system are components of an independent isolated amplifier integrated circuit.
[0054] In some examples, a circuit includes: a monitored component (e.g., the monitored component 602 in Figure 6 ); a controller (e.g., the controller 608 in Figure 6 ); and a digital isolator circuit (e.g., the digital isolator circuit 620 in Figure 6 ). The monitored component has a first terminal (e.g., the first terminal 604 in Figure 6 ) and a second terminal (e.g., the second terminal 606 in Figure 6 ). The controller has a first terminal (e.g., the first terminal 610 in Figure 6 ) and a second terminal (e.g., the second terminal 612 in Figure 6 ). The digital isolator circuit has a first terminal (e.g., the first terminal 622 in Figure 6 ) and a second terminal (e.g., the second terminal 624 in Figure 6 ). In such examples, the first terminal of the controller is coupled to the second terminal of a digital-to-analog converter and a low-pass filter circuitry. The second terminal of the controller is coupled to the first terminal of the digital isolator circuit. The second terminal of the digital isolator circuit is coupled to the first terminal of the monitored component. The second terminal of the monitored component is coupled to the first terminal of a multi-bit analog-to-digital conversion circuitry. In some examples, the monitored component is a motor.
[0055] In this specification, the term “coupled” may encompass a connection, communication, or signal path that enables a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.
[0056] Additionally, in this specification, the recitation “based on” means “at least partially based on”. Thus, if X is based on Y, then X may depend on Y and any number of other factors.
[0057] A device “configured to” perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.
[0058] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components or their ends.
[0059] A circuit or device described herein as including certain components may in fact be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may in fact include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, e.g., by an end user and / or a third party.
[0060] The circuits described herein may be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may in fact be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may in fact be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.
[0061] Although some elements of the described examples are included within an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit may be included within the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / above a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.
[0062] The use of the phrase "ground" in the foregoing description encompasses chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about", "substantially", or "essentially" preceding a parameter means within + / - 10% of the stated parameter, or if the parameter is zero, within a reasonable value that is approximately zero.
[0063] Within the scope of the claims, modifications may be made in the described examples, and other examples are possible.
Claims
1. A circuit comprising: A multi-bit analog-to-digital conversion circuit system having a first terminal and a second terminal; an interpolation circuit having a first terminal and a second terminal, the first terminal of the interpolation circuit being coupled to the second terminal of the multi-bit analog-to-digital conversion circuitry; a filter having a first terminal and a second terminal, the first terminal of the filter being coupled to the second terminal of the interpolation circuit; and A digital delta-sigma modulator has a first terminal and a second terminal, the first terminal of the digital delta-sigma modulator being coupled to the second terminal of the filter. 2 . The circuit of claim 1 , wherein the multi-bit analog-to-digital conversion circuitry comprises an N-th order, m-bit delta-sigma modulator, wherein N and m are integers greater than 1. 3 . 3 . The circuit of claim 2 , wherein the delta-sigma modulator is a 3 rd order 5-bit delta-sigma modulator and the digital delta-sigma modulator is a 2 nd order 1-bit digital delta-sigma modulator.
4. The circuit of claim 1 wherein the multi-bit analog-to-digital conversion circuitry comprises a Nyquist rate ADC that provides a multi-bit output in one clock cycle.
5. The circuit of claim 4, wherein the Nyquist rate ADC is a successive approximation SAR ADC.
6. The circuit of claim 1, further comprising isolation circuitry having a first terminal and a second terminal, the first terminal of the isolation circuitry coupled to the second terminal of the digital delta-sigma modulator.
7. The circuit of claim 6 wherein the multi-bit analog-to-digital conversion circuitry, the interpolation circuitry, the filter, the digital delta-sigma modulator, and the isolation circuitry are components of a stand-alone isolated modulator integrated circuit.
8. The circuit of claim 6, further comprising a digital-to-analog converter and low-pass filter circuitry having a first terminal and a second terminal, the first terminal of the digital-to-analog converter and low-pass filter circuitry being coupled to the second terminal of the isolation circuitry.
9. The circuit of claim 8 wherein the multi-bit analog-to-digital conversion circuitry, the interpolation circuitry, the filter, the digital delta-sigma modulator, the isolation circuitry, and the digital-to-analog converter and low-pass filter circuitry are components of a stand-alone isolation amplifier integrated circuit.
10. The circuit of claim 8, further comprising a monitored component, a controller, and a digital isolator circuit, the monitored component having a first terminal and a second terminal, the controller having a first terminal and a second terminal, the digital isolator circuit having a first terminal and a second terminal, the first terminal of the controller coupled to the second terminal of the digital-to-analog converter and low-pass filter circuitry, the second terminal of the controller coupled to the first terminal of the digital isolator circuit, the second terminal of the digital isolator circuit coupled to the first terminal of the monitored component, and the second terminal of the monitored component coupled to the first terminal of the multi-bit analog-to-digital conversion circuitry.
11. The circuit of claim 10, wherein the monitored component is a motor.
12. A circuit comprising: a multi-bit delta-sigma modulator having a first terminal and a second terminal; an interpolation circuit having a first terminal and a second terminal, the first terminal of the interpolation circuit being coupled to the second terminal of the multi-bit delta-sigma modulator; a filter having a first terminal and a second terminal, the first terminal of the filter being coupled to the second terminal of the interpolation circuit; a digital delta-sigma modulator having a first terminal and a second terminal, the first terminal of the digital delta-sigma modulator being coupled to the second terminal of the filter; and Isolation circuitry has a first terminal and a second terminal, the first terminal of the isolation circuitry being coupled to the second terminal of the digital delta-sigma modulator.
13. The circuit of claim 12, further comprising a digital-to-analog converter and low-pass filter circuitry having a first terminal and a second terminal, the first terminal of the digital-to-analog converter and low-pass filter circuitry being coupled to the second terminal of the isolation circuitry.
14. The circuit of claim 12, wherein the multi-bit delta-sigma modulator is an N-order, m-bit delta-sigma modulator, where N and m are integers greater than 1.
15. The circuit of claim 12, wherein the multi-bit delta-sigma modulator is a 3rd order 5-bit delta-sigma modulator and the digital delta-sigma modulator is a 2nd order 1-bit digital delta-sigma modulator.
16. A circuit comprising: a multi-bit analog-to-digital conversion circuit system configured to convert an analog input signal into a multi-bit signal; an interpolation circuit coupled to the multi-bit analog-to-digital conversion circuitry and configured to interpolate the multi-bit signal to generate an interpolated signal; a filter coupled to the interpolation circuit and configured to filter the interpolated signal to generate a filtered signal; and A digital delta-sigma modulator is coupled to the filter and configured to digitize the filtered signal.
17. The circuit of claim 16, wherein the multi-bit analog-to-digital conversion circuitry comprises a 3rd order 5-bit delta-sigma modulator and the digital delta-sigma modulator is a 2nd order 1-bit digital delta-sigma modulator.
18. The circuit of claim 16, wherein the multi-bit analog-to-digital conversion circuitry comprises a Nyquist rate analog-to-digital converter (ADC) that provides a multi-bit output in one clock cycle.
19. The circuit of claim 16, further comprising isolation circuitry coupled to the digital delta-sigma modulator and configured to isolate a digital output of the digital delta-sigma modulator between different ground potentials.
20. The circuit of claim 19, further comprising a digital-to-analog converter and low-pass filter circuitry coupled to the isolation circuitry and configured to convert the digital output to a filtered analog signal.