A signal sampling and processing system and method for multi-chip synchronization

Abstract

The present invention discloses a signal sampling and processing system and method for multi-chip synchronization, relating to the field of transceiver chips. The system comprises: a clock generation circuit inputting a first differential signal and a second differential signal; synchronously sampling the received signals of multiple transceiver chips to obtain a first synchronization signal and a second synchronization signal; delaying the first synchronization signal and the second synchronization signal until the signals are stable; using the first synchronization signal and the second synchronization signal to generate two control signals with a phase difference of 180°; selecting any one of the control signals to connect to the switch between the clock generation circuit; and selecting another control signal to be sent to the clock generation circuit if the four-phase local oscillator clock signal output by the clock generation circuit is phase-ambiguous. The present invention can achieve multi-chip synchronization, eliminate phase ambiguity, and ensure that the phase of the chip clock remains unchanged.

Description

Technical Field

[0001] The present invention relates to the field of transceiver chips, and in particular to a signal sampling and processing system and method for multi-chip synchronization. Background Art

[0002] In modern communications systems, synchronization of RF transceiver chips is a critical issue. When multiple transceiver chips operate simultaneously, ensuring phase consistency between their local oscillator (LO) clocks and baseband clocks is crucial. However, existing technologies can cause clock phase ambiguity due to factors such as temperature fluctuations and signal interference, making it impossible to achieve precise synchronization among multiple chips. This phase ambiguity primarily stems from the randomness of signal edge alignment in the phase-locked loop (PLL) and clock generation circuits, posing challenges to system stability and performance. Although some solutions have been developed in recent years to mitigate this issue through improved circuit design or additional calibration steps, they remain unable to fundamentally eliminate the impact of phase ambiguity.

[0003] Specifically, when multiple RF transceiver chips operate simultaneously, after the system sends a synchronization signal to each chip, the local oscillator (IQ) clocks of each transceiver chip must maintain a fixed phase. The same requirements apply to the baseband clock phase, requiring that the local oscillator (LO) clocks and baseband clock generation circuits must be free of phase ambiguity. If the LO frequency is generated by a phase-locked loop (PLL) using fractional division, the LO IQ clocks can be looped back into the PLL, where a digital algorithm can be used to maintain a fixed LO clock phase. However, this approach struggles with integer division. Another approach involves delaying the synchronization signal sent by the system to offset the clock edges of the LO PLL or baseband PLL, thus avoiding phase ambiguity in the output clock. This approach is also unreliable because it cannot guarantee that the synchronization signal will remain aligned with the PLL clock edges despite temperature fluctuations, especially at high frequencies (RF transceivers typically operate at very high frequencies, with the PLL output frequency reaching up to 13 GHz). Therefore, there is a need for a signal sampling and processing system and method for multi-chip synchronization, which can achieve multi-chip synchronization, eliminate phase ambiguity, and ensure that the phase of the local oscillator clock or baseband clock of the chip remains unchanged after each synchronization signal arrives. Summary of the Invention

[0004] The technical problem to be solved by the present invention is how to achieve multi-chip synchronization, eliminate phase ambiguity, and ensure that the phase of the local oscillator clock or baseband clock of the chip remains unchanged after each synchronization signal arrives. The purpose is to provide a signal sampling and processing system and method for multi-chip synchronization to solve the above technical problems.

[0005] The present invention is achieved through the following technical solutions:

[0006] A signal sampling and processing system for multi-chip synchronization is applied to multiple transceiver chips. The processing system includes: a phase-locked loop for generating a first differential signal and a second differential signal; a clock generation circuit for inputting the first differential signal and the second differential signal; and the processing system further includes:

[0007] A sampling unit synchronously samples the received signals of the multiple transceiver chips to obtain a first synchronization signal and a second synchronization signal, wherein the sampling signal of the first synchronization signal is a first differential signal, and the sampling signal of the other signal is a second differential signal;

[0008] a delay unit, configured to delay the first synchronization signal and the second synchronization signal so that the first differential signal is synchronized with the first synchronization signal and the second differential signal is synchronized with the second synchronization signal;

[0009] a synchronization unit, generating two control signals based on the first synchronization signal and the second synchronization signal, respectively, wherein the two control signals have the same duty cycle and frequency and a phase difference of 180°;

[0010] The switch selection unit selects any one of the control signals to be sent to the clock generation circuit, and if the four-phase local oscillator clock signal output by the clock generation circuit is phase-ambiguous, another control signal is selected in turn to be sent to the clock generation circuit until no phase ambiguity occurs.

[0011] Furthermore, the sampling unit includes a first RS trigger and a second RS trigger; the first RS trigger and the second RS trigger respectively receive the synchronization control signals of multiple transceiver chips; the sampling signal of the first RS trigger is a first differential signal, and the sampling signal of the second RS trigger is a second differential signal.

[0012] Furthermore, the sampling unit includes a fifth D flip-flop and a sixth D flip-flop; the fifth D flip-flop and the sixth D flip-flop respectively receive the synchronization control signals of multiple transceiver chips; the sampling signal of the fifth D flip-flop is a first differential signal, and the sampling signal of the sixth D flip-flop is a second differential signal.

[0013] Furthermore, the delay unit includes a third RS trigger and a fourth RS trigger; the input end of the third RS trigger is connected to the output end of the first RS trigger; the input end of the fourth RS trigger is connected to the output end of the second RS trigger; the sampling signal of the third RS trigger is the second differential signal; the sampling signal of the fourth RS trigger is the first differential signal.

[0014] Furthermore, the synchronization unit includes a first D flip-flop, a second D flip-flop, a third D flip-flop and a fourth D flip-flop; the input end of the second D flip-flop is connected to the output end of the first RS flip-flop; the first D flip-flop, the second D flip-flop and the third RS flip-flop are connected in parallel; the sampling signal of the first D flip-flop is a first differential signal; the sampling signal of the second D flip-flop is a second differential signal; the input end of the fourth D flip-flop is connected to the output end of the second RS flip-flop; the third D flip-flop, the fourth D flip-flop and the fourth RS flip-flop are connected in parallel; the sampling signal of the fourth D flip-flop is the first differential signal; and the sampling signal of the third D flip-flop is the second differential signal.

[0015] Furthermore, the switch selection unit includes a first switch, a second switch, a third switch and a fourth switch; the output end of the first D flip-flop is connected to the input end of the clock generating circuit through the first switch; the output end of the second D flip-flop is connected to the input end of the clock generating circuit through the second switch; the output end of the third D flip-flop is connected to the input end of the clock generating circuit through the third switch; and the output end of the fourth D flip-flop is connected to the input end of the clock generating circuit through the fourth switch.

[0016] Furthermore, the phase-locked loop is a local oscillator phase-locked loop, and the clock generating circuit is a local oscillator clock or baseband clock generating circuit.

[0017] A signal sampling and processing method for multi-chip synchronization is applied to multiple transceiver chips. The processing method includes: a phase-locked loop for generating a first differential signal and a second differential signal; a clock generation circuit for inputting the first differential signal and the second differential signal. The processing method also includes the following steps:

[0018] Synchronously sampling received signals of multiple transceiver chips to obtain a first synchronization signal and a second synchronization signal; wherein the sampling signal of the first synchronization signal is the first differential signal, and the sampling signal of another signal is the second differential signal;

[0019] delaying the first synchronization signal and the second synchronization signal so that the first differential signal is synchronized with the first synchronization signal and the second differential signal is synchronized with the second synchronization signal;

[0020] generating two control signals based on the first synchronization signal and the second synchronization signal, respectively, wherein the two control signals have the same duty cycle and frequency and a phase difference of 180°;

[0021] Any one of the control signals is selected and sent to the clock generating circuit. If the four-phase local oscillator clock signal output by the clock generating circuit is phase-ambiguous, another control signal is selected and sent to the clock generating circuit in turn until no phase ambiguity occurs.

[0022] Furthermore, the sampling unit includes a first RS trigger and a second RS trigger; the first RS trigger and the second RS trigger respectively receive the synchronization control signals of multiple transceiver chips; the sampling signal of the first RS trigger is the first differential signal, and the sampling signal of the second RS trigger is the second differential signal.

[0023] Furthermore, the sampling unit includes a fifth D flip-flop and a sixth D flip-flop; the fifth D flip-flop and the sixth D flip-flop respectively receive the synchronization control signals of multiple transceiver chips; the sampling signal of the fifth D flip-flop is the first differential signal, and the sampling signal of the sixth D flip-flop is the second differential signal.

[0024] Furthermore, the delay unit includes a third RS trigger and a fourth RS trigger; the input end of the third RS trigger is connected to the output end of the first RS trigger; the input end of the fourth RS trigger is connected to the output end of the second RS trigger; the sampling signal of the third RS trigger is the second differential signal; the sampling signal of the fourth RS trigger is the first differential signal.

[0025] Furthermore, the synchronization unit includes a first D flip-flop, a second D flip-flop, a third D flip-flop and a fourth D flip-flop; the input end of the second D flip-flop is connected to the output end of the first RS flip-flop; the first D flip-flop, the second D flip-flop and the third RS flip-flop are connected in parallel; the sampling signal of the first D flip-flop is the first differential signal; the sampling signal of the second D flip-flop is the second differential signal; the input end of the fourth D flip-flop is connected to the output end of the second RS flip-flop; the third D flip-flop, the fourth D flip-flop and the fourth RS flip-flop are connected in parallel; the sampling signal of the fourth D flip-flop is the first differential signal; and the sampling signal of the third D flip-flop is the second differential signal.

[0026] The switch selection unit includes a first switch, a second switch, a third switch and a fourth switch; the output end of the first D flip-flop is connected to the input end of the clock generation circuit through the first switch; the output end of the second D flip-flop is connected to the input end of the clock generation circuit through the second switch; the output end of the third D flip-flop is connected to the input end of the clock generation circuit through the third switch; and the output end of the fourth D flip-flop is connected to the input end of the clock generation circuit through the fourth switch.

[0027] The phase-locked loop is a local oscillator phase-locked loop;

[0028] The clock generating circuit is a local oscillator clock or a baseband clock generating circuit.

[0029] A signal sampling and processing method for multi-chip synchronization, applied to multiple transceiver chips; the processing method comprises: a phase-locked loop for generating a first differential signal and a second differential signal; a clock generation circuit for inputting the first differential signal and the second differential signal; the processing method further comprises the following steps:

[0030] Synchronously sampling received signals of multiple transceiver chips to obtain a first synchronization signal and a second synchronization signal; wherein the sampling signal of the first synchronization signal is the first differential signal, and the sampling signal of another signal is the second differential signal;

[0031] delaying the first synchronization signal and the second synchronization signal so that the first differential signal is synchronized with the first synchronization signal and the second differential signal is synchronized with the second synchronization signal;

[0032] generating two control signals based on the first synchronization signal and the second synchronization signal, respectively, wherein the two control signals have the same duty cycle and frequency and a phase difference of 180°;

[0033] Any one of the control signals is selected and sent to the clock generating circuit. If the four-phase local oscillator clock signal output by the clock generating circuit is phase-ambiguous, another control signal is selected in turn and sent to the clock generating circuit until no phase ambiguity occurs.

[0034] The synchronous sampling of the synchronization control signals of the plurality of transceiver chips to obtain the first synchronization signal and the second synchronization signal includes:

[0035] respectively sampling the first synchronization signal and the second synchronization signal using an RS trigger or a D trigger;

[0036] The delaying the first synchronization signal and the second synchronization signal includes:

[0037] Using an RS trigger to block the first synchronization signal and the second synchronization signal;

[0038] Generating two control signals based on the first synchronization signal and the second synchronization signal respectively includes:

[0039] Two D flip-flops are respectively used to generate the first synchronization signal and the synchronization signal control signal;

[0040] The selecting any one of the control signals to be sent to the clock generating circuit comprises:

[0041] Different switches are used to control whether each of the control signals is sent to the clock generating circuit.

[0042] The selecting any one of the control signals to be sent to the clock generating circuit comprises:

[0043] Two control signals generated based on the first synchronization signal and two control signals generated based on the second synchronization signal are respectively sent to the clock generation circuit.

[0044] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0045] The present invention provides a signal sampling and processing system for multi-chip synchronization. The system uses a differential clock signal provided by a phase-locked loop (PLL) to resynchronize an off-chip input synchronization signal, and outputs synchronization signals of different phases through a signal selection mechanism, ensuring that the transceiver local oscillator clock and baseband clock maintain phase stability after the synchronization signal arrives. Specifically, a first differential signal and a second differential signal are generated by a PLL and input into a clock generation circuit. A sampling unit synchronously samples the received signals of multiple transceiver chips. The sampling signal of the first synchronization signal is the first differential signal, and the sampling signal of another signal is the second differential signal. A delay unit delays the first synchronization signal and the second synchronization signal until the signals are stable. The synchronization unit uses the first synchronization signal and the second synchronization signal to generate two control signals respectively. The phase difference between the two control signals is 180 degrees. A switch selection unit sequentially selects the switches between each control signal and the clock generation circuit. If the four-phase local oscillator clock signal output by the clock generation circuit is phase-ambiguous, it means that the selected control signal can be sequentially selected up to four times. The present invention uses a phase-locked loop (PLL) to resynchronize the synchronization signals input by multiple chips. The signal enters a clock generation circuit, which outputs four synchronization signals. Signal selection is performed based on phase ambiguity, avoiding phase ambiguity caused by collisions with the edges of the signal sent by the PLL. The synchronization signal selected by the PLL is guaranteed to be sufficiently distant from the PLL's own signal edges, thus preventing phase ambiguity even with temperature fluctuations. This invention enables multi-chip synchronization, eliminates phase ambiguity, and ensures that the phase of the chip's local oscillator clock or baseband clock remains unchanged after each synchronization signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for use in the examples. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be considered as limiting the scope. A person of ordinary skill in the art can also derive other relevant drawings based on these drawings without inventive effort. In the drawings:

[0047] Figure 1 Schematic diagram of a phase-locked loop and a clock generation circuit under ideal conditions in an embodiment of the present application;

[0048] Figure 2 A schematic diagram of signal synchronization generated by a clock generation circuit under ideal conditions in an embodiment of the present application;

[0049] Figure 3 A schematic diagram of signal synchronization generated by a clock generation circuit in the prior art of this application;

[0050] Figure 4 A schematic diagram of an inverter delay signal in the prior art of an embodiment of the present application;

[0051] Figure 5 A schematic diagram of signal synchronization generated by a clock generation circuit in the prior art of an embodiment of the present application;

[0052] Figure 6 Schematic diagram of a signal sampling and processing system for multi-chip synchronization according to an embodiment of the present application;

[0053] Figure 7 A schematic diagram of a conventional RS trigger used in an embodiment of the present application;

[0054] Figure 8 This is an example diagram of a sampling unit according to an embodiment of the present application;

[0055] Figure 9 This is an example diagram of a synchronization unit according to an embodiment of the present application. DETAILED DESCRIPTION

[0056] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0057] The following describes the specific embodiments of the present application in detail in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant invention and are not intended to limit the invention. It should also be noted that, for ease of description, only the portions relevant to the relevant invention are shown in the accompanying drawings.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are for the purpose of describing specific implementation methods only and are not intended to limit this application; unless otherwise defined, all technical and scientific terms used herein have the same common meaning as commonly understood by those with ordinary skills in the art to which this application belongs; in order to avoid unnecessary disputes, the terms "first", "second", etc. cited in this application are set to distinguish similar things and have no other special meanings.

[0059] In addition, although the flowcharts in the figures recorded in this application show the processing procedures according to various embodiments of the present application, it should be understood that this application is not limited to the order and arrangement shown in the figures, but it is possible to perform processing in an order different from that shown in the figures (such as, substantially simultaneously, or in reverse order), depending on the functions / behaviors involved.

[0060] Example

[0061] A phase-locked loop (PLL) is a circuit used to generate a stable clock signal. It locks the phase and frequency of the input signal, thereby outputting a signal that matches the input signal's phase and frequency. In this solution, the PLL output is a differential clock signal, consisting of two complementary signal lines. This signal is more resistant to electromagnetic interference and improves signal integrity.

[0062] like Figures 6 to 9 As shown, an embodiment of the present application provides a signal sampling and processing system for multi-chip synchronization, which is applied to multiple transceiver chips; the processing system includes: a phase-locked loop for generating a first differential signal and a second differential signal; a clock generation circuit for inputting the first differential signal and the second differential signal; the processing system also includes:

[0063] A sampling unit synchronously samples the received signals of multiple transceiver chips to obtain a first synchronization signal and a second synchronization signal; wherein the sampling signal of the first synchronization signal is a first differential signal, and the sampling signal of the other signal is a second differential signal;

[0064] a delay unit, configured to delay the first synchronization signal and the second synchronization signal so that the first differential signal is synchronized with the first synchronization signal and the second differential signal is synchronized with the second synchronization signal;

[0065] a synchronization unit, generating two control signals based on the first synchronization signal and the second synchronization signal, respectively, wherein the two control signals have the same duty cycle and frequency and a phase difference of 180°;

[0066] The switch selection unit selects any one of the control signals and sends it to the clock generation circuit. If the four-phase local oscillator clock signals output by the clock generation circuit are phase-ambiguous, indicating that the four signals have different phases, another control signal is selected and sent to the clock generation circuit in sequence until a control signal without phase ambiguity is selected and sent to the clock generation circuit. In this way, another control signal is selected up to four times and sent to the clock generation circuit.

[0067] A transceiver chip, also known as an interface transceiver chip, is an integrated circuit used for data communication, which is mainly responsible for sending and receiving data between different devices or systems.

[0068] A phase-locked loop (PLL) is a control system that generates an output signal whose phase is aligned with the input signal. There are several different types. The simplest is an electronic circuit consisting of a variable-frequency oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares the phase of this signal with the phase of the input periodic signal, adjusting the oscillator to maintain phase matching. Keeping the input and output phases in lockstep also means keeping the input and output frequencies the same. Therefore, in addition to synchronizing the signal, a phase-locked loop can also track the input frequency or generate the input frequency.

[0069] A clock circuit is an oscillator circuit that produces precise, clock-like motion. All operations follow a timed sequence. The circuit used to generate this time is called a clock circuit. A clock circuit typically consists of a crystal oscillator, a crystal control chip, and capacitors. An oscillator is a circuit that generates a stable, periodic signal. The operating principle of a clock circuit is based on the properties of an oscillator. When connected to an appropriate feedback network, an oscillator self-oscillates, producing a continuous, periodic waveform. These waveforms are typically square, sinusoidal, or pulse waveforms, representing discrete intervals of time.

[0070] The phase-locked loop is a local oscillator phase-locked loop, and the clock generating circuit is a local oscillator clock or a baseband clock generating circuit.

[0071] A local oscillator (LO) phase-locked loop (PLL) is a closed-loop system consisting of a phase-locked loop (PLL) and a voltage-controlled oscillator (VCO). A PLL is a negative feedback control system used to maintain a constant phase difference between the input signal and a reference signal. A VCO is a voltage-controlled oscillator whose output frequency can be adjusted by controlling the input voltage. When the PLL is operating, the reference signal is first divided to obtain a reference frequency, which is then multiplied by the input signal to produce an error signal. This error signal is filtered and amplified, then input into the VCO as a control signal to adjust the VCO's output frequency. By continuously adjusting the VCO's frequency, the phase difference between the input signal and the reference signal is maintained at a constant value, thereby achieving stable and accurate frequency.

[0072] The sampling unit includes a first RS trigger and a second RS trigger; the first RS trigger and the second RS trigger respectively receive the synchronization control signals of multiple transceiver chips; the sampling signal of the first RS trigger is a first differential signal, and the sampling signal of the second RS trigger is a second differential signal.

[0073] The sampling unit includes a fifth D flip-flop and a sixth D flip-flop; the input ends of the fifth D flip-flop and the sixth D flip-flop respectively receive the synchronization control signals of multiple transceiver chips; the sampling signal of the fifth D flip-flop is a first differential signal, and the sampling signal of the sixth D flip-flop is a second differential signal.

[0074] The delay unit includes a third RS trigger and a fourth RS trigger; the input end of the third RS trigger is connected to the output end of the first RS trigger; the input end of the fourth RS trigger is connected to the output end of the second RS trigger; the sampling signal of the third RS trigger is the second differential signal; the sampling signal of the fourth RS trigger is the first differential signal.

[0075] The synchronization unit includes a first D flip-flop, a second D flip-flop, a third D flip-flop and a fourth D flip-flop; the input end of the second D flip-flop is connected to the output end of the first RS flip-flop; the first D flip-flop, the second D flip-flop and the third RS flip-flop are connected in parallel; the sampling signal of the first D flip-flop is a first differential signal; the sampling signal of the second D flip-flop is a second differential signal; the input end of the fourth D flip-flop is connected to the output end of the second RS flip-flop; the third D flip-flop, the fourth D flip-flop and the fourth RS flip-flop are connected in parallel; the sampling signal of the fourth D flip-flop is the first differential signal; and the sampling signal of the third D flip-flop is the second differential signal.

[0076] The switch selection unit includes a first switch, a second switch, a third switch and a fourth switch; the output end of the first D flip-flop is connected to the input end of the clock generation circuit through the first switch; the output end of the second D flip-flop is connected to the input end of the clock generation circuit through the second switch; the output end of the third D flip-flop is connected to the input end of the clock generation circuit through the third switch; and the output end of the fourth D flip-flop is connected to the input end of the clock generation circuit through the fourth switch.

[0077] Figure 1 This is an ideal situation in the existing technology. In fact, the synchronization signal sync_en signal of multiple chips sent by the system is asynchronous with the first differential signal PLL_outn and the second differential signal PLL_outp output of the phase-locked loop. Sync_en may appear at any phase of the PLL output clock generation circuit. Figure 2 express Figure 1 In the ideal case shown in FIG, after receiving this signal, the local oscillator clock generation circuit starts from the next rising edge of PLL_outp (falling edge of PLL_outn) and sequentially generates the four-phase local oscillator Q, I, QB, and IB signals. Figure 3 Shows the situation where sync_en appears at the rising edge of PLL_outp (falling edge of PLL_outn). Here, because sync_en appears just at the edge where the local oscillator clock generation circuit is about to change, due to the influence of clock jitter, temperature, etc., the circuit may respond immediately (corresponding to Figure 3 The first case); It is also possible that the circuit cannot respond immediately, then it will be postponed to the next rising edge of PLL_outp, that is, the next falling edge of PLL_outn (corresponding to Figure 3(The second case). The four-phase local oscillator clocks in the first and second cases differ by 180°. This means that two possible scenarios can occur after the sync_en signal arrives, a phenomenon known as phase ambiguity. Because RF phase-locked loops operate at high frequencies (several GHz to over 10 GHz), clock edges are not very sharp, and circuit response time accounts for a high proportion of the clock period. Therefore, the probability of this phenomenon occurring is quite high. Figure 3 For example, if the local oscillator clock and the local oscillator phase-locked loop clock are not divided by two, the phase ambiguity may not be 180°. This phenomenon can affect the synchronization of multiple transceiver chips. The same problem also exists in baseband clock generation circuits.

[0078] Figure 4 and Figure 5 The demonstration shows an existing technology that uses an inverter delay to delay the sync_en signal, and then uses a switch to select the appropriate sync_en_out signal to stagger the phase-locked loop clock edge. The disadvantage of this technology is that the delay stagger may not be sufficient. Even if the chip is configured at room temperature to eliminate phase ambiguity in the circuit, there may still be a point where the local oscillator clock will cause circuit phase ambiguity within the chip's operating temperature range. Figure 5 As shown, there is a temperature between -40°C and 130°C that causes phase ambiguity in the local oscillator clock generation circuit. This problem is particularly pronounced when the phase-locked loop operates at high frequencies, causing the chip to become unstable. The aforementioned technology makes it difficult to determine whether the phase offset is sufficient and to determine the appropriate phase delay.

[0079] Figure 6 The switch selection unit selects the synchronization signal and is composed of an RS flip-flop, a D flip-flop and a switch. Figure 7This is an example of an RS flip-flop. First, the synchronization signal sync_en, received from the chip, is sampled by the first RS flip-flop (RS flip-flop 1) and the second RS flip-flop (RS flip-flop 2). The sampled signals are the first and second differential signals of the phase-locked loop (PLL_outn and PLL_outp), respectively. The purpose of using two differential signals for separate sampling is to avoid the edges of the sampled signal and the sync_en signal from colliding at this step, which would cause phase ambiguity. For example, if the edges of sync_en and PLL_outp intersect, the distance between sync_en and PLL_outn is optimal, and the phase difference between PLL_outp and PLL_outn is 180°. Subsequently, the first switch sync_en_sel1 and the second switch sync_en_sel2 can be selected, rather than the third and fourth switches sync_en_sel3 and sync_en_sel4, which could cause phase ambiguity. After the first step of sampling, the first synchronization signal sync_en_int1 and the second synchronization signal sync_en_int2 are respectively sent to the first D flip-flop (D flip-flop 1), the second D flip-flop (D flip-flop 2) or the third D flip-flop (D flip-flop 3), and the fourth D flip-flop (D flip-flop 4) for the second step of sampling. The sampling signals are still the two differential signals PLL_outn and PLL_outp of the phase-locked loop. The purpose of this sampling step is to generate two control signals with a phase difference of 180°. There are two groups of control signals with a phase difference of 180°, namely the first switch sync_en_sel1 and the second switch sync_en_sel2, or the third switch sync_en_sel3 and the fourth switch sync_en_sel4. As before, only one of the two groups may be suitable. Assuming that sync_en_sel1 and sync_en_sel2 are more suitable, first arbitrarily select one of them to become Figure 1 If the "sync_en" signal in Figure 1 The PLL_outp / PLL_outn in the Figure 3 As shown), the switch selection circuit can select another signal as "sync_en", and this signal is in the most suitable position because the phase difference between sync_en_sel1 and sync_en_sel2 is exactly 180°.

[0080] The signal selection process can traverse the control signals output when the first switch (sync_en_sel1), the second switch (sync_en_sel2), the third switch (sync_en_sel3) and the fourth switch (sync_en_sel4) are connected separately, and the one without phase ambiguity is selected according to the test results. The determination can be made after a maximum of four selections.

[0081] The third RS flip-flop (RS flip-flop 3) and the third and fourth RS flip-flops (RS flip-flop 4) are used to ensure that the second step sampling of the first synchronization signal sync_en_int1 and the second synchronization signal sync_en_int2 does not cause timing issues. Due to the high operating frequency of the phase-locked loop, the delay of the first RS flip-flop (RS flip-flop 1) and the second RS flip-flop (RS flip-flop 2) may exceed half the cycle of the PLL_outp / PLL_outn signal. To prevent sampling errors, the RST_n signal input to the second D flip-flop (D flip-flop 2) and the fourth D flip-flop (D flip-flop 4) of the first RS flip-flop (RS flip-flop 1) and the second RS flip-flop (RS flip-flop 2) is blocked for a certain period of time. Sampling is not performed until sync_en_int1 and sync_en_int2 are stable.

[0082] Figure 8 and Figure 9 This is an example of signal selection when the switch selection unit finally selects the control signal sync_en transmitted to the clock generation circuit. Figure 8 An example of the first sampling step is shown. As can be seen from the figure, when sync_en is close to an edge of PLL_outp, if device delays vary between -40°C and 130°C, this can cause uncertainty in sync_en_int2, with a deviation greater than half a PLL clock cycle. However, at this point, sync_en is at its farthest from the sensitive edge of PLL_outn, and sync_en_int1 is very stable between -40°C and 130°C, with only a small deviation that does not affect the next sampling step.

[0083] Figure 9 An example of synchronization unit sampling is shown, taking the sampling of the first synchronization signal sync_en_int1 as an example. The delay of the D flip-flop and RS trigger is also shown in the figure. As can be seen from the figure, when sync_en_int1 is sampled by PLL_outn, the first switch sync_en_sel1 signal, after passing through the D flip-flop and routing delay, may encounter the sensitive edge of PLL_outp / PLL_outn at -40℃ to 130℃, causing phase ambiguity (the first switch sync_en_sel1 is located at a sensitive edge of PLL_outp / PLL_outn, see Figure 1 and Figure 3); The second switch sync_en_sel2 is sampled by PLL_outp, and its phase is 180° different from the first switch sync_en_sel1 (through the same D flip-flop and routing delay), which will be in the safest position and will not cause phase ambiguity even in -40℃ ~ 130℃ (the second switch sync_en_sel2 can avoid the sensitive edge of PLL_outp / PLL_outn). The subsequent selection switch selects the second switch sync_en_sel2 as Figure 1 The phase ambiguity problem is solved by using the "sync_en" signal in the delay unit. The function of the delay signal blk_p is the same as before, ensuring that PLL_outp can correctly sample sync_en_int1.

[0084] Apart from Figure 6 In the solution shown, D flip-flops can also be used for the first and second RS flip-flops, but their delay is longer, requiring attention to the subsequent sampling timing of sync_en_int1 and sync_en_int2. Furthermore, the circuit operates at high frequencies, requiring proper layout routing to ensure a 180° phase difference between sync_en_sel1 and 2, and between sync_en_sel3 and 4.

[0085] Figure 8 and Figure 9 This is just an example, actual situations may vary. In any case, when using Figure 6 When the scheme shown is used, the chip only needs to make four selections at most to select the most suitable configuration. This scheme can be used for both the local oscillator clock and the baseband clock to eliminate clock phase ambiguity, making the chip suitable for multi-chip synchronization applications.

[0086] In some optional embodiments, the clock generation circuit includes N trigger stage chains; wherein the first differential signal and the second differential signal are input into the clock generation circuit, and the first synchronization signal and the second synchronization signal are input into the previous stage trigger of the clock generation circuit.

[0087] In an optional embodiment, the first differential signal and the second differential signal are Q1 and Q2 respectively; the first synchronization signal and the second synchronization signal are Q1″ and Q2″ respectively; the N trigger-stage chain includes N+2 trigger stages; wherein the i-th trigger includes a first trigger T1(i) and a second trigger T2(i); the (N+2)-th trigger includes a third trigger T3(N+2) and a fourth trigger T4(N+2); the input end of the first trigger T1(i) is connected to the output end of the second trigger T2(i-1); the input end of the second trigger T2(i) is connected to the output end of the first trigger T1(i-1); the input end of the third trigger T3(N+2) is connected to the output end of the third trigger T3(N+2). The output end of the fourth trigger T4(N+2) is connected; the input end of the fourth trigger T4(N+2) is connected to the output end of the third trigger T3(N+2); the sampling signal of the first trigger T1(i) is the second differential signal; the sampling signal of the second trigger T2(i) is the first differential signal; the sampling signal of the third trigger T3(N+2) is the second differential signal; the sampling signal of the fourth trigger T4(N+2) is the first differential signal; the first differential signal and the second differential signal are input into the first trigger T1(1) and the second trigger T2(1); the first synchronization signal and the second synchronization signal are input into the third trigger T3(N+2) and the fourth trigger T4(N+2).

[0088] In an optional embodiment, the first differential signal and the second differential signal are Q1 and Q2 respectively; the first synchronization signal and the second synchronization signal are Q1″ and Q2″ respectively; the N trigger-stage chain includes N+2 trigger stages; wherein the i-th trigger includes a first trigger T1(i) and a second trigger T2(i); the (N+2)-th trigger includes a third trigger T3(N+2) and a fourth trigger T4(N+2); the input end of the first trigger T1(i) is connected to the output end of the second trigger T2(i-1); the input end of the second trigger T2(i) is connected to the output end of the first trigger T1(i-1); the input end of the third trigger T3(N+2) is connected to the output end of the third trigger T3(N+2). The output end of the fourth trigger T4(N+2) is connected; the input end of the fourth trigger T4(N+2) is connected to the output end of the third trigger T3(N+2); the sampling signal of the first trigger T1(i) is the second differential signal; the sampling signal of the second trigger T2(i) is the first differential signal; the sampling signal of the third trigger T3(N+2) is the second differential signal; the sampling signal of the fourth trigger T4(N+2) is the first differential signal; the first differential signal and the second differential signal are input into the first trigger T1(1) and the second trigger T2(1); the first synchronization signal and the second synchronization signal are input into the third trigger T3(N+2) and the fourth trigger T4(N+2).

[0089] In an optional embodiment, the first differential signal and the second differential signal are Q1 and Q2 respectively; the first synchronization signal and the second synchronization signal are Q1″ and Q2″ respectively; the N trigger-stage chain includes N+2 trigger stages; wherein the i-th trigger includes a first trigger T1(i) and a second trigger T2(i); the (N+2)-th trigger includes a third trigger T3(N+2) and a fourth trigger T4(N+2); the input end of the first trigger T1(i) is connected to the output end of the second trigger T2(i-1); the input end of the second trigger T2(i) is connected to the output end of the first trigger T1(i-1); the input end of the third trigger T3(N+2) is connected to the output end of the third trigger T3(N+2). The output end of the fourth trigger T4(N+2) is connected; the input end of the fourth trigger T4(N+2) is connected to the output end of the third trigger T3(N+2); the sampling signal of the first trigger T1(i) is the second differential signal; the sampling signal of the second trigger T2(i) is the first differential signal; the sampling signal of the third trigger T3(N+2) is the second differential signal; the sampling signal of the fourth trigger T4(N+2) is the first differential signal; the first differential signal and the second differential signal are input into the first trigger T1(1) and the second trigger T2(1); the first synchronization signal and the second synchronization signal are input into the third trigger T3(N+2) and the fourth trigger T4(N+2).

[0090] In summary, the embodiments of the present application provide a signal sampling and processing system and method for multi-chip synchronization: a first differential signal and a second differential signal are generated by a phase-locked loop and input into a clock generation circuit; a sampling unit synchronously samples the received signals of multiple transceiver chips; the sampling signal of the first synchronization signal is the first differential signal, and the sampling signal of another signal is the second differential signal; a delay unit delays the first synchronization signal and the second synchronization signal until the signals are stable, and the synchronization unit uses the first synchronization signal and the second synchronization signal to generate two control signals respectively; the phase difference between the two control signals is 180°; a switch selection unit selects the switch between any one control signal and the clock generation circuit to connect; if the four-phase local oscillator clock signal output by the clock generation circuit is phase ambiguous, another control signal is selected in sequence until the bit ambiguity is eliminated, thereby obtaining the control signal finally sent to the clock generation circuit. Thus, the phase ambiguity problem can be eliminated by performing a maximum of four selections. The present invention uses a phase-locked loop (PLL) to resynchronize the synchronization signals input by multiple chips. The signal enters a clock generation circuit, which outputs four synchronization signals. Signal selection is performed based on phase ambiguity, avoiding phase ambiguity caused by collisions with the edges of the signal sent by the PLL. The synchronization signal selected by the PLL is guaranteed to be sufficiently distant from the PLL's own signal edges, thus preventing phase ambiguity even with temperature fluctuations. This invention enables multi-chip synchronization, eliminates phase ambiguity, and ensures that the phase of the chip's local oscillator clock or baseband clock remains unchanged after each synchronization signal.

[0091] The external input synchronization signal is actually first sampled by the chip reference clock, which also serves as the reference clock for the phase-locked loop (PLL), so they have a certain timing relationship. However, due to the high frequency of the circuit, the local oscillator clock generation circuit cannot guarantee that the synchronization signal will not collide with the PLL's sensitive edge, causing phase ambiguity. The method described in this invention can avoid phase ambiguity.

[0092] The above specific implementation methods further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A signal sampling and processing system for multi-chip synchronization, applied to multiple transceiver chips, the processing system comprising: A phase-locked loop, configured to generate a first differential signal and a second differential signal; A clock generation circuit, configured to input the first differential signal and the second differential signal, wherein the processing system further comprises: a sampling unit, which synchronously samples the synchronization control signals of the plurality of transceiver chips to obtain a first synchronization signal and a second synchronization signal, wherein the sampling signal of the first synchronization signal is the first differential signal, and the sampling signal of the other signal is the second differential signal; a delay unit, configured to delay the first synchronization signal and the second synchronization signal so that the first differential signal is synchronized with the first synchronization signal, and the second differential signal is synchronized with the second synchronization signal; a synchronization unit, configured to generate two control signals based on the first synchronization signal and the second synchronization signal, respectively, wherein the two control signals have the same duty cycle and frequency and a phase difference of 180°; The switch selection unit selects any one of the control signals and sends it to the clock generation circuit. If the four-phase local oscillator clock signal output by the clock generation circuit is phase-ambiguous, another control signal is selected in turn and sent to the clock generation circuit until no phase ambiguity occurs.

2. The signal sampling and processing system for multi-chip synchronization according to claim 1, characterized in that: The sampling unit includes a first RS trigger and a second RS trigger; the first RS trigger and the second RS trigger respectively receive the synchronization control signals of multiple transceiver chips; the sampling signal of the first RS trigger is the first differential signal, and the sampling signal of the second RS trigger is the second differential signal.

3. The signal sampling and processing system for multi-chip synchronization according to claim 2, characterized in that: The sampling unit includes a fifth D flip-flop and a sixth D flip-flop; the fifth D flip-flop and the sixth D flip-flop respectively receive the synchronization control signals of multiple transceiver chips; the sampling signal of the fifth D flip-flop is the first differential signal, and the sampling signal of the sixth D flip-flop is the second differential signal.

4. A signal sampling and processing system for multi-chip synchronization according to claim 2 or 3, characterized in that: The delay unit includes a third RS trigger and a fourth RS trigger; the input end of the third RS trigger is connected to the output end of the first RS trigger; the input end of the fourth RS trigger is connected to the output end of the second RS trigger; the sampling signal of the third RS trigger is the second differential signal; The sampling signal of the fourth RS trigger is the first differential signal.

5. The signal sampling and processing system for multi-chip synchronization according to claim 4, characterized in that: The synchronization unit includes a first D flip-flop, a second D flip-flop, a third D flip-flop and a fourth D flip-flop; the input end of the second D flip-flop is connected to the output end of the first RS flip-flop; the first D flip-flop, the second D flip-flop and the third RS flip-flop are connected in parallel; the sampling signal of the first D flip-flop is the first differential signal; The sampling signal of the second D flip-flop is the second differential signal; the input end of the fourth D flip-flop is connected to the output end of the second RS flip-flop; the third D flip-flop, the fourth D flip-flop and the fourth RS flip-flop are connected in parallel; the sampling signal of the fourth D flip-flop is the first differential signal; the sampling signal of the third D flip-flop is the second differential signal.

6. The signal sampling and processing system for multi-chip synchronization according to claim 5, characterized in that: The switch selection unit includes a first switch, a second switch, a third switch and a fourth switch; the output end of the first D flip-flop is connected to the input end of the clock generation circuit through the first switch; the output end of the second D flip-flop is connected to the input end of the clock generation circuit through the second switch; the output end of the third D flip-flop is connected to the input end of the clock generation circuit through the third switch; and the output end of the fourth D flip-flop is connected to the input end of the clock generation circuit through the fourth switch.

7. The signal sampling and processing system for multi-chip synchronization according to claim 1, characterized in that: The phase-locked loop is a local oscillator phase-locked loop; The clock generating circuit is a local oscillator clock or a baseband clock generating circuit.

8. A signal sampling and processing method for multi-chip synchronization, applied to multiple transceiver chips; The processing method comprises: A phase-locked loop is configured to generate a first differential signal and a second differential signal; and a clock generation circuit is configured to input the first differential signal and the second differential signal. The processing method further comprises the following steps: Synchronously sampling received signals of multiple transceiver chips to obtain a first synchronization signal and a second synchronization signal; wherein the sampling signal of the first synchronization signal is the first differential signal, and the sampling signal of another signal is the second differential signal; delaying the first synchronization signal and the second synchronization signal so that the first differential signal is synchronized with the first synchronization signal and the second differential signal is synchronized with the second synchronization signal; generating two control signals based on the first synchronization signal and the second synchronization signal, respectively, wherein the two control signals have the same duty cycle and frequency and a phase difference of 180°; Any one of the control signals is selected and sent to the clock generating circuit. If the four-phase local oscillator clock signal output by the clock generating circuit is phase-ambiguous, another control signal is selected in turn and sent to the clock generating circuit until no phase ambiguity occurs.

9. The signal sampling and processing method for multi-chip synchronization according to claim 8, characterized in that: The synchronous sampling of the synchronization control signals of the plurality of transceiver chips to obtain the first synchronization signal and the second synchronization signal includes: respectively sampling the first synchronization signal and the second synchronization signal using an RS trigger or a D trigger; The delaying the first synchronization signal and the second synchronization signal includes: Using an RS trigger to block the first synchronization signal and the second synchronization signal; Generating two control signals based on the first synchronization signal and the second synchronization signal respectively includes: Two D flip-flops are respectively used to generate the first synchronization signal and the synchronization signal control signal; The selecting any one of the control signals to be sent to the clock generating circuit comprises: Different switches are used to control whether each of the control signals is sent to the clock generating circuit.

10. The signal sampling and processing method for multi-chip synchronization according to claim 8, characterized in that: The selecting any one of the control signals to be sent to the clock generating circuit comprises: Any one of the two control signals generated by the first synchronization signal and the two control signals generated based on the second synchronization signal is selected and sent to the clock generation circuit.

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