Post-processing device and method for chaotic key distribution

Abstract

The invention provides a post-processing device and method for chaotic key distribution. Comprising a driving source, a power supply module, a synchronous clock module, a first DFB laser, a second DFB laser, a first keying module, a second keying module, a first photoelectric detector, a second photoelectric detector, a first dual-threshold quantization module, a second dual-threshold quantization module, a first FPGA module and a second FPGA module. And screening of seed keys and coding and error correction functions of BCH codes are completed through the FPGA module, real-time performance and miniaturization of key distribution can be achieved, and it is guaranteed that the keys generated by the two communication parties are completely consistent. The post-processing device for chaotic key distribution is miniaturized, high in integration level and high in real-time performance, and can be applied to the field of post-processing of chaotic key distribution.

Description

Technical Field

[0001] The present invention relates to the field of secure communication, and more particularly, to a post-processing device and method for chaotic key distribution. Background Art

[0002] With the rapid development of information technology, information security issues have become the focus of global attention. Traditional cryptographic algorithms (such as RSA, ECC) rely on mathematical complexity as the basis of security, but the breakthrough of quantum computing technology makes these algorithms face the risk of being cracked. Therefore, researching new high-security information encryption and key distribution methods has become an important direction in the field of information security.

[0003] Chaotic key distribution is a secure key distribution technology based on the characteristics of chaotic signals. Due to its non-linearity, randomness, initial value sensitivity and other characteristics, chaotic signals have significant advantages in the field of secure communication. Through chaotic synchronization, the sender and the receiver can generate consistent chaotic signals, thus realizing high-security key distribution. This method avoids the security vulnerabilities of traditional key distribution and has higher complexity and anti-attack ability.

[0004] The chaotic lasers of both communication parties are driven by random light sources to achieve chaotic synchronization. At the same time, the phase of the keyed feedback light is between 0 or π. This process is random and independent. When the phases of the keying of both parties are the same, the lasers A and B output synchronized chaotic signals. Otherwise, the output signals have no correlation. The chaotic signals are collected by a high-speed real-time oscilloscope and processed offline by a computer to extract the consistent keys KA and KB of both parties. However, this offline processing method has the following problems:

[0005] 1. Lack of real-time performance: The signal needs to be collected and processed in the computer first, resulting in a large delay and being unsuitable for high-speed communication scenarios.

[0006] 2. Limited practicality: It depends on a high-speed real-time oscilloscope, the processing process is complex and the power consumption is high, which is not conducive to the miniaturization and integrated design of the device. Summary of the Invention

[0007] The present invention aims to overcome the above-mentioned defects of low real-time performance and complex processing process in the existing secure communication, and proposes a post-processing device and method for chaotic key distribution.

[0008] To solve the above technical problems, the technical solution of the present invention is as follows:

[0009] The present invention provides a post - processing device for chaotic key distribution, including a driving source, a power supply module, a synchronous clock module, a first DFB laser, a second DFB laser, a first keying module, a second keying module, a first photodetector, a second photodetector, a first dual - threshold quantization module, a second dual - threshold quantization module, a first FPGA module, and a second FPGA module;

[0010] The output end of the driving source is respectively connected to the input ends of the first DFB laser and the second DFB laser;

[0011] The output end of the first keying module is connected to the control end of the first DFB laser. The output end of the first DFB laser is connected to the input end of the first photodetector. The output end of the first photodetector is connected to the second input end of the first dual - threshold quantization module. The first and second output ends of the first dual - threshold quantization module are respectively and correspondingly connected to the first and second input ends of the first FPGA module;

[0012] The output end of the first keying module is also connected to the third input end of the first FPGA module;

[0013] The output end of the second keying module is connected to the control end of the second DFB laser. The output end of the second DFB laser is connected to the input end of the second photodetector. The output end of the second photodetector is connected to the second input end of the second dual - threshold quantization module. The first and second output ends of the second dual - threshold quantization module are respectively and correspondingly connected to the first and second input ends of the second FPGA module;

[0014] The output end of the second keying module is also connected to the third input end of the second FPGA module;

[0015] The first output end of the power supply module is connected to the third input end of the first dual - threshold quantization module. The second output end of the power supply module is connected to the first input end of the first dual - threshold quantization module. The third output end of the power supply module is connected to the third input end of the second dual - threshold quantization module. The fourth output end of the power supply module is connected to the first input end of the second dual - threshold quantization module;

[0016] The first and second output ends of the synchronous clock module are respectively and correspondingly connected to the first clock control end and the second clock control end of the first dual - threshold quantization module. The third and fourth output ends of the synchronous clock module are respectively and correspondingly connected to the first clock control end and the second clock control end of the second dual - threshold quantization module;

[0017] The first FPGA module and the second FPGA module are connected through a communication link.

[0018] Preferably, the first dual-threshold quantization module and the second dual-threshold quantization module have the same structure, and both include a first voltage comparator, a second voltage comparator, a first bias unit, a second bias unit, a first D flip-flop, and a second D flip-flop;

[0019] The first input terminal of the first voltage comparator serves as the first input terminal of the dual-threshold quantization module. The second input terminal of the first voltage comparator and the second input terminal of the second voltage comparator both serve as the second input terminal of the dual-threshold quantization module. The first input terminal of the second voltage comparator serves as the third input terminal of the dual-threshold quantization module;

[0020] The output terminal of the first voltage comparator is connected to the input terminal of the first bias unit. The output terminal of the first bias unit is connected to the input terminal of the first D flip-flop. The output terminal of the first D flip-flop serves as the first output terminal of the dual-threshold quantization module;

[0021] The output terminal of the second voltage comparator is connected to the input terminal of the second bias unit. The output terminal of the second bias unit is connected to the input terminal of the second D flip-flop. The output terminal of the second D flip-flop serves as the second output terminal of the dual-threshold quantization module;

[0022] The first clock control terminal of the first D flip-flop is connected to the first clock control terminal of the second D flip-flop. The first clock control terminal of the first D flip-flop serves as the first clock control terminal of the dual-threshold quantization module. The second clock control terminal of the first D flip-flop is connected to the second clock control terminal of the second D flip-flop. The second clock control terminal of the first D flip-flop serves as the second clock control terminal of the dual-threshold quantization module.

[0023] Preferably, the first FPGA module and the second FPGA module have the same structure, and both include a clock synchronization sub-module, a master clock sub-module, a key code screening sub-module, a BCH encoding and decoding sub-module, and a RAM sub-module;

[0024] The first and second input terminals of the clock synchronization sub-module serve as the first and second input terminals of the FPGA module. The output terminal of the clock synchronization sub-module is connected to the first input terminal of the key code screening sub-module. The output terminal of the key code screening sub-module is connected to the input terminal of the BCH encoding and decoding sub-module. The output terminal of the BCH encoding and decoding sub-module serves as the output terminal of the FPGA module;

[0025] The input terminal of the RAM sub-module serves as the third input terminal of the FPGA module. The output terminal of the RAM sub-module is connected to the second input terminal of the key code screening sub-module;

[0026] The master clock sub-module is connected to the clock synchronization sub-module.

[0027] The present invention also provides a post-processing method for chaotic key distribution, including the following steps:

[0028] S1: Use the first key control module and the second key control module to generate the first local key control code and the second local key control code respectively, correspondingly control the parameters of the first DFB laser and the second DFB laser, and use a driving source to drive the first DFB laser and the second DFB laser to generate the first chaotic signal and the second chaotic signal respectively;

[0029] Input the first local key control code and the second local key control code into the RAM sub-module of the first FPGA module and the RAM sub-module of the second FPGA module respectively;

[0030] Input the first chaotic signal and the second chaotic signal into the first photodetector and the second photodetector respectively, and convert them into the first analog electrical signal and the second analog electrical signal correspondingly;

[0031] S2: Input the first analog electrical signal and the second analog electrical signal into the first dual-threshold quantization module and the second dual-threshold quantization module respectively. The power supply module sets the upper and lower voltage thresholds respectively, and the synchronous clock module sets the clocks respectively, and outputs the corresponding dual-level signals;

[0032] S3: Input the dual-level signals of the first dual-threshold quantization module and the second dual-threshold quantization module into the clock synchronization sub-modules of the first FPGA module and the second FPGA module respectively, adjust the main clock sub-modules of the first FPGA module and the second FPGA module to be synchronized with the clock set by the synchronous clock module, and output the first local seed key and the second local seed key respectively;

[0033] The key control code screening sub-module of the first FPGA module obtains the first local key control code from the RAM sub-module of the first FPGA module, and sends the first local key control code to the key control code screening sub-module of the second FPGA module through a communication link. The key control code screening sub-module of the second FPGA module compares the received first local key control code with the second local key control code, and screens the second local seed key according to the comparison result to generate the second screened seed key;

[0034] The key control code screening sub-module of the second FPGA module obtains the second local key control code from the RAM sub-module of the second FPGA module, and sends the second local key control code to the key control code screening sub-module of the first FPGA module through a communication link. The key control code screening sub-module of the first FPGA module compares the received second local key control code with the first local key control code, and screens the first local seed key according to the comparison result to generate the first screened seed key;

[0035] S5: The BCH encoding and decoding sub-module of the first FPGA module encodes the filtered first local seed key to generate parity bits, and sends the parity bits to the BCH encoding and decoding sub-module of the second FPGA module. The BCH encoding and decoding sub-module of the second FPGA module corrects the parity bits according to the second filtered seed key to generate the same key as the first filtered seed key.

[0036] Preferably, in the step S1, the parameters of the DFB laser include power and phase.

[0037] Preferably, the phase is between 0 and pi. When the phases of the first DFB laser and the second DFB laser are the same, the first DFB laser and the second DFB laser output synchronized chaotic signals; otherwise, uncorrelated chaotic signals are output.

[0038] Preferably, the step S2 includes:

[0039] The first analog electrical signal is respectively input into the first voltage comparator and the second voltage comparator of the first dual-threshold quantization module. The first voltage comparator of the first dual-threshold quantization module sets the upper voltage threshold according to the upper and lower voltage thresholds set by the power supply module, and the second voltage comparator of the first dual-threshold quantization module sets the lower voltage threshold according to the upper and lower voltage thresholds set by the power supply module. When the first analog electrical signal is higher than the upper voltage threshold of the first voltage comparator of the first dual-threshold quantization module, both the first voltage comparator and the second voltage comparator of the first dual-threshold quantization module output high levels; when the first analog electrical signal is lower than the lower voltage threshold of the second voltage comparator of the first dual-threshold quantization module, both the first voltage comparator and the second voltage comparator of the first dual-threshold quantization module output low levels; when the first analog electrical signal is between the upper voltage threshold of the first voltage comparator and the lower voltage threshold of the second voltage comparator of the first dual-threshold quantization module, the first voltage comparator of the first dual-threshold quantization module outputs a low level, and the second voltage comparator of the first dual-threshold quantization module outputs a high level;

[0040] The second analog electrical signal is respectively input into the first voltage comparator and the second voltage comparator of the second dual-threshold quantization module. The first voltage comparator of the second dual-threshold quantization module sets the upper voltage threshold according to the upper and lower voltage thresholds set by the power supply module, and the second voltage comparator of the second dual-threshold quantization module sets the lower voltage threshold according to the upper and lower voltage thresholds set by the power supply module. When the second analog electrical signal is higher than the upper voltage threshold of the first voltage comparator of the second dual-threshold quantization module, both the first voltage comparator and the second voltage comparator of the second dual-threshold quantization module output a high level; when the second analog electrical signal is lower than the lower voltage threshold of the second voltage comparator of the second dual-threshold quantization module, both the first voltage comparator and the second voltage comparator of the second dual-threshold quantization module output a low level; when the second analog electrical signal is between the upper voltage threshold of the first voltage comparator of the first dual-threshold quantization module and the lower voltage threshold of the second voltage comparator of the second dual-threshold quantization module, the first voltage comparator of the second dual-threshold quantization module outputs a low level, and the second voltage comparator of the second dual-threshold quantization module outputs a high level.

[0041] Preferably, in the step S3, the clock synchronization of the master clock sub-module of the first FPGA module, the master clock sub-module of the second FPGA module with the synchronization clock module includes:

[0042] Using the clock synchronization sub-module of the first FPGA module, align the dual-level signal of the first dual-threshold quantization module with the master clock of the master clock sub-module of the first FPGA module, and generate a synchronization clock matching the first dual-threshold quantization module through the phase-locked loop of the first FPGA module;

[0043] Using the clock synchronization sub-module of the second FPGA module, align the dual-level signal of the second dual-threshold quantization module with the master clock of the master clock sub-module of the second FPGA module, and generate a synchronization clock matching the second dual-threshold quantization module through the phase-locked loop of the second FPGA module.

[0044] Preferably, the step S5 includes:

[0045] Use the BCH encoding and decoding sub-module of the first FPGA module to encode the first screened seed key to generate parity bits, generate parity bits, and send the parity bits to the BCH encoding and decoding sub-module of the second FPGA module through the communication link;

[0046] The BCH encoding and decoding sub-module of the second FPGA module combines the received parity bits with the second local seed key, uses the BCH decoding algorithm to generate an error location sequence, and performs an exclusive OR operation with the second screened seed key to generate the same key as the first screened seed key.

[0047] The present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned method are implemented.

[0048] Compared with the prior art, the beneficial effects of the technical solution of the present invention are as follows:

[0049] The present invention provides a post-processing device and method for chaotic key distribution. The post-processing process of chaotic key distribution is completed by using a dual-threshold quantization module and an FPGA module, replacing the traditional offline processing process, which can significantly improve the processing speed and meet the requirements of high-speed communication. Through hardware integration, the device proposed by the present invention can reduce equipment dependence and power consumption, realize the miniaturization and high reliability of the device, and provide a real-time and miniaturized solution for the field of secure communication. Description of the Drawings

[0050] Figure 1 It is a schematic structural diagram of a post-processing device for chaotic key distribution described in Embodiment 1. Detailed Embodiments

[0051] The drawings are only for illustrative purposes and should not be construed as a limitation of this patent;

[0052] To better illustrate this embodiment, some components in the drawings are omitted, enlarged or reduced, and do not represent the size of the actual product;

[0053] For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0054] The technical solution of the present invention will be further described below with reference to the drawings and embodiments.

[0055] Embodiment 1

[0056] This embodiment provides a post-processing device for chaotic key distribution, as Figure 1 shown, including a drive source (1), a power supply module (5), a synchronous clock module (6), a first DFB laser (2a), a second DFB laser (2b), a first keying module (3a), a second keying module (3b), a first photodetector (4a), a second photodetector (4b), a first dual-threshold quantization module, a second dual-threshold quantization module, a first FPGA module, and a second FPGA module;

[0057] The output end of the drive source (1) is respectively connected to the input ends of the first DFB laser (2a) and the second DFB laser (2b);

[0058] The output terminal of the first keying module (3a) is connected to the control terminal of the first DFB laser (2a). The output terminal of the first DFB laser (2a) is connected to the input terminal of the first photodetector (4a). The output terminal of the first photodetector (4a) is connected to the second input terminal of the first dual-threshold quantization module. The first and second output terminals of the first dual-threshold quantization module are respectively and correspondingly connected to the first and second input terminals of the first FPGA module;

[0059] The output terminal of the first keying module (3a) is also connected to the third input terminal of the first FPGA module;

[0060] The output terminal of the second keying module (3b) is connected to the control terminal of the second DFB laser (2b). The output terminal of the second DFB laser (2b) is connected to the input terminal of the second photodetector (4b). The output terminal of the second photodetector (4b) is connected to the second input terminal of the second dual-threshold quantization module. The first and second output terminals of the second dual-threshold quantization module are respectively and correspondingly connected to the first and second input terminals of the second FPGA module;

[0061] The output terminal of the second keying module (3b) is also connected to the third input terminal of the second FPGA module;

[0062] The first output terminal of the power supply module (5) is connected to the third input terminal of the first dual-threshold quantization module. The second output terminal of the power supply module (5) is connected to the first input terminal of the first dual-threshold quantization module. The third output terminal of the power supply module (5) is connected to the third input terminal of the second dual-threshold quantization module. The fourth output terminal of the power supply module (5) is connected to the first input terminal of the second dual-threshold quantization module;

[0063] The first and second output terminals of the synchronous clock module (6) are respectively and correspondingly connected to the first clock control terminal and the second clock control terminal of the first dual-threshold quantization module. The third and fourth output terminals of the synchronous clock module (6) are respectively and correspondingly connected to the first clock control terminal and the second clock control terminal of the second dual-threshold quantization module;

[0064] The first FPGA module and the second FPGA module are connected through a communication link.

[0065] The first dual-threshold quantization module and the second dual-threshold quantization module have the same structure, and both include a first voltage comparator, a second voltage comparator, a first bias unit, a second bias unit, a first D flip-flop, and a second D flip-flop;

[0066] The first dual-threshold quantization module includes a first voltage comparator (7a), a second voltage comparator (7b), a first bias unit (8a), a second bias unit (8b), a first D flip-flop (9a), and a second D flip-flop (9b) of the first dual-threshold quantization module;

[0067] The second dual-threshold quantization module includes a first voltage comparator (7c), a second voltage comparator (7d), a first biasing unit (8c), a second biasing unit (8d), a first D flip-flop (9c), and a second D flip-flop (9d) of the second dual-threshold quantization module;

[0068] The first input terminal of the first voltage comparator serves as the first input terminal of the dual-threshold quantization module. The second input terminals of both the first voltage comparator and the second voltage comparator serve as the second input terminal of the dual-threshold quantization module. The first input terminal of the second voltage comparator serves as the third input terminal of the dual-threshold quantization module;

[0069] The output terminal of the first voltage comparator is connected to the input terminal of the first biasing unit. The output terminal of the first biasing unit is connected to the input terminal of the first D flip-flop. The output terminal of the first D flip-flop serves as the first output terminal of the dual-threshold quantization module;

[0070] The output terminal of the second voltage comparator is connected to the input terminal of the second biasing unit. The output terminal of the second biasing unit is connected to the input terminal of the second D flip-flop. The output terminal of the second D flip-flop serves as the second output terminal of the dual-threshold quantization module;

[0071] The first clock control terminal of the first D flip-flop is connected to the first clock control terminal of the second D flip-flop. The first clock control terminal of the first D flip-flop serves as the first clock control terminal of the dual-threshold quantization module. The second clock control terminal of the first D flip-flop is connected to the second clock control terminal of the second D flip-flop. The second clock control terminal of the first D flip-flop serves as the second clock control terminal of the dual-threshold quantization module.

[0072] The first FPGA module and the second FPGA module have the same structure and both include a clock synchronization sub-module, a main clock sub-module, a key code screening sub-module, a BCH encoding / decoding sub-module, and a RAM sub-module;

[0073] The first FPGA module includes a clock synchronization sub-module (10a), a main clock sub-module (11a), a key code screening sub-module (12a), a BCH encoding / decoding sub-module (13a), and a RAM sub-module (14a) of the first FPGA module.

[0074] The second FPGA module includes a clock synchronization sub-module (10b), a main clock sub-module (11b), a key code screening sub-module (12b), a BCH encoding / decoding sub-module (13b), and a RAM sub-module (14b) of the second FPGA module.

[0075] The first and second input terminals of the clock synchronization sub-module serve as the first and second input terminals of the FPGA module. The output terminal of the clock synchronization sub-module is connected to the first input terminal of the key code screening sub-module. The output terminal of the key code screening sub-module is connected to the input terminal of the BCH encoding and decoding sub-module. The output terminal of the BCH encoding and decoding sub-module serves as the output terminal of the FPGA module;

[0076] The input terminal of the RAM sub-module serves as the third input terminal of the FPGA module. The output terminal of the RAM sub-module is connected to the second input terminal of the key code screening sub-module;

[0077] The master clock sub-module is connected to the clock synchronization sub-module.

[0078] In this embodiment, a dual-threshold quantization module and an FPGA module are used to complete the post-processing of chaotic key distribution, replacing the traditional offline processing process. Since the FPGA module can achieve synchronous processing and signal screening, the dual-level signal output by the dual-threshold quantization is input to the FPGA for real-time processing, which can significantly improve the processing speed and meet the requirements of high-speed communication. Through hardware integration, the device proposed in this embodiment can reduce equipment dependence and power consumption, realize the miniaturization and high reliability of the device, and realize the transformation of the post-processing system of chaotic key distribution from offline processing to real-time processing, providing a real-time and miniaturized solution for the field of secure communication.

[0079] Embodiment 2

[0080] Based on Embodiment 1, this embodiment proposes a post-processing method for chaotic key distribution, including the following steps:

[0081] S1: Use the first key control module and the second key control module to generate the first local key code and the second local key code respectively, control the parameters of the first DFB laser and the second DFB laser respectively, and use the drive source to drive the first DFB laser and the second DFB laser to generate the first chaotic signal and the second chaotic signal respectively;

[0082] Input the first local key code and the second local key code into the RAM sub-module of the first FPGA module and the RAM sub-module of the second FPGA module respectively;

[0083] Input the first chaotic signal and the second chaotic signal into the first photodetector and the second photodetector respectively, and convert them into the first analog electrical signal and the second analog electrical signal respectively;

[0084] S2: Input the first analog electrical signal and the second analog electrical signal into the first dual-threshold quantization module and the second dual-threshold quantization module respectively. The power supply module sets the upper and lower voltage thresholds respectively, and the synchronous clock module sets the clocks respectively, and outputs the corresponding dual-level signals;

[0085] S3: Input the dual-level signals of the first dual-threshold quantization module and the second dual-threshold quantization module into the clock synchronization sub-modules of the first FPGA module and the second FPGA module respectively, adjust the clock synchronization of the main clock sub-modules of the first FPGA module and the second FPGA module with the clock set by the synchronization clock module, and output the first local seed key and the second local seed key respectively;

[0086] S4: The key code screening sub-module of the first FPGA module obtains the first local key code from the RAM sub-module of the first FPGA module, and sends the first local key code to the key code screening sub-module of the second FPGA module through the communication link. The key code screening sub-module of the second FPGA module compares the received first local key code with the second local key code, and screens the second local seed key according to the comparison result to generate the second screened seed key;

[0087] The key code screening sub-module of the second FPGA module obtains the second local key code from the RAM sub-module of the second FPGA module, and sends the second local key code to the key code screening sub-module of the first FPGA module through the communication link. The key code screening sub-module of the first FPGA module compares the received second local key code with the first local key code, and screens the first local seed key according to the comparison result to generate the first screened seed key;

[0088] The comparison logic of the key code is implemented based on hardware, and the screening speed is improved through parallel processing. The screened seed key is stored in the internal register of the FPGA, and can also be stored in an external memory (such as RAM) as the input for subsequent error correction and negotiation. The high parallel computing ability of the FPGA module significantly improves the efficiency of signal screening and key generation, meeting the real-time requirements.

[0089] S5: The BCH encoding and decoding sub-module of the first FPGA module encodes the screened first local seed key to generate parity bits, and sends the parity bits to the BCH encoding and decoding sub-module of the second FPGA module. The BCH encoding and decoding sub-module of the second FPGA module performs error correction processing on the parity bits according to the second screened seed key to generate the same key as the first screened seed key.

[0090] In the specific implementation process, a driving source (such as a superluminescent diode SLD) is used to generate broadband optical noise, and then the power and phase of the laser are adjusted through an injection control and keying module to achieve chaotic synchronization or asynchronous state. The chaotic synchronization signal is detected by a photodetector and converted into an analog electrical signal for subsequent quantization processing. In this embodiment, the quantization of the chaotic signal is realized through a dual-threshold quantization module, and the screening of the seed key and the encoding and error correction functions of the BCH code are completed through the FPGA module, realizing the real-time performance and miniaturization of key distribution.

[0091] Embodiment 3

[0092] This embodiment further defines steps S1 - S5 on the basis of Embodiment 2, including:

[0093] In step S1, the parameters of the DFB laser include power and phase.

[0094] The phase is between 0 and pi. When the phases of the first DFB laser and the second DFB laser are the same, the first DFB laser and the second DFB laser output synchronized chaotic signals; otherwise, they output uncorrelated chaotic signals.

[0095] Step S2 includes:

[0096] The first analog electrical signal is respectively input into the first voltage comparator and the second voltage comparator of the first dual-threshold quantization module. The first voltage comparator of the first dual-threshold quantization module sets the upper voltage threshold according to the upper and lower voltage thresholds set by the power supply module, and the second voltage comparator of the first dual-threshold quantization module sets the lower voltage threshold according to the upper and lower voltage thresholds set by the power supply module. When the first analog electrical signal is higher than the upper voltage threshold of the first voltage comparator of the first dual-threshold quantization module, both the first voltage comparator and the second voltage comparator of the first dual-threshold quantization module output high levels; when the first analog electrical signal is lower than the lower voltage threshold of the second voltage comparator of the first dual-threshold quantization module, both the first voltage comparator and the second voltage comparator of the first dual-threshold quantization module output low levels; when the first analog electrical signal is between the upper voltage threshold of the first voltage comparator of the first dual-threshold quantization module and the lower voltage threshold of the second voltage comparator of the first dual-threshold quantization module, the first voltage comparator of the first dual-threshold quantization module outputs a low level, and the second voltage comparator of the first dual-threshold quantization module outputs a high level;

[0097] The second analog electrical signal is respectively input into the first voltage comparator and the second voltage comparator of the second dual-threshold quantization module. The first voltage comparator of the second dual-threshold quantization module sets the upper voltage threshold according to the upper and lower voltage thresholds set by the power supply module, and the second voltage comparator of the second dual-threshold quantization module sets the lower voltage threshold according to the upper and lower voltage thresholds set by the power supply module. When the second analog electrical signal is higher than the upper voltage threshold of the first voltage comparator of the second dual-threshold quantization module, both the first voltage comparator of the second dual-threshold quantization module and the second voltage comparator of the second dual-threshold quantization module output a high level; when the second analog electrical signal is lower than the lower voltage threshold of the second voltage comparator of the second dual-threshold quantization module, both the first voltage comparator of the second dual-threshold quantization module and the second voltage comparator of the second dual-threshold quantization module output a low level; when the second analog electrical signal is between the upper voltage threshold of the first voltage comparator of the first dual-threshold quantization module and the lower voltage threshold of the second voltage comparator of the second dual-threshold quantization module, the first voltage comparator of the second dual-threshold quantization module outputs a low level, and the second voltage comparator of the second dual-threshold quantization module outputs a high level.

[0098] In the step S3, the clock synchronization of the master clock sub-module of the first FPGA module, the master clock sub-module of the second FPGA module with the synchronization clock module includes:

[0099] Using the clock synchronization sub-module of the first FPGA module, align the dual-level signal of the first dual-threshold quantization module with the master clock of the master clock sub-module of the first FPGA module, and generate a synchronization clock matching the first dual-threshold quantization module through the phase-locked loop of the first FPGA module;

[0100] Using the clock synchronization sub-module of the second FPGA module, align the dual-level signal of the second dual-threshold quantization module with the master clock of the master clock sub-module of the second FPGA module, and generate a synchronization clock matching the second dual-threshold quantization module through the phase-locked loop of the second FPGA module, ensuring the clock synchronization between the first dual-threshold quantization module, the second dual-threshold quantization module and the FPGA module, avoiding the delay caused by inconsistent clocks, so as to meet the real-time requirements.

[0101] The step S5 includes:

[0102] Use the BCH encoding and decoding sub-module of the first FPGA module to encode the first screened seed key to generate parity bits, generate parity bits, and send the parity bits to the BCH encoding and decoding sub-module of the second FPGA module through the communication link;

[0103] The BCH encoding and decoding sub-module of the second FPGA module combines the received parity bits with the second local seed key, generates an error location sequence using the BCH decoding algorithm, and performs an exclusive OR operation with the second screening seed key to generate the same key as the first screening seed key.

[0104] This embodiment provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0105] In the specific implementation process, the signal output by the voltage comparator may not meet the level requirements of the subsequent circuit. The level range is adjusted by a biaser to ensure that the signal meets the input voltage requirements of the D flip-flop. Under the action of the differential clock signal, the D flip-flop shapes the adjusted signal to generate a two-level signal (the high level and the low level respectively correspond to 1 and 0 of the digital signal). To ensure that the synchronization and output of the flip-flop do not cause excessive delay, a low-delay synchronization mechanism is used to ensure that the two-level signal can be quickly transmitted to the FPGA module for real-time processing.

[0106] This embodiment uses an FPGA module. The high parallel computing ability of the FPGA module significantly improves the efficiency of signal screening and key generation, meeting the real-time requirements.

[0107] This embodiment uses a BCH encoding and decoding sub-module, which not only reduces the bit error rate in the key distribution process, but also improves the error correction efficiency through hardware implementation, enhancing the practicability of the key distribution device.

[0108] Compared with the prior art, the method proposed in this embodiment has the following beneficial effects:

[0109] 1. High-efficiency error correction: The hardware implementation based on the BCH code provides real-time error correction ability, reducing the impact of bit errors on key consistency.

[0110] 2. Strong real-time performance: The parallel processing logic of the FPGA module ensures the high-speed operation of signal screening and key generation, meeting the requirements of high-speed communication.

[0111] 3. Miniaturized design: The device proposed in this embodiment has a high integration level and can be widely applied in embedded and portable devices, adapting to low-power scenarios.

[0112] The same or similar reference numerals correspond to the same or similar components;

[0113] The terms describing the positional relationship in the drawings are only for illustrative purposes and should not be construed as a limitation of this patent;

[0114] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, rather than limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the claims of the present invention.

Claims

1. A post-processing device for chaotic key distribution, characterized in that: It includes a driving source, a power module, a synchronous clock module, a first DFB laser, a second DFB laser, a first keying module, a second keying module, a first photodetector, a second photodetector, a first dual-threshold quantization module, a second dual-threshold quantization module, a first FPGA module, and a second FPGA module; The output end of the driving source is connected to the input end of the first DFB laser and the input end of the second DFB laser respectively; The output end of the first keying module is connected to the control end of the first DFB laser, the output end of the first DFB laser is connected to the input end of the first photodetector, the output end of the first photodetector is connected to the second input end of the first dual-threshold quantization module, and the first and second output ends of the first dual-threshold quantization module are respectively connected to the first and second input ends of the first FPGA module; The output terminal of the first key control module is also connected to the third input terminal of the first FPGA module; The output end of the second keying module is connected to the control end of the second DFB laser, the output end of the second DFB laser is connected to the input end of the second photodetector, the output end of the second photodetector is connected to the second input end of the second dual-threshold quantization module, and the first and second output ends of the second dual-threshold quantization module are respectively connected to the first and second input ends of the second FPGA module; The output terminal of the second keying module is also connected to the third input terminal of the second FPGA module; The first output end of the power module is connected to the third input end of the first dual-threshold quantization module, the second output end of the power module is connected to the first input end of the first dual-threshold quantization module, the third output end of the power module is connected to the third input end of the second dual-threshold quantization module, and the fourth output end of the power module is connected to the first input end of the second dual-threshold quantization module; The first and second output terminals of the synchronous clock module are respectively connected to the first clock control terminal and the second clock control terminal of the first dual-threshold quantization module, and the third and fourth output terminals of the synchronous clock module are respectively connected to the first clock control terminal and the second clock control terminal of the second dual-threshold quantization module; The first FPGA module is connected to the second FPGA module via a communication link.

2. A post-processing device for chaotic key distribution according to claim 1, characterized in that: The first dual-threshold quantization module and the second dual-threshold quantization module have the same structure, and both include a first voltage comparator, a second voltage comparator, a first bias device, a second bias device, a first D flip-flop, and a second D flip-flop; The first input end of the first voltage comparator is used as the first input end of the dual-threshold quantization module, the second input end of the first voltage comparator and the second input end of the second voltage comparator are both used as the second input end of the dual-threshold quantization module, and the first input end of the second voltage comparator is used as the third input end of the dual-threshold quantization module; The output end of the first voltage comparator is connected to the input end of the first bias device, the output end of the first bias device is connected to the input end of the first D flip-flop, and the output end of the first D flip-flop serves as the first output end of the dual threshold quantization module; The output end of the second voltage comparator is connected to the input end of the second biaser, the output end of the second biaser is connected to the input end of the second D flip-flop, and the output end of the second D flip-flop serves as the second output end of the dual threshold quantization module; The first clock control end of the first D flip-flop is connected to the first clock control end of the second D flip-flop, and the first clock control end of the first D flip-flop serves as the first clock control end of the dual threshold quantization module. The second clock control end of the first D flip-flop is connected to the second clock control end of the second D flip-flop, and the second clock control end of the first D flip-flop serves as the second clock control end of the dual threshold quantization module.

3. A post-processing device for chaotic key distribution according to claim 2, characterized in that: The first FPGA module and the second FPGA module have the same structure, and both include a clock synchronization submodule, a master clock submodule, a key code screening submodule, a BCH encoding and decoding submodule, and a RAM submodule; The first and second input terminals of the clock synchronization submodule serve as the first and second input terminals of the FPGA module, the output terminal of the clock synchronization submodule is connected to the first input terminal of the key code screening submodule, the output terminal of the key code screening submodule is connected to the input terminal of the BCH encoding and decoding submodule, and the output terminal of the BCH encoding and decoding submodule serves as the output terminal of the FPGA module; The input end of the RAM submodule serves as the third input end of the FPGA module, and the output end of the RAM submodule is connected to the second input end of the key code screening submodule; The main clock submodule is connected to the clock synchronization submodule.

4. A post-processing method for chaotic key distribution, characterized in that: The method is implemented based on the device described in claims 1-3. The following steps are involved: S1: using the first keying module and the second keying module to generate the first local keying code and the second local keying code respectively, correspondingly controlling the parameters of the first DFB laser and the second DFB laser, and using the driving source to drive the first DFB laser and the second DFB laser to generate the first chaotic signal and the second chaotic signal respectively; Inputting the first local keying code and the second local keying code into the RAM submodule of the first FPGA module and the RAM submodule of the second FPGA module respectively; Inputting the first chaotic signal and the second chaotic signal into the first photodetector and the second photodetector respectively, and converting them into the first analog electrical signal and the second analog electrical signal respectively; S2: inputting the first analog electrical signal and the second analog electrical signal into the first dual-threshold quantization module and the second dual-threshold quantization module respectively, setting the upper and lower voltage thresholds respectively for the power supply module, setting the clock respectively for the synchronous clock module, and outputting the corresponding dual-level signal; S3: Inputting the bi-level signals of the first dual-threshold quantization module and the second dual-threshold quantization module into the clock synchronization submodules of the first FPGA module and the second FPGA module respectively, adjusting the master clock submodule of the first FPGA module and the master clock submodule of the second FPGA module to synchronize with the clock set by the synchronization clock module, and outputting the first local seed key and the second local seed key respectively; S4: The key code screening submodule of the first FPGA module obtains the first local key code from the RAM submodule of the first FPGA module, and sends the first local key code to the key code screening submodule of the second FPGA module through the communication link. The key code screening submodule of the second FPGA module compares the received first local key code with the second local key code, and screens the second local seed key according to the comparison result to generate a second screened seed key. The key code screening submodule of the second FPGA module obtains the second local key code from the RAM submodule of the second FPGA module, and sends the second local key code to the key code screening submodule of the first FPGA module through the communication link. The key code screening submodule of the first FPGA module compares the received second local key code with the first local key code, and screens the first local seed key according to the comparison result to generate a first screened seed key. S5: The BCH encoding and decoding submodule of the first FPGA module encodes the screened first local seed key to generate a parity check bit, and sends the parity check bit to the BCH encoding and decoding submodule of the second FPGA module. The BCH encoding and decoding submodule of the second FPGA module performs error correction on the parity check bit according to the second screening seed key to generate a key identical to the first screening seed key.

5. A post-processing method for chaotic key distribution according to claim 4, characterized in that: In the step S1, the parameters of the DFB laser include power and phase.

6. A post-processing method for chaotic key distribution according to claim 5, characterized in that: The phase is between 0 and pi. When the phases of the first DFB laser and the second DFB laser are the same, the first DFB laser and the second DFB laser output synchronized chaotic signals. Otherwise, they output irrelevant chaotic signals.

7. A post-processing method for chaotic key distribution according to claim 6, characterized in that: The step S2 comprises: The first analog electrical signal is input into the first voltage comparator and the second voltage comparator of the first dual-threshold quantization module respectively. The first voltage comparator of the first dual-threshold quantization module sets an upper voltage threshold according to the upper and lower voltage thresholds set by the power module, and the second voltage comparator of the first dual-threshold quantization module sets a lower voltage threshold according to the upper and lower voltage thresholds set by the power module. When the first analog electrical signal is higher than the upper voltage threshold of the first voltage comparator of the first dual-threshold quantization module, the first voltage comparator of the first dual-threshold quantization module and the second voltage comparator of the first dual-threshold quantization module both output a high level; when the first analog electrical signal is lower than the lower voltage threshold of the second voltage comparator of the first dual-threshold quantization module, the first voltage comparator of the first dual-threshold quantization module and the second voltage comparator of the first dual-threshold quantization module both output a low level; when the first analog electrical signal is between the upper voltage threshold of the first voltage comparator of the first dual-threshold quantization module and the lower voltage threshold of the second voltage comparator of the first dual-threshold quantization module, the first voltage comparator of the first dual-threshold quantization module outputs a low level, and the second voltage comparator of the first dual-threshold quantization module outputs a high level; The second analog electrical signal is input into the first voltage comparator and the second voltage comparator of the second dual-threshold quantization module respectively. The first voltage comparator of the second dual-threshold quantization module sets an upper voltage threshold according to the upper and lower voltage thresholds set by the power module, and the second voltage comparator of the second dual-threshold quantization module sets a lower voltage threshold according to the upper and lower voltage thresholds set by the power module. When the second analog electrical signal is higher than the upper voltage threshold of the first voltage comparator of the second dual-threshold quantization module, the first voltage comparator of the second dual-threshold quantization module and the second voltage comparator of the second dual-threshold quantization module both output a high level; when the second analog electrical signal is lower than the lower voltage threshold of the second voltage comparator of the second dual-threshold quantization module, the first voltage comparator of the second dual-threshold quantization module and the second voltage comparator of the second dual-threshold quantization module both output a low level; when the second analog electrical signal is between the upper voltage threshold of the first voltage comparator of the first dual-threshold quantization module and the lower voltage threshold of the second voltage comparator of the second dual-threshold quantization module, the first voltage comparator of the second dual-threshold quantization module outputs a low level, and the second voltage comparator of the second dual-threshold quantization module outputs a high level.

8. A post-processing method for chaotic key distribution according to claim 7, characterized in that: In step S3, adjusting the clock synchronization between the master clock submodule of the first FPGA module, the master clock submodule of the second FPGA module and the clock set by the synchronization clock module includes: Using the clock synchronization submodule of the first FPGA module, align the bi-level signal of the first dual-threshold quantization module with the master clock of the master clock submodule of the first FPGA module, and generate a synchronous clock matching the first dual-threshold quantization module through the phase-locked loop of the first FPGA module; The clock synchronization submodule of the second FPGA module is used to align the dual-level signal of the second dual-threshold quantization module with the master clock of the master clock submodule of the second FPGA module, and a synchronous clock matching the second dual-threshold quantization module is generated through the phase-locked loop of the second FPGA module.

9. A post-processing method for chaotic key distribution according to claim 8, characterized in that: The step S5 comprises: Using the BCH encoding and decoding submodule of the first FPGA module to encode the first screening seed key to generate a parity check bit, generating the parity check bit, and sending the parity check bit to the BCH encoding and decoding submodule of the second FPGA module through a communication link; The BCH encoding and decoding submodule of the second FPGA module combines the received parity bit with the second local seed key, generates an error locating sequence using the BCH decoding algorithm, and performs an XOR operation with the second screening seed key to generate a key identical to the first screening seed key.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 4 to 9 are implemented.

Images