A post-processing device and method for chaotic key distribution

Abstract

The application provides a post-processing device and method for chaotic key distribution, which comprises a driving source, a power module, a synchronous clock module, a first DFB laser, a second DFB laser, a first key control module, a second key control module, a first photoelectric detector, a second photoelectric detector, a first double-threshold quantization module, a second double-threshold quantization module, a first FPGA module and a second FPGA module. The double-threshold quantization module is used for quantizing chaotic signals, and the FPGA module is used for screening seed keys and encoding and error correction of BCH codes, so that the real-time performance and miniaturization of key distribution can be realized, and the keys generated by the two communication parties are completely consistent. The application realizes the miniaturization and high integration of the post-processing device for chaotic key distribution, has strong real-time performance, and can be applied to the field of post-processing of chaotic key distribution.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of secure communication, and more particularly, to a post-processing device and method for chaotic key distribution. BACKGROUND

[0002] With the rapid development of information technology, information security has become a global focus. Traditional cryptography algorithms (such as RSA, ECC) rely on mathematical complexity as the basis for security, but the breakthrough of quantum computing technology makes these algorithms face the risk of being cracked. Therefore, researching new high-security information encryption and key distribution methods has become an important direction in the field of information security.

[0003] Chaotic key distribution is a secure key distribution technology based on the characteristics of chaotic signals. Chaotic signals have significant advantages in secure communication due to their nonlinearity, randomness, and initial value sensitivity. Through chaotic synchronization, the sender and receiver can generate consistent chaotic signals, thereby achieving high-security key distribution. This method avoids the security vulnerabilities of traditional key distribution and has higher complexity and attack resistance.

[0004] The chaotic lasers of both communication parties are driven by random light sources to achieve chaotic synchronization, and the phase of the key-controlled feedback light is between 0 and π. This process is random and independent. When the key-controlled phases of both parties are the same, the lasers A and B output synchronized chaotic signals. Otherwise, the output signals have no correlation. Chaotic signals are collected by a high-speed real-time oscilloscope and quantitatively processed offline by a computer to extract consistent keys KA and KB. However, this offline processing method has the following problems:

[0005] 1. Lack of real-time performance: The signal needs to be collected into the computer for processing, resulting in large delay, which is not suitable for high-speed communication scenarios.

[0006] 2. Limited practicality: It relies on a high-speed real-time oscilloscope, and the processing process is complex and power-consuming, which is not conducive to the miniaturization and integration design of the device. SUMMARY

[0007] To overcome the above-mentioned defects of low real-time performance and complex processing process in existing secure communication, a post-processing device and method for chaotic key distribution are proposed.

[0008] To solve the above technical problems, the technical solutions of the present application are as follows:

[0009] The application provides a post-processing device for chaotic key distribution, which comprises a driving source, a power module, a synchronous clock module, a first DFB laser, a second DFB laser, a first key control module, a second key control module, a first photoelectric detector, a second photoelectric detector, a first double-threshold quantization module, a second double-threshold quantization module, a first FPGA module and a second FPGA module.

[0010] The output end of the driving source is connected with the input end of the first DFB laser and the input end of the second DFB laser respectively.

[0011] The output end of the first key control module is connected with the control end of the first DFB laser, the output end of the first DFB laser is connected with the input end of the first photoelectric detector, the output end of the first photoelectric detector is connected with the second input end of the first double-threshold quantization module, and the first and second output ends of the first double-threshold quantization module are connected with the first and second input ends of the first FPGA module respectively.

[0012] The output end of the first key control module is also connected with the third input end of the first FPGA module.

[0013] The output end of the second key control module is connected with the control end of the second DFB laser, the output end of the second DFB laser is connected with the input end of the second photoelectric detector, the output end of the second photoelectric detector is connected with the second input end of the second double-threshold quantization module, and the first and second output ends of the second double-threshold quantization module are connected with the first and second input ends of the second FPGA module respectively.

[0014] The output end of the second key control module is also connected with the third input end of the second FPGA module.

[0015] The first output end of the power module is connected with the third input end of the first double-threshold quantization module, the second output end of the power module is connected with the first input end of the first double-threshold quantization module, the third output end of the power module is connected with the third input end of the second double-threshold quantization module, and the fourth output end of the power module is connected with the first input end of the second double-threshold quantization module.

[0016] The first and second output ends of the synchronous clock module are connected with the first and second clock control ends of the first double-threshold quantization module respectively, and the third and fourth output ends of the synchronous clock module are connected with the first and second clock control ends of the second double-threshold quantization module respectively.

[0017] The first FPGA module and the second FPGA module are connected through a communication link.

[0018] Preferably, the first and second double-threshold quantization modules are identical in structure, each comprising a first voltage comparator, a second voltage comparator, a first biasing device, a second biasing device, a first D flip-flop and a second D flip-flop;

[0019] The first input terminal of the first voltage comparator serves as a first input terminal of the double-threshold quantization module, the second input terminal of the first voltage comparator and the second input terminal of the second voltage comparator both serve as a second input terminal of the double-threshold quantization module, and the first input terminal of the second voltage comparator serves as a third input terminal of the double-threshold quantization module;

[0020] The output terminal of the first voltage comparator is connected to the input terminal of the first biasing device, the output terminal of the first biasing device is connected to the input terminal of the first D flip-flop, and the output terminal of the first D flip-flop serves as a first output terminal of the double-threshold quantization module;

[0021] The output terminal of the second voltage comparator is connected to the input terminal of the second biasing device, the output terminal of the second biasing device is connected to the input terminal of the second D flip-flop, and the output terminal of the second D flip-flop serves as a second output terminal of the double-threshold quantization module;

[0022] The first clock control terminal of the first D flip-flop is connected to the first clock control terminal of the second D flip-flop, the first clock control terminal of the first D flip-flop serves as a first clock control terminal of the double-threshold quantization module, the second clock control terminal of the first D flip-flop is connected to the second clock control terminal of the second D flip-flop, and the second clock control terminal of the first D flip-flop serves as a second clock control terminal of the double-threshold quantization module.

[0023] Preferably, the first and second FPGA modules are identical in structure, each comprising a clock synchronization submodule, a master clock submodule, a key code screening submodule, a BCH encoding and decoding submodule and a RAM submodule;

[0024] The first and second input terminals of the clock synchronization submodule serve as the first and second input terminals of the FPGA module, the output terminal of the clock synchronization submodule is connected to the first input terminal of the key code screening submodule, the output terminal of the key code screening submodule is connected to the input terminal of the BCH encoding and decoding submodule, and the output terminal of the BCH encoding and decoding submodule serves as the output terminal of the FPGA module;

[0025] The input terminal of the RAM submodule serves as the third input terminal of the FPGA module, and the output terminal of the RAM submodule is connected to the second input terminal of the key code screening submodule;

[0026] The master clock submodule is connected to the clock synchronization submodule.

[0027] The application further provides a post-processing method for the chaotic key distribution, comprising the following steps:

[0028] S1: generate first local keying code and second local keying code by using first keying module and second keying module respectively, corresponding to control parameters of first DFB laser and second DFB laser, use driving source to drive first DFB laser and second DFB laser to generate first chaotic signal and second chaotic signal respectively;

[0029] input first local keying code and second local keying code into RAM submodule of first FPGA module and RAM submodule of second FPGA module respectively;

[0030] input first chaotic signal and second chaotic signal into first photoelectric detector and second photoelectric detector respectively, corresponding to convert into first analog electrical signal and second analog electrical signal;

[0031] S2: input first analog electrical signal and second analog electrical signal into first double threshold quantization module and second double threshold quantization module respectively, power module sets upper and lower voltage thresholds respectively, and synchronous clock module sets clock respectively, and outputs corresponding double level signals;

[0032] S3: input double level signals of first double threshold quantization module and second double threshold quantization module into clock synchronization submodule of first FPGA module and second FPGA module respectively, adjust main clock submodule of first FPGA module and main clock submodule of second FPGA module to be synchronous with clock set by the synchronous clock module, and output first local seed key and second local seed key respectively;

[0033] S4: keying code screening submodule of first FPGA module obtains first local keying code from RAM submodule of first FPGA module, sends first local keying code to keying code screening submodule of second FPGA module through communication link, keying code screening submodule of second FPGA module compares received first local keying code with second local keying code, screens second local seed key according to comparison result, and generates second screened seed key;

[0034] keying code screening submodule of second FPGA module obtains second local keying code from RAM submodule of second FPGA module, sends second local keying code to keying code screening submodule of first FPGA module through communication link, keying code screening submodule of first FPGA module compares received second local keying code with first local keying code, screens first local seed key according to comparison result, and generates first screened seed key;

[0035] S5: The BCH encoding and decoding submodule of the first FPGA module encodes the screened first local seed key to generate a parity check bit, and sends the parity check bit to the BCH encoding and decoding submodule of the second FPGA module; the BCH encoding and decoding submodule of the second FPGA module performs error correction processing on the parity check bit according to the second screened seed key to generate the same key as the first screened seed key.

[0036] Preferably, in the step S1, the parameters of the DFB laser include power and phase.

[0037] Preferably, the phase is between 0 and pi, when the phases of the first DFB laser and the second DFB laser are the same, the first DFB laser and the second DFB laser output synchronized chaotic signals, otherwise, output chaotic signals without correlation.

[0038] Preferably, the step S2 comprises:

[0039] The first analog electrical signal is input into the first voltage comparator and the second voltage comparator of the first double-threshold quantization module, the first voltage comparator of the first double-threshold quantization module sets the upper limit voltage threshold according to the upper and lower limit voltage thresholds set by the power module, the second voltage comparator of the first double-threshold quantization module sets the lower limit voltage threshold according to the upper and lower limit voltage thresholds set by the power module, when the first analog electrical signal is higher than the upper limit voltage threshold of the first voltage comparator of the first double-threshold quantization module, the first voltage comparator of the first double-threshold quantization module and the second voltage comparator of the first double-threshold quantization module both output high level; when the first analog electrical signal is lower than the lower limit voltage threshold of the second voltage comparator of the first double-threshold quantization module, the first voltage comparator of the first double-threshold quantization module and the second voltage comparator of the first double-threshold quantization module both output low level; when the first analog electrical signal is between the upper limit voltage threshold of the first voltage comparator of the first double-threshold quantization module and the lower limit voltage threshold of the second voltage comparator of the first double-threshold quantization module, the first voltage comparator of the first double-threshold quantization module outputs low level, and the second voltage comparator of the first double-threshold quantization module outputs high level.

[0040] The second analog electric signal is input into the first voltage comparator and the second voltage comparator of the second double-threshold quantization module respectively, the first voltage comparator of the second double-threshold quantization module sets the upper limit voltage threshold according to the upper and lower limit voltage thresholds set by the power module, the second voltage comparator of the second double-threshold quantization module sets the lower limit voltage threshold according to the upper and lower limit voltage thresholds set by the power module, when the second analog electric signal is higher than the upper limit voltage threshold of the first voltage comparator of the second double-threshold quantization module, the first voltage comparator of the second double-threshold quantization module and the second voltage comparator of the second double-threshold quantization module both output high level, when the second analog electric signal is lower than the lower limit voltage threshold of the second voltage comparator of the second double-threshold quantization module, the first voltage comparator of the second double-threshold quantization module and the second voltage comparator of the second double-threshold quantization module both output low level, when the second analog electric signal is between the upper limit voltage threshold of the first voltage comparator of the first double-threshold quantization module and the lower limit voltage threshold of the second voltage comparator of the second double-threshold quantization module, the first voltage comparator of the second double-threshold quantization module outputs low level and the second voltage comparator of the second double-threshold quantization module outputs high level.

[0041] Preferably, in the step S3, the adjusting the clock synchronization of the master clock submodule of the first FPGA module, the master clock submodule of the second FPGA module and the synchronous clock module comprises:

[0042] The clock synchronization submodule of the first FPGA module is used to align the double-level signal of the first double-threshold quantization module with the master clock of the master clock submodule of the first FPGA module, and the phase-locked loop of the first FPGA module is used to generate a synchronous clock matched with the first double-threshold quantization module.

[0043] The clock synchronization submodule of the second FPGA module is used to align the double-level signal of the second double-threshold quantization module with the master clock of the master clock submodule of the second FPGA module, and the phase-locked loop of the second FPGA module is used to generate a synchronous clock matched with the second double-threshold quantization module.

[0044] Preferably, the step S5 comprises:

[0045] The BCH encoding and decoding submodule of the first FPGA module is used to encode the first screening seed key to generate a parity check bit, the parity check bit is sent to the BCH encoding and decoding submodule of the second FPGA module through the communication link.

[0046] The BCH encoding and decoding submodule of the second FPGA module combines the received parity check bit with the second local seed key, generates an error positioning sequence by using the BCH decoding algorithm, and performs an exclusive or operation with the second screening seed key to generate a same key as the first screening seed key.

[0047] The application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to realize the steps of the method.

[0048] Compared with the prior art, the application has the beneficial effects that:

[0049] The application provides a post-processing device and method for chaotic key distribution, which adopts a double-threshold quantization module and an FPGA module to complete a post-processing process of chaotic key distribution, replaces a traditional offline processing process, can significantly improve processing speed, and meets high-speed communication requirements. Through hardware integration, the device provided by the application can reduce equipment dependence and power consumption, realizes miniaturization and high reliability of the device, and provides a real-time and miniaturized solution for the field of secure communication. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 FIG. 1 is a structural schematic diagram of the post-processing device for chaotic key distribution according to Embodiment 1. DETAILED DESCRIPTION

[0051] The accompanying drawings are only used for illustrative purposes, and cannot be understood as a limitation on the patent;

[0052] In order to better illustrate the embodiment, some components in the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product;

[0053] For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0054] The technical solutions of the application will be further described below in combination with the drawings and embodiments.

[0055] Embodiment 1

[0056] The embodiment provides a post-processing device for chaotic key distribution, as shown in FIG. Figure 1 1, which comprises a driving source (1), a power module (5), a synchronous clock module (6), a first DFB laser (2a), a second DFB laser (2b), a first keying module (3a), a second keying module (3b), a first photodetector (4a), a second photodetector (4b), a first double-threshold quantization module, a second double-threshold quantization module, a first FPGA module and a second FPGA module.

[0057] The output end of the driving source (1) is connected with the input end of the first DFB laser (2a) and the second DFB laser (2b) respectively.

[0058] The output end of the first keying module (3a) is connected with the control end of the first DFB laser (2a), the output end of the first DFB laser (2a) is connected with the input end of the first photodetector (4a), the output end of the first photodetector (4a) is connected with the second input end of the first double-threshold quantization module, and the first and second output ends of the first double-threshold quantization module are correspondingly connected with the first and second input ends of the first FPGA module respectively;

[0059] The output end of the first keying module (3a) is also connected with the third input end of the first FPGA module.

[0060] The output end of the second keying module (3b) is connected with the control end of the second DFB laser (2b), the output end of the second DFB laser (2b) is connected with the input end of the second photodetector (4b), the output end of the second photodetector (4b) is connected with the second input end of the second double-threshold quantization module, and the first and second output ends of the second double-threshold quantization module are correspondingly connected with the first and second input ends of the second FPGA module respectively.

[0061] The output end of the second keying module (3b) is also connected with the third input end of the second FPGA module.

[0062] The first output end of the power supply module (5) is connected with the third input end of the first double-threshold quantization module, the second output end of the power supply module (5) is connected with the first input end of the first double-threshold quantization module, the third output end of the power supply module (5) is connected with the third input end of the second double-threshold quantization module, and the fourth output end of the power supply module (5) is connected with the first input end of the second double-threshold quantization module.

[0063] The first and second output ends of the synchronous clock module (6) are correspondingly connected with the first and second clock control ends of the first double-threshold quantization module respectively, and the third and fourth output ends of the synchronous clock module (6) are correspondingly connected with the first and second clock control ends of the second double-threshold quantization module respectively.

[0064] The first FPGA module and the second FPGA module are connected through a communication link.

[0065] The first double-threshold quantization module and the second double-threshold quantization module are the same in structure and each include a first voltage comparator, a second voltage comparator, a first biasing device, a second biasing device, a first D flip-flop and a second D flip-flop.

[0066] The first double-threshold quantization module includes a first voltage comparator (7a), a second voltage comparator (7b), a first biasing device (8a), a second biasing device (8b), a first D flip-flop (9a) and a second D flip-flop (9b).

[0067] The second dual-threshold quantization module comprises a first voltage comparator (7c), a second voltage comparator (7d), a first biasing device (8c), a second biasing device (8d), a first D flip-flop (9c) and a second D flip-flop (9d) of the second dual-threshold quantization module;

[0068] The first input end of the first voltage comparator serves as a first input end of the dual-threshold quantization module, the second input end of the first voltage comparator and the second input end of the second voltage comparator both serve as a second input end of the dual-threshold quantization module, and the first input end of the second voltage comparator serves as a third input end of the dual-threshold quantization module;

[0069] The output end of the first voltage comparator is connected with the input end of the first biasing device, the output end of the first biasing device is connected with the input end of the first D flip-flop, and the output end of the first D flip-flop serves as a first output end of the dual-threshold quantization module;

[0070] The output end of the second voltage comparator is connected with the input end of the second biasing device, the output end of the second biasing device is connected with the input end of the second D flip-flop, and the output end of the second D flip-flop serves as a second output end of the dual-threshold quantization module;

[0071] The first clock control end of the first D flip-flop is connected with the first clock control end of the second D flip-flop, the first clock control end of the first D flip-flop serves as a first clock control end of the dual-threshold quantization module, the second clock control end of the first D flip-flop is connected with the second clock control end of the second D flip-flop, and the second clock control end of the first D flip-flop serves as a second clock control end of the dual-threshold quantization module.

[0072] The first FPGA module and the second FPGA module are of the same structure, and both comprise a clock synchronization submodule, a main clock submodule, a key code screening submodule, a BCH encoding and decoding submodule and a RAM submodule;

[0073] The first FPGA module comprises a clock synchronization submodule (10a), a main clock submodule (11a), a key code screening submodule (12a), a BCH encoding and decoding submodule (13a) and a RAM submodule (14a) of the first FPGA module.

[0074] The second FPGA module comprises a clock synchronization submodule (10b), a main clock submodule (11b), a key code screening submodule (12b), a BCH encoding and decoding submodule (13b) and a RAM submodule (14b) of the second FPGA module.

[0075] The first and second input ends of the clock synchronization submodule are the first and second input ends of the FPGA module, the output end of the clock synchronization submodule is connected with the first input end of the key code screening submodule, the output end of the key code screening submodule is connected with the input end of the BCH encoding and decoding submodule, and the output end of the BCH encoding and decoding submodule is the output end of the FPGA module;

[0076] The input end of the RAM submodule is the third input end of the FPGA module, and the output end of the RAM submodule is connected with the second input end of the key code screening submodule;

[0077] The main clock submodule is connected with the clock synchronization submodule.

[0078] The embodiment adopts the double-threshold quantization module and the FPGA module to complete the post-processing process of the chaotic key distribution, replaces the traditional offline processing process, and since the FPGA module can realize synchronous processing and signal screening, the double-level signals output by the double-threshold quantization are input to the FPGA for real-time processing, which can significantly improve the processing speed and meet the high-speed communication demand. Through hardware integration, the device provided in the embodiment can reduce equipment dependence and power consumption, realize miniaturization and high reliability of the device, realize the change of the post-processing system of the chaotic key distribution from offline processing to real-time processing, and provide a real-time and miniaturized solution for the security communication field.

[0079] Embodiment 2

[0080] The embodiment proposes a post-processing method for chaotic key distribution based on the embodiment 1, and includes the following steps:

[0081] S1: first and second local key codes are respectively generated by using first and second key modules, parameters of first and second DFB lasers are controlled, and first and second chaotic signals are respectively generated by using a driving source to drive the first and second DFB lasers;

[0082] The first and second local key codes are respectively input to the RAM submodule of the first FPGA module and the RAM submodule of the second FPGA module;

[0083] The first and second chaotic signals are respectively input to first and second photodetectors, and are respectively converted into first and second analog electric signals;

[0084] S2: the first and second analog electric signals are respectively input to first and second double-threshold quantization modules, upper and lower voltage thresholds are respectively set by a power module, and clocks are respectively set by a synchronous clock module, and corresponding double-level signals are output;

[0085] S3: The double-level signals of the first double-threshold quantization module and the second double-threshold quantization module are respectively input into the clock synchronization sub-modules of the first FPGA module and the second FPGA module, the master clock sub-modules of the first FPGA module and the second FPGA module are adjusted to be synchronized with the clock set by the synchronization clock module, and the first local seed key and the second local seed key are respectively output;

[0086] S4: The key screening sub-module of the first FPGA module obtains the first local key from the RAM sub-module of the first FPGA module, sends the first local key to the key screening sub-module of the second FPGA module through a communication link, the key screening sub-module of the second FPGA module compares the received first local key with the second local key, screens the second local seed key according to the comparison result, and generates a second screened seed key.

[0087] The key screening sub-module of the second FPGA module obtains the second local key from the RAM sub-module of the second FPGA module, sends the second local key to the key screening sub-module of the first FPGA module through a communication link, the key screening sub-module of the first FPGA module compares the received second local key with the first local key, screens the first local seed key according to the comparison result, and generates a first screened seed key.

[0088] The comparison logic of the key is realized based on hardware, and the screening speed is improved through parallel processing. The screened seed key is stored in the internal register of the FPGA, and can also be stored in an external memory (such as RAM) as the input of subsequent error correction and negotiation. The high parallel computing capability of the FPGA module significantly improves the efficiency of signal screening and key generation, and meets the real-time requirement.

[0089] S5: The BCH encoding and decoding sub-module of the first FPGA module encodes the screened first local seed key to generate a parity check bit, sends the parity check bit to the BCH encoding and decoding sub-module of the second FPGA module, and the BCH encoding and decoding sub-module of the second FPGA module performs error correction processing on the parity check bit according to the second screened seed key to generate the same key as the first screened seed key.

[0090] In the specific implementation process, a broadband optical noise is generated by using a driving source (such as a superluminescent diode (SLD)), and then the power and phase of the laser are adjusted by an injection control and keying module to achieve a chaotic synchronization or non-synchronization state. The chaotic synchronization signal is detected by a photodetector and converted into an analog electrical signal for subsequent quantization processing. In this embodiment, the quantization of the chaotic signal is realized by a double-threshold quantization module, and the screening of the seed key and the encoding and error correction functions of the BCH code are completed by an FPGA module, thereby realizing the real-time and miniaturization of the key distribution.

[0091] Embodiment 3

[0092] In this embodiment, steps S1-S5 are further limited based on embodiment 2, comprising:

[0093] In step S1, the parameters of the DFB laser include power and phase.

[0094] The phase is between 0 and pi. When the phases of the first DFB laser and the second DFB laser are the same, the first DFB laser and the second DFB laser output synchronized chaotic signals, otherwise, the first DFB laser and the second DFB laser output chaotic signals without correlation.

[0095] The step S2 comprises:

[0096] The first analog electrical signal is input into the first voltage comparator and the second voltage comparator of the first double-threshold quantization module. The first voltage comparator of the first double-threshold quantization module sets the upper voltage threshold according to the upper and lower voltage thresholds set by the power module, and the second voltage comparator of the first double-threshold quantization module sets the lower voltage threshold according to the upper and lower voltage thresholds set by the power module. When the first analog electrical signal is higher than the upper voltage threshold of the first voltage comparator of the first double-threshold quantization module, the first voltage comparator of the first double-threshold quantization module and the second voltage comparator of the first double-threshold quantization module both output high level. When the first analog electrical signal is lower than the lower voltage threshold of the second voltage comparator of the first double-threshold quantization module, the first voltage comparator of the first double-threshold quantization module and the second voltage comparator of the first double-threshold quantization module both output low level. When the first analog electrical signal is between the upper voltage threshold of the first voltage comparator of the first double-threshold quantization module and the lower voltage threshold of the second voltage comparator of the first double-threshold quantization module, the first voltage comparator of the first double-threshold quantization module outputs low level and the second voltage comparator of the first double-threshold quantization module outputs high level.

[0097] The second analog electric signal is input into the first voltage comparator and the second voltage comparator of the second double-threshold quantization module respectively, the first voltage comparator of the second double-threshold quantization module sets the upper limit voltage threshold according to the upper and lower limit voltage thresholds set by the power module, the second voltage comparator of the second double-threshold quantization module sets the lower limit voltage threshold according to the upper and lower limit voltage thresholds set by the power module, when the second analog electric signal is higher than the upper limit voltage threshold of the first voltage comparator of the second double-threshold quantization module, the first voltage comparator of the second double-threshold quantization module and the second voltage comparator of the second double-threshold quantization module output high level, when the second analog electric signal is lower than the lower limit voltage threshold of the second voltage comparator of the second double-threshold quantization module, the first voltage comparator of the second double-threshold quantization module and the second voltage comparator of the second double-threshold quantization module output low level, when the second analog electric signal is between the upper limit voltage threshold of the first voltage comparator of the first double-threshold quantization module and the lower limit voltage threshold of the second voltage comparator of the second double-threshold quantization module, the first voltage comparator of the second double-threshold quantization module outputs low level, and the second voltage comparator of the second double-threshold quantization module outputs high level.

[0098] In the step S3, the clock synchronization of the main clock submodule of the first FPGA module, the main clock submodule of the second FPGA module and the synchronous clock module includes:

[0099] The clock synchronization submodule of the first FPGA module is used to align the double-level signal of the first double-threshold quantization module with the main clock of the main clock submodule of the first FPGA module, and the phase-locked loop of the first FPGA module is used to generate a synchronous clock matched with the first double-threshold quantization module.

[0100] The clock synchronization submodule of the second FPGA module is used to align the double-level signal of the second double-threshold quantization module with the main clock of the main clock submodule of the second FPGA module, and the phase-locked loop of the second FPGA module is used to generate a synchronous clock matched with the second double-threshold quantization module, so as to ensure the clock synchronization among the first double-threshold quantization module, the second double-threshold quantization module and the FPGA module, avoid the delay caused by the inconsistent clock, and meet the real-time requirement.

[0101] The step S5 includes:

[0102] The BCH encoding and decoding submodule of the first FPGA module is used to encode the first screening seed key to generate a parity check bit, the parity check bit is sent to the BCH encoding and decoding submodule of the second FPGA module through the communication link.

[0103] The BCH encoding and decoding submodule of the second FPGA module combines the received parity check bit with a second local seed key, generates an error localization sequence using a BCH decoding algorithm, and performs an XOR operation with a second screening seed key to generate a same key as the first screening seed key.

[0104] The embodiment provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the method.

[0105] In the specific implementation process, the signal output by the voltage comparator may not meet the level requirement of the subsequent circuit, and the biasing device is used to adjust the level range to ensure that the signal meets the input voltage requirement of the D flip-flop. Under the action of the differential clock signal, the D flip-flop shapes the adjusted signal to generate a double-level signal (high level and low level correspond to 1 and 0 of the digital signal, respectively). The synchronization of the flip-flop and the output of the flip-flop are ensured to not cause excessive delay, and a low-delay synchronization mechanism is used to ensure that the double-level signal can be quickly transmitted to the FPGA module for real-time processing.

[0106] The embodiment adopts the FPGA module, and the high parallel computing capability of the FPGA module significantly improves the efficiency of signal screening and key generation and meets the real-time requirement.

[0107] The embodiment adopts the BCH encoding and decoding submodule, which not only reduces the error code rate in the key distribution process, but also improves the error correction efficiency through hardware implementation and enhances the practicability of the key distribution device.

[0108] Compared with the prior art, the method has the following beneficial effects:

[0109] 1. Efficient error correction: the hardware implementation based on the BCH code provides real-time error correction capability, and reduces the influence of error codes on key consistency.

[0110] 2. Strong real-time performance: the parallel processing logic of the FPGA module ensures high-speed operation of signal screening and key generation, and meets the requirement of high-speed communication.

[0111] 3. Miniaturized design: the device has high integration and can be widely applied to embedded and portable devices, and is suitable for low-power consumption scenes.

[0112] The same or similar reference signs correspond to the same or similar components;

[0113] The terms describing the positional relationship in the drawings are only used for exemplary description, and cannot be understood as a limitation to the patent;

[0114] Obviously, the above embodiments of the present application are merely exemplary but not intended to limit the embodiments of the present application. Based on the above description, any other variations or changes can be made by those skilled in the art without departing from the spirit and principles of the present application. It is not necessary to list all the embodiments here. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall fall within the scope of the claims of the present application.

Claims

1. A post-processing device for chaos-oriented key distribution, characterized by, The driving source, the power module, the synchronous clock module, the first DFB laser, the second DFB laser, the first keying module, the second keying module, the first photodetector, the second photodetector, the first double-threshold quantization module, the second double-threshold quantization module, the first FPGA module and the second FPGA module are included. The output end of the driving source is connected with the input end of the first DFB laser and the second DFB laser respectively. The output end of the first keying module is connected with the control end of the first DFB laser, the output end of the first DFB laser is connected with the input end of the first photodetector, the output end of the first photodetector is connected with the second input end of the first double-threshold quantization module, and the first and second output ends of the first double-threshold quantization module are connected with the first and second input ends of the first FPGA module respectively. The output end of the first keying module is also connected with the third input end of the first FPGA module. The output end of the second keying module is connected with the control end of the second DFB laser, the output end of the second DFB laser is connected with the input end of the second photodetector, the output end of the second photodetector is connected with the second input end of the second double-threshold quantization module, and the first and second output ends of the second double-threshold quantization module are connected with the first and second input ends of the second FPGA module respectively. The output end of the second keying module is also connected with the third input end of the second FPGA module. The first output end of the power module is connected with the third input end of the first double-threshold quantization module, the second output end of the power module is connected with the first input end of the first double-threshold quantization module, the third output end of the power module is connected with the third input end of the second double-threshold quantization module, and the fourth output end of the power module is connected with the first input end of the second double-threshold quantization module. The first and second output ends of the synchronous clock module are connected with the first and second clock control ends of the first double-threshold quantization module respectively, and the third and fourth output ends of the synchronous clock module are connected with the first and second clock control ends of the second double-threshold quantization module respectively. The first FPGA module and the second FPGA module are connected through a communication link. The first FPGA module and the second FPGA module are identical in structure and each include a clock synchronization submodule, a main clock submodule, a keying code screening submodule, a BCH encoding and decoding submodule and a RAM submodule. The first and second input ends of the clock synchronization submodule are the first and second input ends of the FPGA module, the output end of the clock synchronization submodule is connected with the first input end of the keying code screening submodule, the output end of the keying code screening submodule is connected with the input end of the BCH encoding and decoding submodule, and the output end of the BCH encoding and decoding submodule is the output end of the FPGA module. The input end of the RAM submodule is the third input end of the FPGA module, and the output end of the RAM submodule is connected with the second input end of the keying code screening submodule. The main clock submodule is connected with the clock synchronization submodule.

2. The post-processing device for chaos-based key distribution according to claim 1, characterized in that The first dual-threshold quantization module and the second dual-threshold quantization module are structurally identical, and each includes a first voltage comparator, a second voltage comparator, a first biasing device, a second biasing device, a first D flip-flop and a second D flip-flop; The first input end of the first voltage comparator serves as a first input end of the dual-threshold quantization module, the second input end of the first voltage comparator and the second input end of the second voltage comparator each serve as a second input end of the dual-threshold quantization module, and the first input end of the second voltage comparator serves as a third input end of the dual-threshold quantization module; The output end of the first voltage comparator is connected with the input end of the first biasing device, the output end of the first biasing device is connected with the input end of the first D flip-flop, and the output end of the first D flip-flop serves as a first output end of the dual-threshold quantization module; The output end of the second voltage comparator is connected with the input end of the second biasing device, the output end of the second biasing device is connected with the input end of the second D flip-flop, and the output end of the second D flip-flop serves as a second output end of the dual-threshold quantization module; The first clock control end of the first D flip-flop is connected with the first clock control end of the second D flip-flop, the first clock control end of the first D flip-flop serves as a first clock control end of the dual-threshold quantization module, the second clock control end of the first D flip-flop is connected with the second clock control end of the second D flip-flop, and the second clock control end of the first D flip-flop serves as a second clock control end of the dual-threshold quantization module.

3. A post-processing method for chaos-oriented key distribution, characterized by, The method is implemented based on the device of claims 1-2, The method comprises the following steps: S1: generating a first local keying code and a second local keying code by using a first keying module and a second keying module, respectively, corresponding to controlling parameters of a first DFB laser and a second DFB laser, and driving the first DFB laser and the second DFB laser by using a driving source to generate a first chaotic signal and a second chaotic signal, respectively; inputting the first local keying code and the second local keying code into a RAM submodule of a first FPGA module and a RAM submodule of a second FPGA module, respectively; inputting the first chaotic signal and the second chaotic signal into a first photodetector and a second photodetector, respectively, corresponding to converting into a first analog electrical signal and a second analog electrical signal; S2: inputting the first analog electrical signal and the second analog electrical signal into a first dual-threshold quantization module and a second dual-threshold quantization module, respectively, setting upper and lower voltage thresholds by using a power supply module, and setting a clock by using a synchronous clock module, and outputting corresponding dual-level signals; S3: inputting the dual-level signals of the first dual-threshold quantization module and the second dual-threshold quantization module into a clock synchronization submodule of the first FPGA module and a clock synchronization submodule of the second FPGA module, respectively, adjusting the clock of a main clock submodule of the first FPGA module and a main clock submodule of the second FPGA module to be synchronized with the clock set by the synchronous clock module, and outputting a first local seed key and a second local seed key, respectively. S4: The key code screening submodule of the first FPGA module obtains the first local key code from the RAM submodule of the first FPGA module, and sends the first local key code to the key code screening submodule of the second FPGA module through the communication link. The key code screening submodule of the second FPGA module compares the received first local key code with the second local key code, screens the second local seed key according to the comparison result, and generates a second screened seed key; The key code screening submodule of the second FPGA module obtains the second local key code from the RAM submodule of the second FPGA module, and sends the second local key code to the key code screening submodule of the first FPGA module through the communication link. The key code screening submodule of the first FPGA module compares the received second local key code with the first local key code, screens the first local seed key according to the comparison result, and generates a first screened seed key; S5: The BCH encoding and decoding submodule of the first FPGA module encodes the first screened seed key to generate a parity check bit, and sends the parity check bit to the BCH encoding and decoding submodule of the second FPGA module. The BCH encoding and decoding submodule of the second FPGA module performs error correction processing on the parity check bit according to the second screened seed key to generate a key identical to the first screened seed key.

4. The post-processing method for chaos-oriented key distribution according to claim 3, characterized in that, The parameters of the DFB laser in the step S1 include power and phase.

5. The post-processing method for chaos-based key distribution according to claim 4, characterized in that, The phase is between 0 and pi. When the phases of the first DFB laser and the second DFB laser are the same, the first DFB laser and the second DFB laser output synchronized chaotic signals, otherwise, the first DFB laser and the second DFB laser output chaotic signals without correlation.

6. The post-processing method for chaos-based key distribution according to claim 5, wherein, The step S2 includes: The first analog electrical signal is input into the first voltage comparator and the second voltage comparator of the first double-threshold quantization module. The first voltage comparator of the first double-threshold quantization module sets an upper limit voltage threshold according to the upper and lower limit voltage thresholds set by the power module, and the second voltage comparator of the first double-threshold quantization module sets a lower limit voltage threshold according to the upper and lower limit voltage thresholds set by the power module. When the first analog electrical signal is higher than the upper limit voltage threshold of the first voltage comparator of the first double-threshold quantization module, the first voltage comparator of the first double-threshold quantization module and the second voltage comparator of the first double-threshold quantization module both output high level. When the first analog electrical signal is lower than the lower limit voltage threshold of the second voltage comparator of the first double-threshold quantization module, the first voltage comparator of the first double-threshold quantization module and the second voltage comparator of the first double-threshold quantization module both output low level. When the first analog electrical signal is between the upper limit voltage threshold of the first voltage comparator of the first double-threshold quantization module and the lower limit voltage threshold of the second voltage comparator of the first double-threshold quantization module, the first voltage comparator of the first double-threshold quantization module outputs low level, and the second voltage comparator of the first double-threshold quantization module outputs high level. The second analog electric signal is input into the first voltage comparator and the second voltage comparator of the second dual-threshold quantization module, the first voltage comparator of the second dual-threshold quantization module sets the upper limit voltage threshold according to the upper and lower limit voltage thresholds set by the power module, the second voltage comparator of the second dual-threshold quantization module sets the lower limit voltage threshold according to the upper and lower limit voltage thresholds set by the power module, when the second analog electric signal is higher than the upper limit voltage threshold of the first voltage comparator of the second dual-threshold quantization module, the first voltage comparator of the second dual-threshold quantization module and the second voltage comparator of the second dual-threshold quantization module both output high level, when the second analog electric signal is lower than the lower limit voltage threshold of the second voltage comparator of the second dual-threshold quantization module, the first voltage comparator of the second dual-threshold quantization module and the second voltage comparator of the second dual-threshold quantization module both output low level, when the second analog electric signal is between the upper limit voltage threshold of the first voltage comparator of the first dual-threshold quantization module and the lower limit voltage threshold of the second voltage comparator of the second dual-threshold quantization module, the first voltage comparator of the second dual-threshold quantization module outputs low level and the second voltage comparator of the second dual-threshold quantization module outputs high level.

7. The method of claim 6, wherein the method is a post-processing method for chaos-based key distribution. In the step S3, the adjustment of the clock synchronization of the main clock submodule of the first FPGA module, the main clock submodule of the second FPGA module and the synchronous clock module includes: The clock synchronization submodule of the first FPGA module is used to align the dual-level signal of the first dual-threshold quantization module with the main clock of the main clock submodule of the first FPGA module, and the phase-locked loop of the first FPGA module is used to generate the synchronous clock matched with the first dual-threshold quantization module; The clock synchronization submodule of the second FPGA module is used to align the dual-level signal of the second dual-threshold quantization module with the main clock of the main clock submodule of the second FPGA module, and the phase-locked loop of the second FPGA module is used to generate the synchronous clock matched with the second dual-threshold quantization module.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that The computer program is executed by the processor to realize the steps of the method in any one of claims 4-7.

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