Successive approximation type single-ramp analog-to-digital converter, readout circuit and image sensor

Abstract

The invention provides a successive approximation type single-slope analog-to-digital converter, a readout circuit and an image sensor, and the analog-to-digital converter comprises a high-order analog-to-digital conversion module which carries out the successive approximation type conversion of a pixel signal to obtain high-order conversion data and residual pixel data, and comprises a switched capacitor array, a comparator, a logic control circuit and a prediction circuit; the switched capacitor array receives pixel signals, and the upper electrode plate is connected to the comparator; the prediction circuit is connected with the switched capacitor array and controls the voltage of a lower pole plate of the switched capacitor array under the control of the logic control circuit and the comparator; and the low-order analog-to-digital conversion module is used for performing single-slope conversion on the residual pixel data to obtain low-order conversion data. The high-order conversion data of the current row of pixels is predicted through the prediction circuit according to the quantization result of the previous row of pixels, so that the quantization frequency can be effectively reduced, the power consumption can be reduced, the quantization efficiency can be improved, and the problem of how to improve the quantization efficiency of an analog-to-digital converter in the image sensor is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing circuit design, and particularly relates to a successive approximation single ramp analog-to-digital converter, a readout circuit, and an image sensor. Background Art

[0002] As a core component of modern imaging devices, CIS (CMOS Image Sensor) has important applications in the fields of consumer electronics, medical imaging, security monitoring, vehicle-mounted, etc. For these applications, low-power and high-quantization speed designs are particularly important. The analog-to-digital converter (ADC) plays the role of converting analog signals into digital signals, is an important part of the CIS readout circuit, and most of the power consumption in the CIS also comes from the ADC.

[0003] Currently, SS ADC (Single slop ADC) is widely used in the field of image sensors due to its advantages of good linearity and low power consumption. A traditional SS ADC generally consists of a ramp generator, a counter, and a comparator. Among them, the ramp generator generates a ramp voltage Vramp under the control of a clock. The ramp voltage Vramp is coupled to the positive input terminal of the comparator, and the pixel output signal Vpixout is coupled to the negative input terminal of the comparator; when the output voltage Vramp of the ramp generator is less than the pixel output signal Vpixout, the output of the comparator flips from 0 to 1, the counter stops counting, and finally the difference between the results of the two counts is the digital code value after quantization of the pixel signal.

[0004] However, for the existing N-bit SS ADC, it takes 2 N clock cycles to complete one quantization, and the quantization speed is very slow. Moreover, in practical applications, in order to eliminate FPN (Fixed Pattern noise), CDS (Correlated Double Sampling) or CMS (Correlated Multiple Sampling) operations are often performed, making the time for completing one effective readout even longer. Therefore, the existing single ramp analog-to-digital converter cannot meet the design requirements of high-frame-rate, high-resolution, and low-power image sensors. Summary of the Invention

[0005] The purpose of the present invention is to provide a successive approximation single ramp analog-to-digital converter, a readout circuit, and an image sensor to at least solve the problem of how to improve the quantization efficiency of the analog-to-digital converter in an image sensor.

[0006] To solve the above technical problems, the present invention provides a successive approximation single ramp analog-to-digital converter, including: A high-bit analog-to-digital conversion module is used to perform successive approximation conversion on pixel signals to obtain high-bit conversion data and remaining pixel data. The high-bit analog-to-digital conversion module includes a switched-capacitor array, a comparator, a logic control circuit, and a prediction circuit. The input end of the switched-capacitor array receives pixel signals, and the upper plates of the switched-capacitor array are connected to the first input end of the comparator. The second input end of the comparator receives a common-mode voltage. The output end of the comparator is respectively connected to the logic control circuit and the prediction circuit. The logic control circuit is connected to the prediction circuit. The prediction circuit is connected to the switched-capacitor array to control the voltage of the lower plates of the switched-capacitor array under the control of the logic control circuit and the comparator. The prediction circuit outputs high-bit conversion data. A low-bit analog-to-digital conversion module, whose input end is connected to the output end of the comparator, is used to perform single-ramp conversion on the remaining pixel data not converted by the high-bit analog-to-digital conversion module to obtain low-bit conversion data. The sum of the conversion accuracy of the high-bit analog-to-digital conversion module and the conversion accuracy of the low-bit analog-to-digital conversion module is the conversion accuracy of the entire analog-to-digital conversion module.

[0007] Optionally, in the successive approximation single-ramp analog-to-digital converter, the high-bit analog-to-digital conversion module further includes an operational amplifier circuit. The operational amplifier circuit includes a first operational amplifier capacitor, a second operational amplifier capacitor, a first operational amplifier switch, a second operational amplifier switch, and an operational amplifier. The first input end of the operational amplifier receives pixel signals through the first operational amplifier capacitor, and the second input end receives a common-mode voltage through the second operational amplifier capacitor. The two ends of the first operational amplifier switch are respectively connected to the first input end and the first output end of the operational amplifier, and the two ends of the second operational amplifier switch are respectively connected to the second input end and the second output end of the operational amplifier. The first output end of the operational amplifier is connected to the first input end of the comparator, and the second output end of the operational amplifier is connected to the second input end of the comparator.

[0008] Optionally, in the successive approximation single-ramp analog-to-digital converter, the switched-capacitor array includes M + 1 switched-capacitor branches connected in parallel. Each switched-capacitor branch includes a switching switch and a sampling capacitor connected in series, and is used to perform high-M-bit data quantization on pixel signals. The switching switch is used to switch to access different reference voltages or ramp voltages under the control of the prediction circuit, where M is an integer greater than or equal to 3.

[0009] Optionally, in the successive approximation single-ramp analog-to-digital converter, during the row readout process of the successive approximation single-ramp analog-to-digital converter, if the currently read pixel is located in the first row, the prediction circuit does not start; otherwise, the prediction circuit starts. When the prediction circuit is started, the prediction circuit uses the high-k bit conversion data obtained by converting the pixels in the previous row as the prediction value for the conversion of the pixels in the current row, and controls the switch capacitor branch corresponding to the high-k bits to output a prediction voltage to the comparator for comparison; where k is an integer greater than or equal to 1 and less than or equal to M.

[0010] Optionally, in the successive approximation single-ramp analog-to-digital converter, the prediction circuit includes a prediction value storage circuit, a selection and judgment circuit, and a prediction result judgment circuit; the prediction value storage circuit is used to store the high-k bit conversion data obtained by converting the pixels in the previous row; the selection and judgment circuit is used to read the high-k bit conversion data from the prediction value storage circuit and receive the M-bit control data output by the logic control circuit to output an M+1-bit prediction result; the prediction result judgment circuit is used to judge whether the prediction is successful according to the comparison result output by the comparator and the prediction result output by the selection and judgment circuit, and generate a comparator control signal according to the judgment result.

[0011] Optionally, in the successive approximation single-ramp analog-to-digital converter, the selection and judgment circuit includes k flip-flops, k AND gates, and M+1 multiplexers; the input terminal of each flip-flop is respectively connected to one bit of the high-k bit conversion data, and the output terminal is connected to the first input terminal of one AND gate; the second input terminal of each AND gate is connected to the inverted first row trigger signal; the first input terminals of M multiplexers are respectively connected to one bit of the M-bit control data output by the logic control circuit, the first input terminal of the M+1th multiplexer is grounded, the second input terminals of k multiplexers are connected to the output terminal of the AND gate, the second input terminals of M-k+1 multiplexers are connected to the power supply, and the output terminals of the multiplexers output prediction result data.

[0012] Optionally, in the successive approximation single-ramp analog-to-digital converter, the selection and judgment circuit further includes a selection signal generation circuit; the selection signal generation circuit includes a first selection signal generation unit and a second selection signal generation unit; the first selection signal generation unit is used to generate a first selection signal according to the inverted first row trigger signal and the first prediction enable signal; the second selection signal generation unit is used to generate a second selection signal according to the inverted first row trigger signal and the second prediction enable signal; the first selection signal is the selection signal of the k multiplexers connected to the AND gates, and the second selection signal is the selection signal of the remaining M-k+1 multiplexers.

[0013] Optionally, in the successive approximation single-ramp analog-to-digital converter, the prediction result judgment circuit includes a first flip-flop, a second flip-flop, a first dual multiplexer, a second dual multiplexer, an inverter, a first AND gate, a second AND gate, and an OR gate; the input terminals of the first flip-flop and the second flip-flop are connected to the output terminal of the comparator; the output terminal of the first flip-flop is connected to the first input terminal of the first AND gate, and the output terminal of the second flip-flop is connected to the second input terminal of the first AND gate through the inverter; the output terminal of the first AND gate is connected to the selection terminal of the first dual multiplexer; the two input terminals of the first dual multiplexer are respectively connected to a first comparator enable signal and a second comparator enable signal; the two input terminals of the second dual multiplexer are respectively connected to a first prediction enable signal and ground, and the selection terminal is connected to the inverted first row trigger signal; the input terminals of the OR gate are connected to a third comparator enable signal, the output terminal of the first dual multiplexer, and the output terminal of the second dual multiplexer; the input terminals of the second AND gate are respectively connected to a clock signal and the output terminal of the OR gate; the output terminal of the second AND gate outputs a comparator clock signal, and the comparator control signal includes the comparator clock signal.

[0014] To solve the above technical problems, the present invention further provides a readout circuit, including the successive approximation single-ramp analog-to-digital converter described in any one of the above.

[0015] To solve the above technical problems, the present invention further provides an image sensor, including the readout circuit described above.

[0016] The successive approximation single-ramp analog-to-digital converter, readout circuit, and image sensor provided by the present invention include: a high-bit analog-to-digital conversion module for performing successive approximation conversion on a pixel signal to obtain high-bit conversion data and remaining pixel data; the high-bit analog-to-digital conversion module includes a switched-capacitor array, a comparator, a logic control circuit, and a prediction circuit; an input end of the switched-capacitor array receives the pixel signal, and an upper plate of the switched-capacitor array is connected to a first input end of the comparator; a second input end of the comparator receives a common-mode voltage; an output end of the comparator is respectively connected to the logic control circuit and the prediction circuit; the logic control circuit is connected to the prediction circuit; the prediction circuit is connected to the switched-capacitor array to control a lower plate voltage of the switched-capacitor array under the control of the logic control circuit and the comparator; the prediction circuit outputs the high-bit conversion data; a low-bit analog-to-digital conversion module for performing single-ramp conversion on the remaining pixel data not converted by the high-bit analog-to-digital conversion module to obtain low-bit conversion data. Based on the strong spatial correlation between pixels in an image, the prediction circuit predicts the high-bit conversion data of the current row of pixels according to the quantization results of the previous row of pixels, which can effectively reduce the number of quantization times, thereby reducing the charge and discharge times of the high-bit capacitor. This can not only reduce power consumption but also improve the quantization efficiency, solving the problem of how to improve the quantization efficiency of the analog-to-digital converter in an image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a structural block diagram of the successive approximation single-ramp analog-to-digital converter provided in this embodiment; Figure 2 is a circuit schematic diagram of the successive approximation single-ramp analog-to-digital converter provided in this embodiment; Figure 3 is a structural block diagram of the prediction circuit provided in this embodiment; Figure 4 is a circuit schematic diagram of the selection and judgment circuit provided in this embodiment; Figure 5 is a circuit schematic diagram of the prediction result judgment circuit provided in this embodiment; Figure 6 is a circuit schematic diagram of the logic circuit for generating an enable signal provided in this embodiment; Figure 7 is a timing control diagram of the successive approximation single-ramp analog-to-digital converter without enabling the prediction function provided in this embodiment; Figure 8 is a timing control diagram of the successive approximation single-ramp analog-to-digital converter with the prediction function enabled provided in this embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] The successive approximation type single ramp analog-to-digital converter, readout circuit and image sensor proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different focuses and sometimes use different scales.

[0019] It should be noted that the "first", "second", etc. in the description, claims and drawings of the present invention are used to distinguish similar objects, so as to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that such structures can be interchanged under appropriate circumstances. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0020] In the existing conventional readout circuit, the analog-to-digital converter quantifies each pixel signal from scratch. However, for a frame of image, most pixels have strong spatial correlation and the pixel value differences are very small, that is, the output signal values of most correlated pixels are similar. The existing quantization method ignores the similarity relationship between the pixel output signal values, resulting in waste of resources in the quantization process.

[0021] Based on this, this embodiment provides a successive approximation type single ramp analog-to-digital converter, as Figure 1 shown, including: A high-bit analog-to-digital conversion module for performing successive approximation type conversion on the pixel signal to obtain high-bit conversion data and remaining pixel data; the high-bit analog-to-digital conversion module includes a switched capacitor array, a comparator, a logic control circuit and a prediction circuit; the input end of the switched capacitor array receives the pixel signal, and the upper plate of the switched capacitor array is connected to the first input end of the comparator; the second input end of the comparator receives the common-mode voltage; the output end of the comparator is respectively connected to the logic control circuit and the prediction circuit; the logic control circuit is connected to the prediction circuit; the prediction circuit is connected to the switched capacitor array to control the lower plate voltage of the switched capacitor array under the control of the logic control circuit and the comparator; the prediction circuit outputs the high-bit conversion data; A low-bit analog-to-digital conversion module, whose input end is connected to the output end of the comparator, for performing single ramp conversion on the remaining pixel data not converted by the high-bit analog-to-digital conversion module to obtain low-bit conversion data.

[0022] The successive approximation single-ramp analog-to-digital converter provided in this embodiment, based on the strong spatial correlation between pixels in an image, can effectively reduce the quantization times by predicting the high-order conversion data of the current row of pixels according to the quantization results of the pixels in the previous row through a prediction circuit, thereby reducing the charge and discharge times of the high-order capacitors. This can not only reduce power consumption but also improve the quantization efficiency, solving the problem of how to improve the quantization efficiency of the analog-to-digital converter in an image sensor.

[0023] Among them, the working principle of successive approximation conversion is to gradually approximate the digital value of the input analog signal through a successive approximation register (SAR). The specific process is that the SAR starts from the highest bit, sets each bit to 1 in turn, then converts this digital value into an analog voltage through a digital-to-analog converter (DAC), and compares it with the input analog signal. If the converted analog voltage is greater than the input analog signal, this bit is set to 0, otherwise it is set to 1. Such a comparison is carried out bit by bit until the lowest bit.

[0024] Specifically, in this embodiment, assuming that the pixel data after quantization conversion is N bits (N bit) in total, the high-order analog-to-digital conversion module is responsible for converting the high M-bit pixel data in a successive approximation conversion manner, and the low-order mode conversion module is responsible for converting the remaining low N - M-bit pixel data in a single-ramp conversion manner; where M is an integer greater than or equal to 3 and less than or equal to N.

[0025] Furthermore, in this embodiment, the low-order analog-to-digital conversion module is similar to the existing analog-to-digital converter structure and includes a comparator, a counter, and a capacitor. Specifically, to simplify the circuit structure, as Figure 2 shown, the low-order analog-to-digital conversion module can share a comparator and the capacitors in the switched capacitor array with the high-order analog-to-digital converter module. The output end of the comparator is connected to the counter, and the capacitors of the switched capacitor array are connected to the ramp voltage.

[0026] And, in this embodiment, as Figure 2 shown, in the high-order analog-to-digital conversion module, the switched capacitor array includes M + 1 switched capacitor branches connected in parallel; each of the M switched capacitor branches includes switching switches S(0) to S(M - 1) and sampling capacitors C(0) to C(M - 1) connected in series, and the other switched capacitor branch (ramp sampling branch) includes switching switch S(P) and C(01) connected in series.

[0027] Among them, the switching switches S(0) to S(M - 1) and the sampling capacitors C(0) to C(M - 1) (M switch-capacitor branches) are used to perform high-M-bit quantization on the pixel signal; the switching switches S(0) to S(M - 1) are used to switch the lower plates of the sampling capacitors C(0) to C(M - 1) to access different reference voltages under the control of the prediction circuit. The switching switch S(P) and the sampling capacitor C(01) (ramp sampling branch) are used to perform low-N-bit quantization on the pixel signal; the switching switch S(P) is used to switch the lower plate of the sampling capacitor C(01) to access the reference voltage Vref or the ramp voltage Vramp under the control of the prediction circuit.

[0028] Further, in this embodiment, the switch-capacitor array further includes a reset switch S(R) connected in parallel with the switch-capacitor branches; and the switch-capacitor array further includes a switch S(S) for controlling the switch-capacitor array to sample the pixel signal. In practical applications, the switching switches S(0) to S(M - 1) and S(P) can be single-pole double-throw switches.

[0029] In this embodiment, two reference voltages are set, namely the first reference voltage Vref1 and the second reference voltage Vref2, and Vref2 > Vref1. In practical applications, the first reference voltage Vref1 can be 0, and the second reference voltage Vref2 can be Vref. The first reference voltage Vref1 is connected to one end of the switch S(R) and the first branch ends of the switching switches S(0) to S(M - 1), the second reference voltage Vref2 is connected to the second branch ends of the switching switches S(0) to S(M - 1) and S(P), and the ramp voltage Vramp is connected to the first branch end of the switching switch S(P). Thus, by adjusting the conduction states of the reset switch S(R), the lower-plate switching switches S(0) to S(M - 1) and S(P), the adjustment of the lower-plate voltages of the sampling capacitors in each branch can be achieved. In practical applications, the states of the switching switches S(0) to S(M - 1) and S(P) in the switch-capacitor array are controlled by the output values Q(01), Q(0) to Q(M - 1) of the prediction circuit.

[0030] And, in this embodiment, as Figure 2As shown, the high-bit analog-to-digital conversion module further includes an operational amplifier circuit; the operational amplifier circuit includes a first operational amplifier capacitor C1, a second operational amplifier capacitor C2, a first operational amplifier switch S1, a second operational amplifier switch S2, and an operational amplifier; the first input terminal of the operational amplifier is coupled to the pixel signal through the first operational amplifier capacitor C1, and the second input terminal is coupled to GND through the second operational amplifier capacitor C2 to obtain a common-mode voltage; both ends of the first operational amplifier switch S1 are respectively connected to the first input terminal and the first output terminal of the operational amplifier, and both ends of the second operational amplifier switch S2 are respectively connected to the second input terminal and the second output terminal of the operational amplifier; the first output terminal of the operational amplifier is connected to the first input terminal of the comparator, and the second output terminal of the operational amplifier is connected to the second input terminal of the comparator.

[0031] In this embodiment, by adding an operational amplifier circuit, the voltage difference can be amplified, the common mode can be established, and the kickback noise can be weakened. In this way, after the comparator amplifies the signal amplified by the operational amplifier circuit again, the voltage difference at the output terminal of the comparator is close to VDD, which is beneficial to the subsequent digital circuit's utilization of the output signal.

[0032] In Figure 2 In the circuit shown, the first input terminal is the negative input terminal, and the second input terminal is the positive input terminal. At this time, if the output value of the switched-capacitor array is less than the voltage of the positive input terminal of the comparator (common-mode voltage), the comparator outputs 1, otherwise it outputs 0.

[0033] Further, in this embodiment, as Figure 3 shown, the prediction circuit includes a predicted value storage circuit, a selection and judgment circuit, and a prediction result judgment circuit; the predicted value storage circuit is used to store the high-k-bit conversion data P M-1 、P M-2 、……P M-k converted from the pixels of the previous row, where k is an integer greater than or equal to 1 and less than or equal to M; the selection and judgment circuit is used to read the high-k-bit conversion data from the predicted value storage circuit and receive the M-bit control data B 0 to B M-1 output by the logic control circuit to output M + 1-bit prediction results Q(01), Q(0) to Q(M - 1); the prediction result judgment circuit is used to judge whether the prediction is successful according to the comparison result output by the comparator and generate a comparator control signal according to the judgment result. Specifically, it is the comparator clock signal CLK_C.

[0034] Specifically, in this embodiment, as Figure 4 shown, the selection and judgment circuit includes k flip-flops, k AND gates, and M + 1 multiplexers ( Figure 4In the illustrated embodiment, k is 4 and M is 7). One bit of data P in the high-k-bit conversion data is respectively connected to the input end of each trigger, and the output end is connected to the first input end of one of the AND gates; the second input end of each AND gate is connected to the inverted first row trigger signal ROW_B1; one bit of the M-bit control data output by the logic control circuit is respectively connected to the first input end of M multiplexers, the first input end of the (M + 1)-th multiplexer is grounded, the second input ends of k multiplexers are connected to the output end of the AND gate, the second input ends of M - k + 1 multiplexers are connected to the power supply, and the output end of the multiplexer outputs the predicted result data.

[0035] It should be noted that in this embodiment, ROW1 represents the pulse trigger signal for the first row of pixels output by the row selection decoding drive circuit; ROW_B1 represents the signal after inverting ROW1.

[0036] Preferably, in order to implement the selection output control of the multiplexer, in this embodiment, the selection judgment circuit further includes a selection signal generation circuit; the selection signal generation circuit includes a first selection signal generation unit and a second selection signal generation unit; the first selection signal generation unit is used to generate a first selection signal S0 according to the inverted first row trigger signal ROW_B1 and the first prediction enable signal Pre_en1; the second selection signal generation unit is used to generate a second selection signal S1 according to the inverted first row trigger signal ROW_B1 and the second prediction enable signal Pre_en2; the first selection signal S0 is the selection signal of the k multiplexers connected to the AND gates, and the second selection signal S1 is the selection signal of the remaining M - k + 1 multiplexers.

[0037] In practical applications, the trigger can specifically be a D trigger. Also, the first selection signal generation unit includes a first selection AND gate and a selection OR gate. The two input ends of the first selection AND gate are respectively connected to the inverted first row trigger signal ROW_B1 and the first prediction enable signal Pre_en1, and the two input ends of the selection OR gate are respectively connected to the output end of the first selection AND gate and the predicted result O confirmed by the predicted result judgment circuit 0 , and the output end outputs the first selection signal S0; the second selection signal generation unit includes a second selection AND gate. The two input ends of the second selection AND gate are respectively connected to the inverted first row trigger signal ROW_B1 and the second prediction enable signal Pre_en2, and the output end outputs the second selection signal S1.

[0038] Also, in this embodiment, as Figure 5As shown, the prediction result judgment circuit includes a first flip-flop, a second flip-flop, a first dual multiplexer, a second dual multiplexer, a NOT gate, a first AND gate, a second AND gate, and an OR gate; the clock terminals of the first flip-flop and the second flip-flop are connected to different enable signals EN1 and EN2; the input terminals of the first flip-flop and the second flip-flop are connected to the output terminal of the comparator, that is, connected to Vcomp; the output terminal of the first flip-flop is connected to the first input terminal of the first AND gate, and the output terminal of the second flip-flop is connected to the second input terminal of the first AND gate through the NOT gate; the output terminal of the first AND gate is connected to the selection terminal of the first dual multiplexer, providing a selection signal O to the selection terminal of the first dual multiplexer 0 ; the two input terminals of the first dual multiplexer are respectively connected to a first comparator enable signal EN_A and a second comparator enable signal EN_B; the two input terminals of the second dual multiplexer are respectively connected to a first prediction enable signal Pre_en1 and ground GND, and the selection terminal is connected to the inverted first row trigger signal ROW_B1; the input terminals of the OR gate are connected to a third comparator enable signal EN_X, the output terminal of the first dual multiplexer, and the output terminal of the second dual multiplexer; the input terminals of the second AND gate are respectively connected to a clock signal CLKC and the output terminal of the OR gate; the output terminal of the second AND gate outputs a comparator clock signal CLK_C, and the comparator control signal includes the comparator clock signal

[0039] In practical applications, the first flip-flop and the second flip-flop can be D flip-flops. Also, the clock terminals of the first flip-flop and the second flip-flop being connected to different enable signals EN1 and EN2 can be obtained by performing a logic operation on a first selection signal, a second selection signal, a first prediction enable signal, and a second prediction enable signal using a logic circuit. Specifically, the logic circuit used can be as Figure 6 shown. The first stage includes an XOR gate and an AND gate, and the second stage includes two AND gates; the first selection signal S0_0 and the second selection signal S0_1 are respectively input to the two input terminals of the XOR gate and the first-stage AND gate; one input terminal of each of the two second-stage AND gates is connected to the clock signal CLKC, and the other input terminal is respectively connected to the output terminal of the XOR gate and the output terminal of the AND gate. The output terminals of the two AND gates respectively output the enable signals EN1 and EN2

[0040] Next, please refer to Figure 2 and in combination with Figure 7 and Figure 8 the timing diagrams shown to illustrate the working mode of the successive approximation single-ramp analog-to-digital converter provided in this embodiment above. Among them, when the successive approximation single-ramp analog-to-digital converter provided in this embodiment is working, there are two modes: ① working without turning on the prediction circuit; ② working with the prediction circuit turned on

[0041] Specifically, during the row readout process of the successive approximation single-ramp analog-to-digital converter, if the currently read pixel is located in the first row, the prediction circuit is not activated; otherwise, the prediction circuit is activated.

[0042] ① When the conversion prediction is not performed by enabling the prediction circuit, refer to Figure 2 and Figure 7 , the working mode of the successive approximation single-ramp analog-to-digital converter provided in this embodiment is as follows: State 1: Sample the pixel signal (reset signal) Vrst. The switch S(S) is closed, and the upper plate of the switched-capacitor array is connected to PIX_OUT (reset signal Vrst). At the same time, the reset switches S1 and S2 are closed. The left plate of C1 is connected to PIX_OUT, and the right plate is connected to the negative input terminal Vn of the comparator preamplifier; the left plate of C2 is connected to GND, and the right plate is connected to the positive input terminal Vp of the preamplifier, thereby completing the sampling of the reset signal Vrst.

[0043] In State 1, the charge value Q1 stored in the switched-capacitor array is:

[0044] where represents the pixel reset signal, represents the total capacitance value of the switched-capacitor array.

[0045] State 2 (including SAR quantization and SS quantization): Quantify the reset signal. The logic control circuit directly controls the output voltage value Vdac of the switched-capacitor array. This value passes through the coupling capacitor C1 to the negative input terminal Vn of the comparator, and the comparator compares and outputs the Vcomp signal. If the comparator outputs 1, it means that the output value of the switched-capacitor array is less than the voltage at the positive input terminal of the comparator; otherwise, it outputs 0. The output signal of the comparator is fed back to the logic control circuit to control the circuit switching of each branch in the switched-capacitor array, and so on to complete the comparison of the high M bits. When entering the quantization of the low N-M bits, the counter enable signal EN_CNT is pulled high, and the counter starts counting until the comparator outputs 0, at which point the counting stops, and the digital code value of the counter at this time is the quantization result of the low N-M bits.

[0046] In State 2, the charge value Q2 stored in the switched-capacitor array is:

[0047]

[0048] where represents the reference voltage connected to the lower plate of the sampling capacitor in each switched-capacitor branch in the switched-capacitor array; represents the quantization code value of the high M bits; Represents the quantization code value of the lower N-M bits; Represents the binary capacitance value of the sampling capacitor corresponding to the serial number, ; Represents the voltage value of the ramp signal.

[0049] As can be seen from State 1 and State 2, during the comparison stage, the voltage value Vdac output by the switched-capacitor array is:

[0050] At this time, during the comparison stage, the Vdac voltage is coupled to the negative input terminal of the comparator through a capacitor. The voltage conditions at the positive and negative input terminals of the comparator are as follows:

[0051]

[0052] The comparator quickly distinguishes and gives a comparison result according to the difference of the input signals and under the timing control.

[0053] State 3: Sample the pixel signal (exposure signal) Vsig. The switch S(S) is closed, and the upper plate of the switched-capacitor array is connected to PIX_OUT (exposure signal Vsig). The left plate of C1 is connected to PIX_OUT, and the right plate is connected to the negative input terminal Vn of the preamplifier of the comparator; the left plate of C2 is connected to GND, and the right plate is connected to the positive input terminal Vp of the preamplifier, thus completing the sampling of the exposure signal Vsig.

[0054] State 4 (including SAR quantization and SS quantization): Quantize the exposed signal Vsig. The logic control circuit directly controls the voltage value output by the switched-capacitor array. This value passes through the coupling capacitor C1 to the negative input terminal Vn of the comparator, and the comparator compares and outputs the Vcomp signal. If the comparator outputs 1, it means that the output value of the switched-capacitor array is less than the voltage at the positive input terminal of the comparator; otherwise, it outputs 0. The output signal of the comparator is fed back to the logic control circuit to control the circuit switching of each branch in the switched-capacitor array, and so on to complete the comparison of the higher M bits. When entering the low N-M bit SS ADC quantization, the counter enable signal EN_CNT is pulled high, and the counter starts counting until the comparator outputs 0, then stops counting. The digital code value of the counter at this time is the quantization result of the low N-M bits.

[0055] Similarly, in State 3 and State 4, the voltage value Vdac output by the switched-capacitor array is:

[0056] At this time, during the comparison stage, the Vdac voltage is coupled to the negative input terminal of the comparator through a capacitor. The voltage conditions at the positive and negative input terminals of the comparator are as follows:

[0057]

[0058] The comparator quickly resolves and gives a comparison result according to the difference of the input signals and under timing control.

[0059] ② When the prediction circuit is enabled to perform conversion prediction, refer to Figure 2 and Figure 8 , the working mode of the successive approximation single-ramp analog-to-digital converter provided in this embodiment is as follows: State 1: After the sampling and quantization of the first row of pixels are completed according to working mode ①, the write enable signal EN_W is pulled high, and the converted code values (digital codes) of the high k bits, that is, P N-1 , P N-2 ... P N-k are written into the prediction circuit.

[0060] State 2 (including SAR quantization and SS quantization): When quantizing the pixel signal (exposure signal) Vsig, the prediction circuit is enabled (since the pixels in the reset signal are not photosensitive and the reset signal remains constant for the same pixel, there is no need to predict the reset signal).

[0061] In this embodiment, the prediction is performed twice: Prediction 1: The first prediction enable signal Pre_en1 is pulled high, and the prediction circuit uses the converted data of the high k bits obtained from the previous row of pixels as the prediction value for the conversion of the current row of pixels. The prediction circuit outputs P N-1 , P N-2 ... P N-k and B N-k-1 , B N-k-2 ... B 0 , Q 01 . The output signal controls the voltage switching of the lower plates of the sampling capacitors in each switch-capacitor branch in the switch-capacitor array, so that the prediction value is configured to the lower plates of the sampling capacitors in the switch-capacitor array, so that the predicted voltage Vdac output by the switch-capacitor branch is coupled to the comparator through the capacitor C1 for comparison. If the result output by the comparator is 1, it indicates that the prediction value is less than Vrst - Vsig. P N-1 , P N-2 ... P N-k are the k-bit prediction values, and B N-k-1 , B N-k-2 ... B 0 are the code values output by the logic control circuit of this row.

[0062] In Prediction 1, the initial prediction value output by the switch-capacitor array is:

[0063] Prediction 2: The second prediction enable signal Pre_en2 is pulled high, and the prediction circuit outputs P N-1 、P N-2 ……P N-k and 111……11. The output signal controls the voltage switching of the lower plates of the sampling capacitors in each switch-capacitor branch of the switch-capacitor array, and switches the voltage of the lower plates of the remaining M-k+1 sampling capacitors in the switch-capacitor array to Vref2, so that the switch-capacitor branch outputs a predicted sampling voltage to the comparator for comparison. If the result output by the comparator is 0, it indicates that the predicted value is greater than Vrst - Vsig, which indicates that the effective pixel signal to be quantized is within the range of Vdac2, and it is effective to start the quantization of the remaining bits after the prediction ends.

[0064] In Prediction 2, the initial predicted value output by the switch-capacitor array is:

[0065] If , it indicates that the pixel signal of the current row has a small difference (strong correlation) with the pixel signal of the previous row. Therefore, the value output by the prediction circuit can be used as the quantization value of the high k bits. The prediction circuit will switch the clock signal CLK_C of the comparator, so that the analog-to-digital converter skips the high k bits quantization and directly quantizes from the N-k-th bit, achieving both improving the quantization efficiency and reducing the power consumption; if not satisfied, it indicates that the pixels of the current row do not have strong correlation with the pixels of the previous row, so a complete quantization needs to be restarted.

[0066] For the successive approximation single-ramp analog-to-digital converter (SAR / SS ADC) provided in this embodiment, through the above logical reasoning involved in the sampling, prediction, and quantization processes, it can be seen that when quantizing non-first-row pixels, the prediction circuit is turned on. At this time, if the high k-bit predicted value is predicted effectively, the high k bits quantization can be directly skipped. In this way, for pixel units with strong correlation, the output values do not need to be repeatedly quantized, effectively reducing the quantization times of the analog-to-digital converter, thereby reducing the charge and discharge times of the high-order capacitors, which can not only reduce the power consumption but also improve the quantization efficiency; if the high k-bit predicted value prediction fails effectively, it indicates that the pixel output value has a large difference from the adjacent pixels in the previous row. Therefore, the successive approximation single-ramp analog-to-digital converter re-quantizes.

[0067] The successive approximation single-ramp analog-to-digital converter (SAR / SS ADC) provided in this embodiment can, on the basis of accelerating the quantization speed, utilize the spatial correlation between pixels to predict the high k-bit digital code value of the pixels in this row with the quantization result of the pixels in the previous row, reduce the quantization times of the analog-to-digital converter for the pixel output value, and save the power consumption of the readout circuit for reading out one frame of the image.

[0068] This embodiment also provides a readout circuit, including the successive approximation single-ramp analog-to-digital converter as described above.

[0069] In addition, this embodiment also provides an image sensor, including the readout circuit as described above.

[0070] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. In addition, the different parts among the embodiments can also be combined and used. The present invention does not limit this.

[0071] The successive approximation single-ramp analog-to-digital converter, readout circuit, and image sensor provided in this embodiment include: a high-bit analog-to-digital conversion module for performing successive approximation conversion on the pixel signal to obtain high-bit conversion data and remaining pixel data; the high-bit analog-to-digital conversion module includes a switched-capacitor array, a comparator, a logic control circuit, and a prediction circuit; the input end of the switched-capacitor array receives the pixel signal, and the upper plate of the switched-capacitor array is connected to the first input end of the comparator; the second input end of the comparator receives the common-mode voltage; the output end of the comparator is respectively connected to the logic control circuit and the prediction circuit; the logic control circuit is connected to the prediction circuit; the prediction circuit is connected to the switched-capacitor array to control the voltage of the lower plate of the switched-capacitor array under the control of the logic control circuit and the comparator; the prediction circuit outputs the high-bit conversion data; a low-bit analog-to-digital conversion module for performing single-ramp conversion on the remaining pixel data not converted by the high-bit analog-to-digital conversion module to obtain low-bit conversion data. Based on the strong spatial correlation between pixels in the image, the prediction circuit predicts the high-bit conversion data of the current row of pixels according to the quantization results of the pixels in the previous row, which can effectively reduce the number of quantization times, thereby reducing the charge and discharge times of the high-bit capacitor. It can not only reduce the power consumption, but also improve the quantization efficiency, and solves the problem of how to improve the quantization efficiency of the analog-to-digital converter in the image sensor.

[0072] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the scope of protection of the claims.

Claims

1. A successive approximation single slope analog-to-digital converter, characterized in that: include: A high-bit analog-to-digital conversion module is used to perform successive approximation conversion on the pixel signal to obtain high-bit conversion data and remaining pixel data; The high-bit analog-to-digital conversion module includes a switch capacitor array, a comparator, a logic control circuit and a prediction circuit; the input end of the switch capacitor array receives a pixel signal, and the upper plate of the switch capacitor array is connected to the first input end of the comparator; the second input end of the comparator receives a common mode voltage; the output end of the comparator is respectively connected to the logic control circuit and the prediction circuit; the logic control circuit is connected to the prediction circuit; the prediction circuit is connected to the switch capacitor array, so that under the control of the logic control circuit and the comparator, the prediction circuit controls the lower plate voltage of the switch capacitor array; the prediction circuit outputs high-bit conversion data; The low-bit analog-to-digital conversion module has an input end connected to the output end of the comparator and is used to perform single-slope conversion on the remaining pixel data not converted by the high-bit analog-to-digital conversion module to obtain low-bit conversion data.

2. The successive approximation single slope analog-to-digital converter according to claim 1, characterized in that: The high-bit analog-to-digital conversion module also includes an operational amplifier circuit; the operational amplifier circuit includes a first operational amplifier capacitor, a second operational amplifier capacitor, a first operational amplifier switch, a second operational amplifier switch and an operational amplifier; the first input end of the operational amplifier receives a pixel signal through the first operational amplifier capacitor, and the second input end receives a common-mode voltage through the second operational amplifier capacitor; the two ends of the first operational amplifier switch are respectively connected to the first input end and the first output end of the operational amplifier, and the two ends of the second operational amplifier switch are respectively connected to the second input end and the second output end of the operational amplifier; the first output end of the operational amplifier is connected to the first input end of the comparator, and the second output end of the operational amplifier is connected to the second input end of the comparator.

3. The successive approximation single slope analog-to-digital converter according to claim 1, characterized in that: The switch capacitor array includes M+1 switch capacitor branches connected in parallel; each of the switch capacitor branches includes a switching switch and a sampling capacitor connected in series, which are used to perform high M-bit quantization on the pixel signal, and the switching switch is used to switch to different reference voltages or ramp voltages under the control of the prediction circuit; wherein M is an integer greater than or equal to 3.

4. The successive approximation single slope analog-to-digital converter according to claim 3, characterized in that: In the row readout process of the successive approximation type single slope analog-to-digital converter, if the currently readout pixel is located in the first row, the prediction circuit is not started, otherwise, the prediction circuit is started; When the prediction circuit is started, the prediction circuit uses the high k-bit conversion data obtained from the previous row of pixel conversion as the prediction value for the current row of pixel conversion, and uses the prediction value to control the switching capacitor branch corresponding to the high k bits to output the prediction voltage to the comparator for comparison; wherein k is an integer greater than or equal to 1 and less than or equal to M.

5. The successive approximation single slope analog-to-digital converter according to claim 4, characterized in that: The prediction circuit includes a prediction value storage circuit, a selection judgment circuit and a prediction result judgment circuit; the prediction value storage circuit is used to store the high k-bit conversion data obtained by converting the previous row of pixels; the selection judgment circuit is used to read the high k-bit conversion data from the prediction value storage circuit, and receive the M-bit control data output by the logic control circuit to output the M+1-bit prediction result; the prediction result judgment circuit is used to judge whether the prediction is successful based on the comparison result output by the comparator and the prediction result output by the selection judgment circuit, and generate a comparator control signal based on the judgment result.

6. The successive approximation single slope analog-to-digital converter according to claim 5, characterized in that: The selection judgment circuit includes k triggers, k AND gates and M+1 dual-way selectors; the input end of each of the triggers is respectively connected to one bit of the high k-bit conversion data, and the output end is connected to the first input end of an AND gate; the second input end of each of the AND gates is connected to the inverted first row trigger signal; the first input ends of the M dual-way selectors are respectively connected to one bit of the M-bit control data output by the logic control circuit, the first input end of the M+1th dual-way selector is grounded, the second input ends of the k dual-way selectors are connected to the output end of the AND gate, the second input ends of the M-k+1 dual-way selectors are connected to the power supply, and the output end of the dual-way selector outputs the prediction result data.

7. The successive approximation register single slope analog-to-digital converter according to claim 6, characterized in that: The selection judgment circuit also includes a selection signal generating circuit; the selection signal generating circuit includes a first selection signal generating unit and a second selection signal generating unit; the first selection signal generating unit is used to generate a first selection signal according to the inverted first row trigger signal and the first prediction enable signal; the second selection signal generating unit is used to generate a second selection signal according to the inverted first row trigger signal and the second prediction enable signal; the first selection signal is the selection signal of the k dual-way selectors connected to the AND gate, and the second selection signal is the selection signal of the remaining M-k+1 dual-way selectors.

8. The successive approximation register single slope analog-to-digital converter according to claim 5, characterized in that: The prediction result judgment circuit includes a first trigger, a second trigger, a first dual-way selector, a second dual-way selector, a NOT gate, a first AND gate, a second AND gate and an OR gate; the input end of the first trigger and the input end of the second trigger are connected to the output end of the comparator; the output end of the first trigger is connected to the first input end of the first AND gate, and the output end of the second trigger is connected to the second input end of the first AND gate through the NOT gate; the output end of the first AND gate is connected to the selection end of the first dual-way selector; the two input ends of the first dual-way selector are respectively connected to the first comparator enable signal and the second comparator enable signal; the two input ends of the second dual-way selector are respectively connected to the first prediction enable signal and the ground, and the selection end is connected to the conversion data of the previous row of pixels after inversion; the input end of the OR gate is connected to the third comparator enable signal, the output end of the first dual-way selector and the output end of the second dual-way selector; the input ends of the second AND gate are respectively connected to the clock signal and the output end of the OR gate; the output end of the second AND gate outputs the comparator clock signal, and the comparator control signal includes the comparator clock signal.

9. A readout circuit, characterized in that: It comprises a successive approximation single slope analog-to-digital converter as described in any one of claims 1 to 8.

10. An image sensor, characterized in that: Comprising a readout circuit as claimed in claim 9.

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