Low-power-consumption reading circuit based on pixel signal prediction and CMOS image sensor

Abstract

The invention discloses a low-power-consumption reading circuit based on pixel signal prediction and a CMOS image sensor, the low-power-consumption reading circuit comprises a ramp generator, a comparator, a logic circuit and a counter, the positive phase input end of the comparator receives a ramp signal of the ramp generator, the negative phase input end of the comparator receives a pixel signal, and the logic circuit is connected with the counter. The comparator predicts and compares the input pixel signal according to the ramp signal, and outputs a prediction signal and a comparison signal; the logic circuit separates the prediction signal output by the comparator from the comparison signal, feeds the prediction signal back to the comparator, and outputs a generated prediction window to the counter; the counter quantizes the pixel signal based on the prediction window generated by the logic circuit and outputs the quantized pixel signal. According to the invention, the pixel signals are predicted and compared through only one comparator, and the prediction window is generated, so that the low n-bit counter only needs to work in the prediction window, the turnover frequency of the counter is greatly reduced, and the dynamic power consumption of the reading circuit is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and particularly to a low-power readout circuit structure and a CMOS image sensor under the imaging conditions of a high-speed and high-precision CMOS image sensor. Background Art

[0002] Column-parallel single-slope analog-to-digital converters (SS ADCs) have been widely used in CMOS image sensors (CISs) due to their advantages such as simple structure and high linearity. With the continuous improvement of integration, operating frequency, and quantization accuracy, the power consumption of traditional column-parallel SS ADCs has become increasingly difficult to control, becoming one of the main factors affecting imaging quality and reducing device lifespan. The power consumption of SS ADCs mainly comes from two aspects. On the one hand, it is the static power consumption of the comparator, and on the other hand, it is the dynamic power consumption of the counter. In terms of static power consumption, since it is not affected by frequency, extremely low power consumption can be achieved by reducing the comparator current; in terms of dynamic power consumption, limited by the operating mode of the SS ADC, the counter needs to flip multiple times for each signal quantization, especially for low bit positions, which generates a large amount of power consumption. With the gradual increase of the operating frequency and quantization accuracy of CMOS image sensors, this problem is particularly serious. Therefore, how to achieve an ultra-low-power counting method remains a difficult point for SS ADCs at present. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies and defects of the prior art, and provide a low-power readout circuit and a CMOS image sensor based on pixel signal prediction. By proposing an offset comparator structure, it is possible to predict pixel signals while maintaining the performance of the comparator, so as to reduce the working time of the counter, reduce its number of flips, and thereby reduce the dynamic power consumption of the counter.

[0004] An object of the present invention is to provide a low-power readout circuit based on pixel signal prediction, including a ramp generator, a comparator, a logic circuit, and a counter. The positive input terminal of the comparator receives the ramp signal of the ramp generator, and the negative input terminal of the comparator receives the pixel signal. The comparator is used to predict and compare the input pixel signal according to the ramp signal, and output a prediction signal and a comparison signal; the logic circuit is used to separate the prediction signal and the comparison signal output by the comparator, feedback the prediction signal back to the comparator, and output the generated prediction window to the counter; the counter quantizes the pixel signal based on the prediction window output by the logic circuit and outputs the quantized pixel signal.

[0005] Among them, the comparator includes a two-stage operational amplifier module. The first-stage operational amplifier module is a five-transistor operational amplifier structure with an offset structure, and the second-stage operational amplifier module is a common-source operational amplifier structure.

[0006] Among them, the comparator includes MOS transistors M1 - M9, switches clk1, clk2, S1, AZ1, AZ2, capacitors C1, C2; the source of MOS transistor M1 is grounded, the gate is connected to the first-stage bias voltage signal Vb of the comparator through switch S1, and the drain is connected to the sources of MOS transistors M2 and M3; the drain of MOS transistor M2 is connected to switch clk2, one end of AZ1, and the drain of MOS transistor M6. The drain of MOS transistor M6 is connected to its gate, and the sources of MOS transistors M6, M7, and M8 are connected to the power supply voltage VDD. The gate of MOS transistor M6 is connected to the gate of MOS transistor M7. The drain of MOS transistor M7 is connected to the gate of MOS transistor M8. The other end of switch clk2 is connected to the drain of MOS transistor M4. After passing through a capacitor C1, the ramp signal is connected to the other end of switch AZ1, and the gates of MOS transistors M2 and M4. The source of MOS transistor M4 is connected to the source of MOS transistor M2 and is connected to one end of capacitor C2. The other end of capacitor C2 is grounded; the sources of MOS transistors M3 and M5 are connected and are connected to one end of another capacitor C2. The other end of the other capacitor C2 is grounded. The drain of MOS transistor M3 is connected to switch clk1, one end of another switch AZ1, and the drain of MOS transistor M7. The other end of switch clk1 is connected to the drain of MOS transistor M5. The other end of another switch AZ1 is connected to the gates of MOS transistors M3 and M5. The pixel signal is connected to the gates of MOS transistors M3 and M5 after passing through a capacitor; the drain of MOS transistor M8 is connected to V OUT , one end of switch AZ2, and the drain of MOS transistor M9. The source of MOS transistor M9 is grounded, and the gate is connected to the other end of switch AZ2.

[0007] Among them, MOS transistors M2 and M3 are input pairs of the same size.

[0008] Among them, MOS transistors M4 and M5 are offset pairs of the same size.

[0009] Among them, the counter includes a low n-bit counter and a high m-bit counter; the prediction window is output to the low n-bit counter, so that the low n-bit counter starts counting when the prediction signal arrives and stops counting when the comparison signal arrives.

[0010] Among them, when the ramp starts, the high m-bit counter starts counting. When the prediction signal arrives, the low n-bit counter starts counting. After the comparison signal arrives, the high m-bit counter and the low n-bit counter stop counting. At this time, the output code value of each bit of the counter is the quantization code value of the pixel signal.

[0011] Among them, the clock frequency of the counter is set to: the counter clock frequency is X Hz, then the frequency of the input clock CLK_L of the low n-bit counter is X Hz, and the frequency of the input clock CLK_M of the high m-bit counter is X / 2 n Hz.

[0012] Among them, the counter is composed of a BWI module, D flip-flops, registers, and an output buffer circuit connected in sequence; the BWI module flips the code value of the input reset signal according to the clock signal, performs two's complement operation to achieve digital correlated double sampling, the D flip-flops count according to the input signal of the BWI module and output the quantization result, the registers store the quantization result output by the D flip-flops according to the latch control signal, and the output buffer circuit outputs the digital code according to the output signal of the registers and the conversion output signal

[0013] Another object of the present invention is to provide a CMOS image sensor including the low-power readout circuit based on pixel signal prediction.

[0014] The present invention utilizes the characteristics of the comparator, realizes the prediction of the pixel signal by adjusting the size of the input pair transistors, and then completes the quantization of the pixel signal through a two-step counter; compared with the traditional readout circuit, only one comparator is used to predict and compare the pixel signal to generate a prediction window, so that the low n-bit counter only needs to work in the prediction window, greatly reducing the number of flips of the counter and reducing the dynamic power consumption of the readout circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is the working principle diagram of the low-power ADC based on pixel prediction of the present invention.

[0016] Figure 2 is the structural diagram of the low-power ADC based on pixel signal prediction of the present invention.

[0017] Figure 3 is the basic circuit structural diagram of the offset comparator of the present invention.

[0018] Figure 4 is the basic circuit structural diagram of the BWI counter of the present invention.

[0019] Figure 5 is the timing diagram of the readout circuit of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0021] The present invention predicts pixel signals and adjusts the effective working range of a counter through prediction. The basic logic is that for an SS ADC with N=n+m-bit precision, the counter adopts a two-step structure. Among them, the low n-bit counter is only enabled when the predicted signal arrives and only needs to work within a small range of the prediction window (PW), while the high m-bit counter counts normally, so as to reduce the number of counter flips and lower the power consumption.

[0022] The key of the present invention lies in reasonably predicting pixel signals and generating a prediction window with a stable size. Each pixel signal is an unknown quantity before comparison, so it is difficult to make a reasonable prediction for it. The existing methods mainly predict it by adding additional ramps or comparators, which will increase the complexity of the circuit and cause additional area and power consumption waste.

[0023] The present invention uses a comparator to realize the prediction and comparison of pixel signals. The basic low-power readout circuit structure is as Figure 2 shown. The overall circuit mainly consists of a ramp generator, a comparator, a two-step counter, and a logic circuit. Among them, the comparator realizes the prediction and comparison of pixel signals; the logic circuit is used to separate the prediction signal and the comparison signal; the two-step counter realizes the quantization of pixel signals.

[0024] The comparator in the present invention is a two-stage operational amplifier. The first stage is a five-transistor operational amplifier with an offset structure, and the second stage is a common-source operational amplifier. Its circuit structure is as Figure 3 shown.

[0025] Usually, a comparator adopts a symmetric structure to ensure that comparison occurs when the voltages at the positive and negative input terminals are equal. When the comparator is no longer symmetric, that is, when the input pair transistor sizes are asymmetric, the critical comparison point will shift. For example, when the size of the negative terminal of the comparator is larger than that of the positive input terminal, a larger current will flow through the negative terminal, and the critical comparison point will also shift towards the negative terminal. Therefore, when the voltage at the negative terminal remains unchanged, a larger voltage is required at the positive terminal to compare with it.

[0026] Therefore, the present invention utilizes the characteristics that different input pair transistor size ratios of the comparator result in different critical comparison points, and realizes the regulation of the input pair transistor size ratio of the comparator by shunting adjustable offset pair transistors on both sides of the input pair transistors. As Figure 3 shown, in the circuit structure of the present invention, M2 and M3 are input pair transistors of the same size, M4 and M5 are offset pair transistors of the same size, and they are all NMOS transistors. Figure 3 In the circuit of , M6 and M7, M8 are PMOS transistors, and the others are NMOS transistors.

[0027] Refer to Figure 3In the shown circuit structure, when the comparator is working normally, the offset transistor is disconnected from the circuit; when the comparator predicts the pixel signal, one end of the input pair transistor needs to be connected to the offset transistor, making the two ends of the comparator asymmetric, causing an offset and changing its critical comparison point; to ensure the symmetry of the comparator during reset, the other end of the input pair transistor also needs to be connected to the offset transistor; at the same time, to suppress the non-ideal factors introduced when the offset transistor is connected or disconnected from the circuit, a capacitor C2 is directly connected between the sources of M4 and M5 and the ground for suppression.

[0028] Under the premise of ensuring its performance, the offset comparator structure of the present invention can realize the prediction and comparison of pixel signals, and the prediction window can be adjusted by the size ratio of the offset transistor to the input pair transistor.

[0029] The logic circuit in the present invention is mainly used to separate the predicted signal and the comparison signal output by the comparator, feedback the predicted signal back to the comparator, and disconnect the offset transistor; at the same time, the generated prediction window is output to the counter to control the counter to complete the quantization of the signal.

[0030] The counter circuit in the present invention consists of two-step counters, which are two counters with different operating frequencies. According to the size of the prediction window, they can be divided into a low n-bit counter and a high m-bit counter. The low n-bit counter performs counting operations within the time range of the prediction window, and the high m-bit counter starts working when the ramp signal starts. Its circuit structure is as Figure 4 shown. The counter in the present invention consists of a BWI module, D flip-flops, registers, and an output buffer circuit. Among them, the BWI module flips the code value of the reset signal, performs two's complement operations, and realizes digital correlated double sampling. The D flip-flops perform counting, and the registers store the quantization results.

[0031] The working principle of the two-step counter of the present invention is that when the ramp starts, the high m-bit counter starts counting. After the predicted signal arrives, the low n-bit counter starts counting. After the comparison signal arrives, the high m-bit counter and the low n-bit counter stop counting. At this time, the output code value of each bit of the counter is the quantization code value of the pixel signal.

[0032] Among them, if the counter clock frequency is X Hz, then the input clock CLK_L frequency of the low n-bit counter is X Hz, and the input clock CLK_M frequency of the high m-bit counter is X / 2 n Hz. Among them, the low n-bit counter has a high working frequency and many flip times, which is the main source of the dynamic power consumption of the counter. This two-step counter can make the low n-bit counter only work within the prediction window, reducing the power consumption of the counter.

[0033] The present invention utilizes the offset characteristic of a comparator to propose an offset comparator structure, which can effectively predict pixel signals. By using the predicted signal to regulate the working range of a counter, the low n-bit counter only needs to work within the prediction window, greatly reducing the number of counter flips and significantly reducing the dynamic power consumption of the counter, thereby realizing a low-power readout circuit for a CMOS image sensor, especially under high-speed and high-precision imaging conditions.

[0034] Figure 5 The basic working timing circuit diagram of the low-power readout circuit of the present invention is given. Combining the circuit structure diagram, the comparator, and the counter circuit diagram, its basic working process is as follows:

[0035] First, before the comparator is reset, both switches clk1 and clk2 are closed, and the offset transistors are symmetrically connected to the comparator circuit to ensure the stability of the reset point and generate a suitable reset voltage to make the comparator circuit work stably. After the reset is completed, the comparator first quantifies the reset signal. Before the ramp starts, switch clk2 is disconnected. At this time, only the negative input terminal of the comparator is connected to the offset transistor, and the comparator is offset. At this time, the pixel signal is equivalent to Vpixel’ in the timing circuit diagram. The ramp signal will be compared at a point greater than the pixel signal to generate a predicted signal Vpre. This predicted signal Vpre is fed back through the subsequent logic circuit, and the clock clk1 is turned off, so that both offset transistors are disconnected from the comparator, and the critical comparison point is restored. Until the ramp signal is the same as the pixel signal, a comparison occurs to generate a comparison signal Vcomp. When quantifying the pixel signal, the clock clk1 is closed again to offset the comparator, and then the corresponding predicted signal and comparison signal are generated through the same process.

[0036] In the present invention, the logic circuit separates the output signal Vop into a predicted signal Vpre and a comparison signal Vcomp according to the output signal Vop of the comparator, and feeds the predicted signal back to the comparator. At the same time, after processing the predicted signal and the lowest bit clock signal of the high m-bit counter, a prediction window is generated. The prediction window is the time period from generating the predicted signal to generating the comparison signal. This prediction window is output to the low n-bit counter in the two-step counter, causing it to start counting when the predicted signal arrives and stop counting when the comparison signal arrives. The high m-bit counter normally counts when the ramp signal starts and stops counting when the comparison signal arrives.

[0037] The present invention combines the high m-bit and low n-bit counters and realizes digital CDS through the BWI module to output the final quantized code value and realize the quantization of pixel signals.

[0038] Since the clock frequency of the lower n-bit of the counter is high and the counter flips frequently, which is the main source of the dynamic power consumption of the counter, while the clock frequency of the higher m-bit is low and the counter flips less frequently, resulting in less dynamic power consumption. Therefore, without introducing additional circuits basically, the present invention can greatly reduce the number of counter flips and significantly reduce the dynamic power consumption of the counter.

[0039] Another object of the embodiments of the present invention is to provide a CMOS image sensor, including the low-power readout circuit based on pixel signal prediction.

[0040] The foregoing has shown and described the basic principles, main features and advantages of the present invention. For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms.

[0041] Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced by the present invention.

[0042] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A low power readout circuit based on pixel signal prediction, characterized in that: The invention comprises a ramp generator, a comparator, a logic circuit and a counter, wherein the positive input terminal of the comparator receives a ramp signal of the ramp generator, the negative input terminal of the comparator receives a pixel signal, the comparator is used to predict and compare the input pixel signal according to the ramp signal, and output a prediction signal and a comparison signal; the logic circuit is used to separate the prediction signal and the comparison signal output by the comparator, feed the prediction signal back to the comparator, and output the generated prediction window to the counter; the counter quantizes the pixel signal based on the prediction window generated by the logic circuit, and outputs the quantized pixel signal.

2. The low power consumption readout circuit based on pixel signal prediction according to claim 1, characterized in that: The comparator comprises a two-stage operational amplifier module, the first stage operational amplifier module is a five-transistor operational amplifier structure with an offset structure, and the second stage operational amplifier module is a common source operational amplifier structure.

3. The low power consumption readout circuit based on pixel signal prediction according to claim 2, characterized in that: The comparator includes MOS tubes M1-M9, switches clk1, clk2, S1, AZ1, AZ2, capacitors C1 and C2; the source of MOS tube M1 is grounded, the gate is connected to the first-stage bias voltage signal Vb of the comparator through switch S1, and the drain is connected to the source of MOS tubes M2 and MOS tubes M3; the drain of MOS tube M2 is connected to one end of switches clk2 and AZ1 and the drain of MOS tube M6, the drain of MOS tube M6 is connected to the gate, and the sources of MOS tube M6, MOS tube M7 and MOS tube M8 are connected to the power supply voltage VDD, the gate of MOS tube M6 is connected to the gate of MOS tube M7, the drain of MOS tube M7 is connected to the gate of MOS tube M8, the other end of switch clk2 is connected to the drain of MOS tube M4, and the ramp signal After passing through a capacitor C1, it is connected to the other end of the switch AZ1, the gates of the MOS tube M2 and the MOS tube M4. The source of the MOS tube M4 is connected to the source of the MOS tube M2 and to one end of the capacitor C2, and the other end of the capacitor C2 is grounded; the MOS tube M3 is connected to the source of the MOS tube M5 and to one end of another capacitor C2, and the other end of the other capacitor C2 is grounded. The drain of the MOS tube M3 is connected to the switch clk1, one end of another switch AZ1 and the drain of the MOS tube M7. The other end of the switch clk1 is connected to the drain of the MOS tube M5, and the other end of the other switch AZ1 is connected to the gates of the MOS tubes M3 and M5. After passing through a capacitor, the pixel signal is connected to the gates of the MOS tubes M3 and M5; the drain of the MOS tube M8 is connected to V OUT , one end of the switch AZ2 and the drain of the MOS tube M9, the source of the MOS tube M9 is grounded, and the gate is connected to the other end of the switch AZ2.

4. The low power consumption readout circuit based on pixel signal prediction according to claim 1, characterized in that: The MOS tube M2 and the MOS tube M3 are input pairs of tubes of the same size.

5. The low power consumption readout circuit based on pixel signal prediction according to claim 1, characterized in that: The MOS tube M4 and the MOS tube M5 are offset pairs of tubes of the same size.

6. The low power consumption readout circuit based on pixel signal prediction according to claim 1, characterized in that: The counter includes a low n-bit counter and a high m-bit counter; the prediction window is output to the low n-bit counter, so that the low n-bit counter starts counting when the prediction signal arrives and stops counting when the comparison signal arrives.

7. The low power consumption readout circuit based on pixel signal prediction according to claim 7, characterized in that: When the ramp starts, the high m-bit counter starts counting. When the prediction signal arrives, the low n-bit counter starts counting. After the comparison signal arrives, the high m-bit counter and the low n-bit counter stop counting. At this time, the output code value of each bit of the counter is the quantization code value of the pixel signal.

8. The low power consumption readout circuit based on pixel signal prediction according to claim 7, characterized in that: The clock frequency of the counter is set to: counter clock frequency X Hz, then the frequency of the low n-bit counter input clock CLK_L is X Hz, and the frequency of the high m-bit counter input clock CLK_M is X / 2 n Hz.

9. The low power consumption readout circuit based on pixel signal prediction according to claim 6 is characterized in that: The counter is composed of a BWI module, a D flip-flop, a register and an output buffer circuit which are connected in sequence; the BWI module flips the code value of the input reset signal according to the clock signal, performs a complement operation, and realizes digital correlated double sampling; the D flip-flop counts and outputs a quantization result according to the input signal of the BWI module; the register stores the quantization result output by the D flip-flop according to a latch control signal; and the output buffer circuit outputs a digital code according to the output signal of the register and the converted output signal.

10. A CMOS image sensor, characterized in that: The invention comprises a low-power readout circuit based on pixel signal prediction as described in any one of claims 1 to 9.

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