Split-gate memory and forming method thereof

Abstract

The invention discloses a split-gate memory and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a device region and a logic region which are adjacent to each other; depositing and forming a plurality of mutually discrete memory gates on the device region; sequentially forming a metal selection gate material layer and a first photoresist layer on the device region; exposing and developing the first photoresist layer to form the first photoresist layer with a metal selection gate pattern; the first photoresist layer with the metal selection gate pattern is used as a mask, the metal selection gate material layer is etched until the surface of the device area is exposed, a plurality of discrete metal selection gates are formed, and the metal selection gates are adjacent to the storage gates. As the surface of the metal selection gate is smooth, the interface quality between the metal selection gate and the channel in the substrate of the device region can be improved, scattering of carriers in the substrate of the device region is reduced, the carrier mobility and the channel current are further improved, the driving capability of the split-gate memory device is enhanced, and the performance of the split-gate memory is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular, to a split-gate memory and a method for forming the same. Background Art

[0002] The storage unit of a SONOS device usually consists of a SONOS storage transistor (simply referred to as a storage transistor) and a high-voltage selection transistor (simply referred to as a selection transistor). Among them, the storage transistor is used to store data, and the selection transistor is used to complete the selection of data addresses. Both transistors are in the same well region. Among them, the SONOS device also includes a Split-gate memory. The Split-gate structure divides the single gate in a traditional MOSFET into two or more parts, and each part can be independently controlled. For example, in the Split-gate memory, one gate is used to control charge storage (storage gate), and the other gate is used to control the read operation (selection gate).

[0003] However, the performance of the current split-gate memory needs to be improved. Summary of the Invention

[0004] The technical problem solved by the present invention is how to improve the performance of the split-gate memory.

[0005] To solve the above technical problem, an embodiment of the present invention provides a method for forming a split-gate memory, including: providing a substrate, the substrate including an adjacent device region and a logic region; depositing and forming a plurality of discrete storage gates on the device region; sequentially forming a metal selection gate material layer and a first photoresist layer on the device region; exposing and developing the first photoresist layer to form a first photoresist layer with a metal selection gate pattern; using the first photoresist layer with the metal selection gate pattern as a mask to etch the metal selection gate material layer until the surface of the device region is exposed, forming a plurality of discrete metal selection gates, and the metal selection gates are adjacent to the storage gates.

[0006] Optionally, the method for forming the split-gate memory further includes: sequentially forming a peripheral metal selection gate material layer and a second photoresist layer on the logic region; exposing and developing the second photoresist layer to form a second photoresist layer with a peripheral metal selection gate pattern; using the second photoresist layer with the peripheral metal selection gate pattern as a mask to etch the peripheral metal selection gate material layer until the surface of the logic region is exposed, forming a peripheral metal selection gate.

[0007] Optionally, the metal selection gate and the peripheral metal selection gate are formed simultaneously.

[0008] Optionally, the process of forming the metal select gate material layer and the peripheral metal select gate material layer is a chemical vapor deposition process, and the process parameters of the chemical vapor deposition process are as follows: the deposition temperature is 300°C to 500°C, and the deposition gas is WF 6 , H 2 and SiH 4 or a combination of one or more of them, and the deposition rate is 50 Å / min to 200 Å / min.

[0009] Optionally, before the step of forming the metal select gate material layer and the peripheral metal select gate material layer, the method further includes: forming an adhesion layer on the substrate.

[0010] Optionally, the materials of the metal select gate and the peripheral metal select gate include one or more combinations of tungsten, aluminum, and cobalt, the material of the adhesion layer includes titanium nitride, and the width range of the metal select gate is 50 nanometers to 60 nanometers.

[0011] Optionally, before the step of forming the first photoresist layer, the method further includes: planarizing the metal select gate material layer until the top surface of the storage gate is exposed.

[0012] Optionally, before the step of forming the storage gate, the method further includes: forming a storage gate oxide layer on the substrate; before the step of forming the metal select gate, the method further includes: forming a metal select gate oxide layer on the substrate surface and the sidewalls of the storage gate, and the metal select gate oxide layer is located between the storage gate and the metal select gate; after the step of forming the metal select gate, the method further includes: forming sidewalls on the sidewalls of the metal select gate and the sidewalls of the storage gate; using the metal select gate, the storage gate, and the sidewalls as masks to perform ion implantation on the substrate to form source / drain regions.

[0013] Optionally, the method for forming the split-gate memory further includes: forming an interlayer dielectric layer on the substrate; etching the interlayer dielectric layer until the surface of the source / drain region is exposed to form a plurality of openings; forming a metal silicide layer at the bottom of the openings; filling a conductive material into the openings to form conductive plugs.

[0014] Correspondingly, the present invention further provides a split-gate memory, including: a substrate, the substrate includes adjacent device regions and logic regions; storage gates, located on the device regions, and a plurality of the storage gates are discrete from each other; a metal select gate, located on the device regions, and the metal select gate is adjacent to the storage gates.

[0015] Optionally, the split-gate memory further includes: a peripheral metal select gate, located on the logic region; an adhesion layer, located between the substrate and the metal select gate, and between the substrate and the peripheral metal select gate.

[0016] Optionally, the materials of the metal select gate and the peripheral metal select gate include one or a combination of tungsten, aluminum, and cobalt, the material of the adhesion layer includes titanium nitride, and the width range of the metal select gate is 50 nanometers to 60 nanometers.

[0017] Optionally, the split-gate memory further includes: a storage gate oxide layer located between the substrate and the storage gate; a metal select gate oxide layer located on the surface of the substrate, on the sidewalls of the storage gate, and between the storage gate and the metal select gate; sidewalls located on the sidewalls of the metal select gate and the sidewalls of the storage gate; source / drain regions located in the substrate on both sides of the storage gate and the metal select gate.

[0018] Optionally, it further includes: an interlayer dielectric layer located on the substrate; an opening located in the interlayer dielectric layer, and the opening exposes the surface of the source / drain region; a metal silicide layer located at the bottom of the opening; and a conductive plug located in the opening, and the conductive plug is electrically connected to the metal silicide layer.

[0019] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0020] The technical solution of the present invention forms a metal select gate on the substrate in the device region. Since the surface of the metal select gate is smooth, it can improve the interface quality between the metal select gate and the channel in the substrate of the device region, reduce the scattering of carriers in the substrate of the device region, and thus improve the carrier mobility and channel current, thereby enhancing the driving ability of the split-gate memory device and improving the performance of the split-gate memory; and when realizing the same electrical function, adopting the structure of the metal select gate, the required width of the metal select gate is smaller than that of the polysilicon select gate structure in the prior art, thereby reducing the width of the metal select gate and the volume of the split-gate memory and improving the integration degree of the split-gate memory.

[0021] Furthermore, in the technical solution of the present invention, by forming a peripheral metal select gate on the substrate in the peripheral region, since the surface of the peripheral metal select gate is smooth, it can improve the interface quality between the peripheral metal select gate and the channel in the substrate of the peripheral region, reduce the scattering of carriers in the substrate of the peripheral region, and thus improve the carrier mobility and channel current, thereby enhancing the driving ability of the devices in the peripheral region; in addition, the peripheral metal select gate and the metal select gate are formed simultaneously, reducing the manufacturing cost and improving the manufacturing efficiency. Description of the Drawings

[0022] Figure 1 is a schematic structural diagram of a split-gate memory;

[0023] Figures 2 to 9It is a schematic diagram of the formation process of a split-gate memory in an embodiment of the present invention. Detailed implementation manners

[0024] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0025] For the current Split-gate memory structure, please refer to Figure 1 , the split-gate memory structure includes: a substrate; a storage gate 202 located on the substrate; a select gate 201 located on the substrate, and the select gate 201 is adjacent to the storage gate 202.

[0026] It should be noted that the storage gate 202 is used to control charge storage, and the select gate 201 is used to control the read operation.

[0027] In the above solution, the material of the select gate 201 is polysilicon. When an external electric field is applied, a depletion layer will be formed at the interface between the polysilicon and the oxide layer on the substrate, which will reduce the effective width of the channel, limit the space for carriers to pass through, and thus reduce the channel current, affecting the performance of the memory.

[0028] To solve the above technical problems, the present invention provides a split-gate memory and a method for forming the same. By forming a metal select gate on the substrate in the device region, since the surface of the metal select gate is smooth, it can improve the interface quality between the metal select gate and the inner channel of the substrate in the device region, reduce the scattering of carriers in the substrate in the device region, and thus improve the carrier mobility and channel current, thereby enhancing the driving ability of the split-gate memory device and improving the performance of the split-gate memory; and in the case of realizing the same electrical function, adopting the structure of the metal select gate, the required width of the metal select gate is smaller than that of the polysilicon select gate structure in the prior art, thereby reducing the width of the metal select gate and the volume of the split-gate memory, and improving the integration degree of the split-gate memory.

[0029] To make the above objects, features and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0030] Figures 2 to 9 It is a schematic diagram of the formation process of a split-gate memory in an embodiment of the present invention.

[0031] Please refer to Figure 2 , a substrate 100 is provided, and the substrate 100 includes an adjacent device region I and a logic region II.

[0032] In some embodiments of the present invention, it further includes: forming an isolation region 101 in the substrate 100; forming a storage gate oxide layer 102 on the surface of the substrate 100.

[0033] The method for forming the isolation region 101 includes: etching the substrate 100 to form a shallow trench (not shown in the figure); forming the isolation region 101 in the shallow trench.

[0034] In some embodiments of the present invention, the process of etching the substrate 100 uses a dry etching process, and the process parameters of the dry etching process are: the pressure in the chamber is 5 mT to 15 mT, the source power is 350 W to 1200 W, the bias voltage is 150 V to 600 V, the gas flow rate is 20 sccm to 200 sccm, and the etching time is 8 s to 60 s.

[0035] In this embodiment, the thickness range of the shallow trench (not shown in the figure) is 3200 Å to 3400 Å.

[0036] In some embodiments of the present invention, the shallow trench is filled by a chemical vapor deposition process to form the isolation region 101.

[0037] In this embodiment, the material of the isolation region 101 is silicon oxide, the shape of the isolation region 101 is an inverted trapezoid, and the isolation region 101 is used to avoid electrical crosstalk between adjacent active devices.

[0038] Specifically, the thickness of the isolation region 101 above the surface of the substrate 100 is 0 Å to 80 Å.

[0039] In other embodiments of the present invention, it further includes: removing the isolation region above the substrate surface through a planarization process.

[0040] The process of the planarization process uses a chemical mechanical polishing process. Specifically, by adjusting the process parameters of the chemical mechanical polishing, it can be ensured that the isolation region 101 above the surface of the substrate 100 is removed during the polishing process and stops at a surface flush with the substrate 100.

[0041] Among them, the thickness range of the storage gate oxide layer 102 is 50 Å to 70 Å.

[0042] The method for forming the storage gate oxide layer 102 includes: using a chemical vapor deposition process to sequentially form a charge tunneling layer 1023, a charge trapping layer 1022, and a charge blocking layer 1021 on the substrate 100.

[0043] In some embodiments of the present invention, the materials of the charge tunneling layer 1023 and the charge blocking layer 1021 are silicon oxide, and the material of the charge trapping layer 1022 is silicon nitride.

[0044] Among them, the charge tunneling layer 1023 is used to precisely control the entry and exit of electrons from the charge trapping layer 1022 to ensure the accuracy of data writing and erasing; the charge trapping layer 1022 is used to capture and retain electrons to represent the state of the storage cell; the charge blocking layer 1021 is used to prevent charge leakage from the gate to the charge trapping layer 1022.

[0045] Please refer to Figure 3 , a storage gate material layer 1031 is formed on the substrate 100.

[0046] In some embodiments of the present invention, the storage gate material layer 1031 is formed by a chemical vapor deposition process.

[0047] In this embodiment, the thickness range of the storage gate material layer 1031 is from 950 angstroms to 1050 angstroms, and the material of the storage gate material layer 1031 is single-crystalline silicon or polycrystalline silicon.

[0048] In this embodiment, a third photoresist layer 1032 is formed on the storage gate material layer 1031; the third photoresist layer 1032 is exposed and developed to form a third photoresist layer 1032 with a storage gate 103 pattern.

[0049] Please refer to Figure 4 , a plurality of discrete storage gates 103 are deposited and formed on the device region I.

[0050] In some embodiments of the present invention, the method for forming a plurality of discrete storage gates 103 includes: using the third photoresist layer 1032 with a storage gate 103 pattern as a mask, sequentially etching the storage gate material layer 1031, the charge blocking layer 1021, and the charge trapping layer 1022 until the charge tunneling layer 1023 is exposed, thereby forming a plurality of discrete storage gates 103.

[0051] In a specific embodiment, the bottom of the storage gate 103 has a storage gate oxide layer 102, and the substrate 100 has the charge tunneling layer 1023.

[0052] In some embodiments of the present invention, the storage gate material layer 1031 is etched away by a dry etching process until the substrate 100 is exposed. The parameters of the dry etching process include: the pressure of the chamber is from 5.5 mT to 50 mT, the source power is from 180 W to 1000 W, the etching gas includes CH 2 F 2 , Cl 2 , HBr, He, and O 2 in combination of one or more of them, the gas flow rate is from 20 sccm to 200 sccm, and the etching time is from 6 s to 40 s.

[0053] In some other embodiments of the present invention, after forming the storage gate 103, it further includes: forming a metal select gate oxide layer 1032 on the substrate 100 and on the surface of the storage gate 103.

[0054] Please refer to Figure 5 , and forming a metal select gate material layer 1041 on the metal select gate oxide layer 1032.

[0055] In some other embodiments of the present invention, it further includes: sequentially forming a peripheral metal select gate material layer 1042 on the logic region II.

[0056] In a specific embodiment, the peripheral metal select gate material layer 1042 and the metal select gate material layer 1041 are formed simultaneously.

[0057] The process of forming the metal select gate material layer 1041 and the peripheral metal select gate material layer 1042 is a chemical vapor deposition process. The process parameters of the chemical vapor deposition process are: the deposition temperature is 300 °C to 500 °C, and the deposition gas is WF 6 、H 2 and SiH 4 or a combination of one or more of them, and the deposition rate is 50 Å / min to 200 Å / min.

[0058] In other embodiments of the present invention, before the step of forming the metal select gate material layer 1041 and the peripheral metal select gate material layer 1042, it further includes: forming an adhesion layer (not shown in the figure) on the substrate 100.

[0059] Among them, the materials of the metal select gate 104 and the peripheral metal select gate 1043 include one or more combinations of tungsten, aluminum, and cobalt. The material of the adhesion layer includes titanium nitride. The width range of the metal select gate 104 is 50 nanometers to 60 nanometers.

[0060] Among them, the thickness range of the adhesion layer is 5 nanometers to 10 nanometers.

[0061] The present invention adopts a metal select gate 104 with a width range of 50 nanometers to 60 nanometers. In the case of achieving the same electrical function, by adopting the structure of the metal select gate, the width of the required metal select gate 104 is smaller than that of the polysilicon select gate structure in the prior art, thereby reducing the width of the metal select gate and the volume of the split-gate memory, and improving the integration degree of the split-gate memory.

[0062] Please refer to Figure 6, the metal select gate material layer 1041 is planarized until the top surface of the storage gate 103 is exposed; a first photoresist layer 1044 is formed on the metal select gate material layer 1041; the first photoresist layer 1044 is exposed and developed to form a first photoresist layer 1044 having a metal select gate 104 pattern.

[0063] In some other embodiments of the present invention, it further includes: forming a second photoresist layer 1045 on the peripheral metal select gate material layer 1042; exposing and developing the second photoresist layer 1045 to form a second photoresist layer 1045 having a peripheral metal select gate 1043 pattern.

[0064] Please refer to Figure 7 , using the first photoresist layer 1044 having a metal select gate 104 pattern as a mask, etching the metal select gate material layer 1041 until the surface of the device region I is exposed, forming a plurality of discrete metal select gates 104, and the metal select gate 104 is adjacent to the storage gate 103.

[0065] In some embodiments of the present invention, it further includes: using the second photoresist layer 1045 having a peripheral metal select gate 1043 pattern as a mask, etching the peripheral metal select gate material layer 1042 until the surface of the logic region II is exposed, forming a peripheral metal select gate 1043.

[0066] In a specific embodiment, the metal select gate 104 and the peripheral metal select gate 1043 are formed simultaneously.

[0067] In some other embodiments of the present invention, it further includes: etching the metal select gate 104 oxide layer on the substrate 100 and the metal select gate oxide layer 1032 on the top surface of the storage gate 103 until the charge tunneling layer 1023 and the top surface of the storage gate 103 are exposed.

[0068] In a specific embodiment, the metal select gate oxide layer 1032 is located at the bottom of the metal select gate 104 and on the sidewall surface between the metal select gate 104 and the storage gate 103. The metal select gate oxide layer 1032 at the bottom of the metal select gate 104 is the gate oxide layer of the metal select gate 104, and the metal select gate oxide layer 1032 on the sidewall surface between the metal select gate 104 and the storage gate 103 is an isolation layer to avoid electrical crosstalk between the metal select gate 104 and the storage gate 103.

[0069] In the above solution, by forming the metal select gate 104 on the substrate 100 in the device region I, since the surface of the metal select gate 104 is smooth, it can improve the interface quality between the metal select gate 104 and the channel in the substrate 100 of the device region I, reduce the scattering of carriers in the substrate 100 of the device region I, thereby improving the carrier mobility and the channel current, enhancing the driving ability of the split-gate memory device, and improving the performance of the split-gate memory; and when achieving the same electrical function, adopting the structure of the metal select gate 104, the required width of the metal select gate 104 is smaller than that of the polysilicon select gate structure in the prior art, thereby reducing the width of the metal select gate 104 and the volume of the split-gate memory, and improving the integration degree of the split-gate memory.

[0070] In addition, in the present invention, by forming the peripheral metal select gate 1043 on the substrate 100 in the peripheral region, since the surface of the peripheral metal select gate 1043 is smooth, it can improve the interface quality between the peripheral metal select gate 1043 and the channel in the substrate 100 of the peripheral region, reduce the scattering of carriers in the substrate 100 of the peripheral region, thereby improving the carrier mobility and the channel current, and enhancing the driving ability of the devices in the peripheral region; in addition, the peripheral metal select gate 1043 and the metal select gate 104 are formed simultaneously, reducing the manufacturing cost and improving the manufacturing efficiency.

[0071] Please refer to Figure 8 , and form spacers 105 on the sidewalls of the metal select gate 104 and the sidewalls of the storage gate 103.

[0072] In other embodiments of the present invention, before the step of forming the spacers 105, it further includes: forming an oxide layer (not shown in the figure) on the sidewall surfaces and the top surfaces of the storage gate 103, the sidewall surfaces and the top surfaces of the metal select gate 104, and the sidewall surfaces and the top surfaces of the peripheral metal select gate 1043; performing a first ion implantation on the substrate 100 using the oxide layer as a mask to form a lightly doped region 1091.

[0073] In a specific embodiment, the material of the oxide layer (not shown in the figure) is silicon oxide and silicon nitride, the spacers 105 are located on the sidewall surfaces of the oxide layer, and the oxide layer and the spacers 105 are in an "ONON" structure.

[0074] In some embodiments of the present invention, after the step of forming the spacers 105, it further includes: performing a second ion implantation on the substrate 100 using the oxide layer and the spacers 105 as a mask to form source / drain regions 1092.

[0075] In a specific embodiment, the ion concentration range of the first ion implantation and the second ion implantation is 2.0E4 ions / cm 2 to 5.0E7 ions / cm2 。

[0076] Among them, the ion implantation dose in the lightly doped region 1091 is less than that in the source / drain region 1092, and the lightly doped region 1091 and the source / drain region 1092 are formed simultaneously.

[0077] In this embodiment, the thickness range of the lightly doped region 1091 is 700 Å to 900 Å, and the thickness range of the source / drain region 1092 is 1500 Å to 1800 Å.

[0078] In some embodiments of the present invention, after the steps of forming the lightly doped region 1091 and the source / drain region 1092, it further includes: etching the top surfaces of the storage gate 103, the metal select gate 104, and the top surface oxide layer of the peripheral metal select gate 1043 until the oxide layer surface is exposed.

[0079] Please refer to Figure 9 , forming an interlayer dielectric layer 106 on the substrate 100; etching the interlayer dielectric layer 106 until the surface of the source / drain region 1092 is exposed to form a plurality of openings (not shown in the figure); forming a metal silicide layer 107 at the bottom of the openings; filling the openings with a conductive material to form conductive plugs 108.

[0080] In some embodiments of the present invention, the process of etching the interlayer dielectric layer 106 is dry etching, and the process parameters of the dry etching include: the pressure of the chamber is 20 mT to 100 mT, the source power is 500 W to 2800 W, the bias power is 30 W to 2800 W, the gas flow rate is 20 sccm to 200 sccm, and the etching time is 8 s to 20 s.

[0081] After the step of forming the openings, it further includes: forming a metal layer (not shown in the figure) at the bottom of the openings; performing an annealing process to react the metal layer (not shown in the figure) with the top surface of the lightly doped region 1091 to form a metal silicide layer 107.

[0082] After forming the metal silicide layer 107, it further includes: filling the openings with a conductive material to form conductive plugs 108.

[0083] In some embodiments of the present invention, the conductive plugs 108 are formed by chemical vapor deposition process or physical vapor deposition process.

[0084] In some embodiments of the present invention, the material of the conductive plugs 108 is copper, aluminum, or tungsten.

[0085] In some embodiments of the present invention, the method for forming a metal layer (not shown in the figure) is a chemical vapor deposition process. The material of the metal layer (not shown in the figure) is nickel-platinum alloy, titanium or cobalt, and the thickness range of the metal layer is 80 angstroms to 130 angstroms.

[0086] In some embodiments of the present invention, the steps of performing an annealing process include: performing a first sub-annealing process on the top surfaces of the metal layer and a partial lightly doped region 1091, causing the top surfaces of the metal layer and the partial lightly doped region 1091 to react to form a high-resistance metal silicide layer (not shown in the figure); performing a second sub-annealing process on the high-resistance metal silicide layer, causing a phase change reaction of the high-resistance metal silicide layer to form a metal silicide layer 107.

[0087] In this embodiment, the first sub-annealing process uses a rapid thermal annealing furnace, and the process parameters of the first sub-annealing process are: the annealing temperature is 200°C to 350°C, and the annealing time is 15 seconds to 45 seconds.

[0088] In this embodiment, the second sub-annealing process uses a rapid thermal annealing furnace, and the process parameters of the second sub-annealing process are: the annealing temperature is 300°C to 600°C, and the time is 15 seconds to 45 seconds.

[0089] In this embodiment, after the first sub-annealing process, it further includes: using wet etching to remove the metal layer that has not reacted with silicon to prevent short circuits caused by bridging.

[0090] The temperature of the first sub-annealing process is lower than the temperature of the second sub-annealing process. Under the first sub-annealing process, with the annealing temperature being 200°C to 350°C, the metal layer will only react with the top surface of the partial lightly doped region 1091 to form a high-resistance metal silicide layer. If the annealing temperature is outside the range of 200°C to 350°C, it will cause problems such as incomplete reaction or overreaction between the metal layer and the top surface of the partial lightly doped region 1091.

[0091] Under the second sub-annealing process, with the annealing temperature being 300°C to 600°C, the high-resistance metal silicide layer is converted into a low-resistance metal silicide layer. If the annealing temperature is outside the range of 300°C to 600°C, it will cause the high-resistance metal silicide layer not to be completely converted into a low-resistance metal silicide layer.

[0092] In the above solution, a two-step annealing process is adopted to form the metal silicide layer 107, avoiding the problem of short circuit caused by generating a low-resistance metal silicide layer through only one annealing process. Specifically, the process temperature in a single annealing process is very high. In such a high-temperature environment, silicon can diffuse along the grain boundaries of the metal silicide layer 107, resulting in excessive growth of the metal silicide layer 107 on the silicon oxide boundary, and the subsequent wet etching cannot remove the metal silicide layer 107 on the oxide, thus causing a short circuit.

[0093] In some embodiments of the present invention, the material of the metal silicide layer 107 is NiSi containing Pt.

[0094] Correspondingly, please continue to refer to Figure 9 , the present invention also provides a split-gate memory, including: a substrate 100, the substrate 100 includes an adjacent device region I and a logic region II; a storage gate 103, located on the device region I, and a plurality of the storage gates 103 are discrete from each other; a metal select gate 104, located on the device region I, and the metal select gate 104 is adjacent to the storage gate 103.

[0095] In some embodiments of the present invention, the split-gate memory further includes: a peripheral metal select gate 1043, located on the logic region II; an adhesion layer, located between the substrate 100 and the metal select gate 104, and between the substrate 100 and the peripheral metal select gate 1043.

[0096] In some embodiments of the present invention, the materials of the metal select gate 104 and the peripheral metal select gate 1043 include one or a combination of tungsten, aluminum, and cobalt, the material of the adhesion layer includes titanium nitride, and the width range of the metal select gate 104 is 50 nanometers to 60 nanometers.

[0097] In some embodiments of the present invention, the split-gate memory further includes: a storage gate oxide layer 102, located between the substrate 100 and the storage gate 103; a metal select gate oxide layer 1032, located on the surface of the substrate 100 and the sidewalls of the storage gate 103, and between the storage gate 103 and the metal select gate 104; sidewalls 105, located on the sidewalls of the metal select gate 104 and the storage gate 103; source / drain regions 1092, located in the substrate 100 on both sides of the storage gate 103 and the metal select gate 104.

[0098] In some embodiments of the present invention, the split-gate memory further includes: an interlayer dielectric layer 106 located on the substrate 100; an opening (not shown in the figure) located within the interlayer dielectric layer 106 and exposing the surface of the source / drain region 1092; a metal silicide layer 107 located at the bottom of the opening; and a conductive plug 108 located within the opening and electrically connected to the metal silicide layer 107.

[0099] In the above solution, the metal select gate 104 is located on the substrate 100 of the device region I. Since the surface of the metal select gate 104 is smooth, it can improve the interface quality between the metal select gate 104 and the channel in the substrate 100 of the device region I, reduce the scattering of carriers in the substrate 100 of the device region I, thereby improving the carrier mobility and the channel current, and enhancing the driving ability of the split-gate memory device and improving the performance of the split-gate memory. Moreover, when achieving the same electrical function, adopting the structure of the metal select gate 104, the required width of the metal select gate 104 is smaller than that of the polysilicon select gate structure in the prior art, thereby reducing the width of the metal select gate 104 and the volume of the split-gate memory and improving the integration degree of the split-gate memory.

[0100] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a split-gate memory, characterized in that: include: Providing a substrate, the substrate comprising adjacent device regions and logic regions; Depositing a plurality of mutually discrete storage gates on the device region; forming a metal selection gate material layer and a first photoresist layer in sequence on the device region; exposing and developing the first photoresist layer to form a first photoresist layer having a metal selection gate pattern; Using the first photoresist layer with the metal selection gate pattern as a mask, the metal selection gate material layer is etched until the surface of the device region is exposed to form a plurality of discrete metal selection gates, wherein the metal selection gates are adjacent to the storage gates.

2. The method for forming a split gate memory according to claim 1, wherein: Also includes: sequentially forming a peripheral metal selection gate material layer and a second photoresist layer on the logic area; exposing and developing the second photoresist layer to form a second photoresist layer having a peripheral metal selection gate pattern; Using the second photoresist layer having the peripheral metal selection gate pattern as a mask, the peripheral metal selection gate material layer is etched until the surface of the logic region is exposed to form a peripheral metal selection gate.

3. The method for forming a split gate memory according to claim 2, wherein: The metal selection gate and the peripheral metal selection gate are formed simultaneously.

4. The method for forming a split gate memory according to claim 2, wherein: The process for forming the metal selection gate material layer and the peripheral metal selection gate material layer is a chemical vapor deposition process, and the process parameters adopted by the chemical vapor deposition process are: the deposition temperature is 300°C to 500°C, the deposition gas is a combination of one or more of WF6, H2 and SiH4, and the deposition rate is 50Å / min to 200Å / min.

5. The method for forming a split gate memory according to claim 4, wherein: Before the step of forming the metal selection gate material layer and the peripheral metal selection gate material layer, the method further includes: An adhesive layer is formed on the substrate.

6. The method for forming a split gate memory according to claim 5, wherein: The material of the metal selection gate and the peripheral metal selection gate includes a combination of one or more of tungsten, aluminum and cobalt, the material of the adhesion layer includes titanium nitride, and the width of the metal selection gate ranges from 50 nanometers to 60 nanometers.

7. The method for forming a split gate memory according to claim 1, wherein: Before the step of forming the first photoresist layer, the method further comprises: The metal selection gate material layer is planarized until the top surface of the storage gate is exposed.

8. The method for forming a split gate memory according to claim 1, wherein: Before the step of forming the storage gate, the method further includes: forming a storage gate oxide layer on the substrate; Before the step of forming the metal selection gate, the method further includes: forming a metal selection gate oxide layer on the surface of the substrate and the sidewall of the storage gate, wherein the metal selection gate oxide layer is located between the storage gate and the metal selection gate; After the step of forming the metal selection gate, the method further comprises: forming sidewall spacers on sidewalls of the metal selection gate and sidewalls of the storage gate; Using the metal selection gate, the storage gate and the sidewall as masks, ion implantation is performed on the substrate to form source / drain regions.

9. The method for forming a split gate memory according to claim 8, wherein: Also includes: forming an interlayer dielectric layer on the substrate; Etching the interlayer dielectric layer until the surface of the source / drain region is exposed to form a plurality of openings; forming a metal silicide layer at the bottom of the opening; A conductive material is filled into the opening to form a conductive plug.

10. A split-gate memory, characterized in that: include: A substrate, the substrate comprising adjacent device regions and logic regions; A storage gate is located on the device region, and a plurality of the storage gates are separated from each other; A metal selection gate is located on the device region, and the metal selection gate is adjacent to the storage gate.

11. The split gate memory according to claim 10, characterized in that: Also includes: A peripheral metal selection gate located on the logic region; An adhesive layer is located between the substrate and the metal selection gate, and between the substrate and the peripheral metal selection gate.

12. The split gate memory according to claim 11, characterized in that: The material of the metal selection gate and the peripheral metal selection gate includes a combination of one or more of tungsten, aluminum and cobalt, the material of the adhesion layer includes titanium nitride, and the width of the metal selection gate ranges from 50 nanometers to 60 nanometers.

13. The split gate memory according to claim 10, characterized in that: Also includes: A storage gate oxide layer, located between the substrate and the storage gate; A metal selection gate oxide layer, located between the substrate surface and the sidewall of the storage gate, and between the storage gate and the metal selection gate; Sidewall spacers, located on sidewalls of the metal selection gate and sidewalls of the storage gate; The source / drain region is located in the substrate on both sides of the storage gate and the metal selection gate.

14. The split gate memory according to claim 13, characterized in that: Also includes: An interlayer dielectric layer, located on the substrate; An opening, located in the interlayer dielectric layer, and the opening exposes the surface of the source / drain region; a metal silicide layer located at the bottom of the opening; A conductive plug is located in the opening and is electrically connected to the metal silicide layer.

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