Transient suppression diode chip manufacturing method
By using physical vapor deposition coating and multiple doping diffusion lithography etching during the production process of the transient suppression diode, the leakage and voltage parameter failure problems caused by sand blasting are solved, and efficient metal film adhesion and electrical parameters stability are achieved.
Patent Information
- Application Number
- CN202510170991.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-17
- Publication Date
- 2025-05-30
AI Technical Summary
During the production of transient suppression diodes, sand blasting causes fine cracks on the wafer surface, which may cause leakage and voltage parameter failure.
A transient suppression diode chip production method is adopted, and the traditional electroless coating method is replaced by a physical vapor deposition coating method, and multiple doping and diffusion and photolithography etching are performed on the surface of the silicon wafer to form a suitable structure to avoid the metal film falling off.
It effectively solves the problems of leakage and voltage parameter failure caused by surface treatment before electroless nickel plating, and improves the adhesion and electrical parameters of the metal film, with a pass rate of 97.7%.
Smart Images
Figure CN120076353A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electronic components, and more particularly to a method for manufacturing a transient voltage suppression diode chip. Background Art
[0002] In the semiconductor processing technology, after the surface of the wafer is doped with acceptor impurities such as boron, the surface cannot directly react chemically with metallic nickel. Therefore, in the process of manufacturing a transient voltage suppressor (TVS) on an N-type substrate, when nickel plating is performed on the surface of the wafer by a chemical method, a sandblasting treatment is first performed on the surface to roughen the surface of the wafer physically and then chemical nickel plating is carried out. However, the sandblasting treatment may cause microcracks on the surface of the wafer bombarded by fine sand, and in severe cases, silicon cracks may occur inside the device, resulting in leakage and failure of voltage parameters. Summary of the Invention
[0003] In view of the above problems, a method for manufacturing a transient voltage suppression diode chip provided by the present application can solve the problems of leakage and failure of voltage parameters existing in the prior art.
[0004] The technical solution adopted by the present invention to solve its technical problems is as follows:
[0005] A method for manufacturing a transient voltage suppression diode chip includes the following steps:
[0006] S1, cleaning the impurities on the surface of the silicon wafer;
[0007] S2, forming a layer of SiO 2 film on the first surface of the silicon wafer;
[0008] S3, performing N-type doping phosphorus source diffusion on the second surface of the silicon wafer to obtain a first-diffusion wafer;
[0009] S4, dividing the first-diffusion wafer to obtain first-diffusion silicon wafers;
[0010] S5, performing P-type doping boron source diffusion on the second surface of the first-diffusion silicon wafer opposite to the first surface to obtain a second-diffusion wafer;
[0011] S6, dividing the second-diffusion wafer to obtain second-diffusion silicon wafers;
[0012] S7, performing a first photolithography on the surface of the second-diffusion silicon wafer where phosphorus is diffused to form a plurality of latent images;
[0013] S8, performing a first etching to form trenches between adjacent latent images;
[0014] S9. Lay glass powder on the phosphorus-diffused side of the secondary-diffused silicon wafer and perform glass passivation to obtain a primary-passivated silicon wafer;
[0015] S10. Clean the primary-passivated silicon wafer;
[0016] S11. Repeat the operations of steps S7 - S10 on the boron-diffused side of the primary-passivated silicon wafer to obtain a secondary-passivated silicon wafer;
[0017] S12. Evaporate a metal film on the secondary-passivated silicon wafer;
[0018] S13. Strip off the metal film evaporated in the trenches;
[0019] S14. Divide to obtain die chips.
[0020] Further, step S1 includes the following steps:
[0021] 1.1 Heat the No. 1 solution, immerse the silicon wafer in the No. 1 solution, and then perform overflow flushing. The No. 1 solution is a mixed solution of hydrogen peroxide, ammonia water, and deionized water, and its volume ratio is: hydrogen peroxide (hydrogen peroxide solution): ammonia water: deionized water = 1:1:6;
[0022] 1.2 Heat the No. 2 solution, immerse the silicon wafer in the No. 2 solution, and then perform overflow flushing. The No. 2 solution is a mixed solution of hydrogen peroxide, hydrochloric acid, and deionized water, and its volume ratio is: hydrogen peroxide (hydrogen peroxide solution): hydrochloric acid: deionized water = 1:1:6;
[0023] 1.3 Dry.
[0024] Further, in step S2, the growth conditions of the SiO 2 film are as follows: the temperature of the oxidation furnace is 600 °C. First, introduce wet oxygen, and then introduce dry oxygen. The flow rate of the introduced wet oxygen is 2 - 3 L / min, and the time is 8 - 10 h; the flow rate of the introduced dry oxygen is 2 - 3 L / min, and the time is 1 - 2 h.
[0025] Further, in step S3, the diffusion temperature for N-type doping phosphorus source diffusion is 1200 - 1300 °C, and the diffusion time is 30 - 50 h.
[0026] Further, in step S5, the diffusion temperature for P-type doping boron source diffusion is 1100 - 1300 °C, and the diffusion time is 10 - 20 h.
[0027] Further, step S9 includes the following steps:
[0028] 9.1 Clean the secondary-diffused silicon wafer obtained in step S8;
[0029] 9.2 Place the secondary diffusion silicon wafer on the chuck, with the side diffused with phosphorus facing up;
[0030] 9.3 Take glass powder and place it on the secondary diffusion silicon wafer, and spread it evenly with a squeegee;
[0031] 9.4 Push it into the glass sintering furnace for glass passivation to obtain a primary passivated silicon wafer, and the thickness of the glass passivation is 35um.
[0032] Further, step S10 includes the following steps,
[0033] 10.1 Immerse the primary passivated silicon wafer in a hydrofluoric acid solution, and then rinse it with overflow water;
[0034] 10.2 Immerse the primary passivated silicon wafer in a mixed acid, and then rinse it with overflow water. The mixed acid is composed of nitric acid, hydrofluoric acid and glacial acetic acid, and their volume ratio is nitric acid: hydrofluoric acid: glacial acetic acid = 5:3:1;
[0035] 10.3 Immerse the primary passivated silicon wafer in a hot cleaning solution for ultrasonic cleaning for 10 - 15 minutes, and then perform ultrasonic cleaning with pure water overflow for 10 - 15 minutes.
[0036] Further, in step S12, TiAl is vapor - deposited on the side diffused with boron, and TiNiAg is vapor - deposited on the side diffused with phosphorus.
[0037] Further, in the metal film TiNiAg, the thickness of Ti is The thickness of Ni is The thickness of Ag is
[0038] In the metal film TiAl, the thickness of Ti is The thickness of Al is
[0039] Further, step S14 includes the following steps,
[0040] 14.1 Use an SD laser dicing machine to perform a first - cut along the grooves on the first or second side of the secondary passivated silicon wafer;
[0041] 14.2 Use an SD laser dicing machine to perform a second - cut along the grooves on the side of the secondary passivated silicon wafer where the first - cut was made;
[0042] 14.3 Use a splitting machine to split the secondary passivated silicon wafer that has completed two cuts to obtain die chips.
[0043] The beneficial effects of the present invention are:
[0044] A method for fabricating a transient voltage suppression diode chip provided by an embodiment of the present application uses a physical vapor deposition coating method to replace the traditional chemical coating method. On the one hand, it can solve the problems of leakage and voltage parameter failure caused by the necessary surface treatment before electroless nickel plating in the prior art. On the other hand, the physical vapor deposition coating method adopted in the embodiment of the present application has the advantage that the metal film is not easily peeled off compared with the traditional chemical coating method. Through tests, among 97,620 wafers fabricated by the method of the embodiment of the present application, 2,309 wafers have appearance metal peeling or abnormal electrical parameters, and the qualified rate is 97.7%, which has been significantly improved compared with the traditional method. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] Figure 1 It is a schematic arrangement diagram of a silicon wafer and a phosphorus paper in step 3.1;
[0046] Figure 2 It is a schematic structural diagram of the primary diffusion wafer obtained in step 3.2;
[0047] Figure 3 It is a schematic structural diagram of the primary segmentation unit obtained in step 4.1;
[0048] Figure 4 It is a schematic arrangement diagram of the primary diffusion silicon wafer and a boron paper in step 5.1;
[0049] Figure 5 It is a schematic structural diagram of the secondary segmentation unit obtained in step 6.1;
[0050] Figure 6 It is a layout diagram of a latent image and a trench during the first lithography in step S7;
[0051] Figure 7 It is a three-dimensional structural schematic diagram of the secondary passivation silicon wafer obtained in step S11 Figure 1 ;
[0052] Figure 8 It is a three-dimensional structural schematic diagram of the secondary passivation silicon wafer obtained in step S11 Figure 2 ;
[0053] Figure 9 It is a schematic diagram of the position of the cutting focus of the two cuts in step S14;
[0054] Figure 10 It is a schematic structural diagram after the first cut in step S14;
[0055] Figure 11 It is a schematic structural diagram after the second cut in step S14;
[0056] Figure 12 It is a three-dimensional structural schematic diagram of the die obtained in step S14.
[0057] In the figure: 1, silicon wafer; 11, first surface; 12, second surface; 13, latent image; 14, groove; 21, phosphorus paper; 22, boron paper; 3, SiO 2 thin film; 41, phosphosilicate glass; 42, borosilicate glass; 5, die. Specific implementation manner
[0058] In order to enable those skilled in the art to better understand the technical solutions in this application, the following will describe the technical solutions in the embodiments of this application in detail with reference to the accompanying drawings in the embodiments of this application. The described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of this application.
[0059] A method for manufacturing a transient suppression diode chip includes the following steps:
[0060] S1, cleaning the impurities on the surface of the silicon wafer 1.
[0061] 1.1 Heat the No. 1 solution to 80 ± 5 °C, and immerse the silicon wafer 1 in the No. 1 solution for 10 minutes, then overflow and flush with water for 10 minutes to complete the primary cleaning of the silicon wafer 1. The No. 1 solution is a mixed solution of hydrogen peroxide (hydrogen peroxide), ammonia water and deionized water, and its volume ratio is: hydrogen peroxide (hydrogen peroxide): ammonia water: deionized water = 1:1:6.
[0062] 1.2 Heat the No. 2 solution to 80 ± 5 °C, and immerse the silicon wafer 1 in the No. 2 solution for 10 minutes, then overflow and flush with water for 10 minutes to complete the secondary cleaning of the silicon wafer 1. The No. 2 solution is a mixed solution of hydrogen peroxide (hydrogen peroxide), hydrochloric acid and deionized water, and its volume ratio is: hydrogen peroxide (hydrogen peroxide): hydrochloric acid: deionized water = 1:1:6.
[0063] 1.3 Dry the silicon wafer 1 that has been cleaned twice.
[0064] S2, generating a layer of SiO 2 thin film 3 on the first surface 11 of the silicon wafer 1.
[0065] 2.1 Place the silicon wafer 1 in an oxidation furnace for high-temperature oxidation, and generate a layer of SiO 2 thin film 3 on the surface of the silicon wafer 1. The temperature of the oxidation furnace is 600 °C, and wet oxygen is first introduced, and then dry oxygen is introduced. The flow rate of the wet oxygen introduced is 2 L / min, and the time is 7 h; the flow rate of the dry oxygen introduced is 3 L / min, and the time is 2 h.
[0066] 2.2 Spin-coat photoresist on the first surface 11 of the silicon wafer 1.
[0067] 2.3 Immerse the silicon wafer 1 obtained in step 2.2 in the #3 solution for 30 seconds, and then rinse it with overflowing water for 10 minutes to remove the SiO 2 thin film 3 in areas other than the first side 11. The SiO 2 thin film 3 on the first side 11 will not be removed under the protection of the photoresist. The #3 solution is a mixed solution of hydrofluoric acid, ammonium fluoride and water, and its volume ratio is: hydrofluoric acid: ammonium fluoride: water = 1:2:3.
[0068] 2.4 Immerse the silicon wafer 1 obtained in step 2.3 in the photoresist remover for 20 - 30 seconds, and then rinse it with overflowing water for 10 minutes to remove the photoresist on the first side 11.
[0069] 2.5 Clean the silicon wafer 1 obtained in step 2.4.
[0070] S3. Perform N-type doping phosphorus source diffusion on the silicon wafer 1 obtained in step S2 to obtain a first diffusion wafer.
[0071] 3.1 Arrange and press the silicon wafer 1 obtained in step S2 and the phosphorus paper 21 in the order as Figure 1 shown. That is, place a piece of phosphorus paper 21 between two silicon wafers 1, and the second side 12 of the silicon wafer 1 faces the phosphorus paper 21 as the permeation surface, so as to form a first diffusion unit, and then arrange multiple first diffusion units in sequence along one direction.
[0072] 3.2 Place the silicon wafer 1 and the phosphorus paper 21 arranged and pressed in the order as Figure 1 shown flat on the silicon carbide flat boat, place silicon blind wafers below, press a 1 cm thick silicon press wafer above, and then push it into the diffusion furnace for first source diffusion to obtain the first diffusion wafer as Figure 2 shown.
[0073] As a specific implementation manner, in this embodiment, the diffusion temperature for N-type doping phosphorus source diffusion is 1300 °C, and the diffusion time is 40 h.
[0074] S4. Divide the first diffusion wafer obtained in step S3 to obtain first diffusion silicon wafers 1.
[0075] 4.1 Immerse the first diffusion wafer obtained in step S3 in the oxide etching solution to remove the SiO 2 thin film 3 and the oxide layer formed during the first source diffusion, and divide the first diffusion wafer into several first segmentation units as Figure 3 shown.
[0076] Preferably, the oxide layer etching solution is a mixed solution of hydrofluoric acid, ammonium fluoride, and water, and their volume ratio is: hydrofluoric acid : ammonium fluoride : water = 1:2:3. The immersion time of the primary diffusion wafer in the oxide layer etching solution is 20 - 60 seconds. The oxide layer within the photolithography lines of the obtained primary segmentation unit should be completely removed when observed under a microscope.
[0077] 4.2 Immerse the primary segmentation unit obtained in step 4.1 in a hydrofluoric acid solution for etching, so that the phosphosilicate glass 41 formed between the two primary diffusion silicon wafers 1 in the primary segmentation unit due to high temperature is dissolved, thereby obtaining independent primary diffusion silicon wafers 1.
[0078] Preferably, the immersion time of the primary segmentation unit in the hydrofluoric acid solution is 45h, so as to completely remove the surface - crystallized phosphosilicate glass 41, making the surface of the primary diffusion silicon wafer 1 clean and free of foreign objects.
[0079] As another implementation method, the operation sequences of step 4.1 and step 4.2 can be exchanged.
[0080] S5. Perform P - type doping boron source diffusion on the primary diffusion silicon wafer 1 obtained in step S4 to obtain a secondary diffusion wafer.
[0081] 5.1 Arrange and press the primary diffusion silicon wafer 1 obtained in step S4 and the boron paper 22 in the order as Figure 4 shown. That is, place a boron paper 22 between two primary diffusion silicon wafers 1, and the first surface 11 of the silicon wafer 1 faces the boron paper 22 as the permeation surface, thereby forming a secondary diffusion unit. Then arrange multiple secondary diffusion units in sequence along one direction.
[0082] 5.2 Place the primary diffusion silicon wafer 1 and the boron paper 22 arranged and pressed in the order as Figure 4 shown flat on a silicon carbide flat boat, place silicon blind wafers below, press a 1 - cm thick silicon pressure wafer above, and then push it into the diffusion furnace for secondary source diffusion to obtain a secondary diffusion wafer.
[0083] As a specific implementation method, in this embodiment, the diffusion temperature for P - type doping boron source diffusion is 1200 °C, and the diffusion time is 15h.
[0084] S6. Segment the secondary diffusion wafer obtained in step S5 to obtain secondary diffusion silicon wafers 1.
[0085] 6.1 Immerse the secondary diffusion wafer obtained in step S5 in the oxide layer etching solution to remove the oxide layer formed during secondary source diffusion and divide the secondary diffusion wafer into several secondary segmentation units as Figure 5 shown.
[0086] Preferably, the oxide layer etching solution is a mixed solution of hydrofluoric acid, ammonium fluoride and water, and its volume ratio is: hydrofluoric acid: ammonium fluoride: water = 1:2:3. The soaking time of the secondary diffusion wafer in the oxide layer etching solution is 20 - 60 seconds, and the oxide layer within the photolithography lines should be completely removed when observing the secondary segmentation unit under a microscope.
[0087] 6.2 Immerse the secondary segmentation unit obtained in step 6.1 in a hydrofluoric acid solution for etching, so that the borosilicate glass 42 formed between the two secondary diffusion silicon wafers 1 in the secondary segmentation unit due to high temperature is dissolved, thereby obtaining independent secondary diffusion silicon wafers 1.
[0088] Preferably, the soaking time of the secondary segmentation unit in the hydrofluoric acid solution is 45 h, so as to completely eliminate the surface-crystallized borosilicate glass 42, making the surface of the secondary diffusion silicon wafer 1 clean and free of foreign matters.
[0089] As another implementation manner, the operation orders of step 6.1 and step 6.2 can be exchanged.
[0090] S7, perform a first photolithography on the phosphorus-diffused side (i.e., the second side 12) of the secondary diffusion silicon wafer 1, thereby forming a plurality of latent images 13.
[0091] As a specific implementation manner, as Figure 6 shown, the latent image 13 in this embodiment has a square structure and is arranged in a matrix.
[0092] S8, perform a first etching on the secondary diffusion silicon wafer 1 obtained in step S7 through an etching process, thereby forming grooves 14 between adjacent latent images 13.
[0093] As a specific implementation manner, the groove 14 formed in this embodiment is as Figure 6 shown, and the grooving depth of the groove 14 is 20 - 70 um, and the width of the groove 14 is 100 - 150 um.
[0094] S9, lay a layer of glass powder on the phosphorus-diffused side of the secondary diffusion silicon wafer 1, and perform glass passivation through a glass sintering furnace to obtain a first passivated silicon wafer 1.
[0095] 9.1 Clean the secondary diffusion silicon wafer 1 obtained in step S8.
[0096] 9.2 Place the secondary diffusion silicon wafer 1 on a chuck, and suck the bottom surface of the secondary diffusion silicon wafer 1 through the chuck, with the phosphorus-diffused side of the secondary diffusion silicon wafer 1 facing upward.
[0097] 9.3 Use a powder spoon to take 1 mL of glass powder and place it on the secondary diffusion silicon wafer 1, and spread it evenly with a scraper. When scraping the powder, do not scrape along the groove 14. The scraping direction of the powder should form a 45-degree angle with the groove 14 to ensure that the glass powder is scraped into the groove 14.
[0098] 9.4 Load the secondary diffusion silicon wafer 1 into a quartz boat and push it into a glass sintering furnace for glass passivation to obtain a primary passivated silicon wafer 1. The thickness of the glass passivation is 35 um.
[0099] S10. Clean the primary passivated silicon wafer 1 obtained in step S9.
[0100] 10.1 Immerse the primary passivated silicon wafer 1 that has completed passivation in a hydrofluoric acid solution for 5 seconds, and then rinse it with overflowing water for 4 minutes. In the hydrofluoric acid solution, the volume ratio of hydrofluoric acid to water is 5:1, that is, hydrofluoric acid: water = 5:1.
[0101] 10.2 Immerse the primary passivated silicon wafer 1 that has completed step 10.1 in a mixed acid for 1 second, and then rinse it with overflowing water for 4 minutes. The mixed acid is composed of nitric acid, hydrofluoric acid and glacial acetic acid, and its volume ratio is nitric acid: hydrofluoric acid: glacial acetic acid = 5:3:1.
[0102] 10.3 Immerse the primary passivated silicon wafer 1 that has completed step 10.2 in a hot cleaning solution (Harmo powder solution) for ultrasonic cleaning for 10 - 15 minutes, and then perform ultrasonic cleaning with pure water overflowing for 10 - 15 minutes.
[0103] S11. Repeat the operations of steps S7 - S10 on the boron-diffused side of the primary passivated silicon wafer 1 to obtain the secondary passivated silicon wafer 1 as shown in Figure 7 and Figure 8 shown.
[0104] S12. Use an electron beam evaporation platform to perform metal film evaporation on the secondary passivated silicon wafer 1 obtained in step S11. Among them, TiAl is evaporated on the boron-diffused side, and TiNiAg is evaporated on the phosphorus-diffused side.
[0105] As a specific implementation manner, in this embodiment, when performing evaporation, the starting vacuum value ≤ 3*E - 6 Torr, the rotation speed of the evaporation pot is 5 rpm, the evaporation temperature is 40 °C, and the evaporation rate is Ti: Ni: Ag: Al: In the metal film TiNiAg, the thickness of Ti is The thickness of Ni is The thickness of Ag is In the metal film TiAl, the thickness of Ti is The thickness of Al is
[0106] S13. Strip off the metal film evaporated in the groove 14.
[0107] S14. Divide the secondary passivated silicon wafer 1 to obtain the die 5.
[0108] 14.1 Use an SD laser dicing machine to perform a first cut along the groove 14 on the first surface 11 or the second surface 12 of the secondary passivated silicon wafer 1.
[0109] As a specific implementation manner, in this embodiment, a first cut is performed along the groove 14 on the first surface 11 of the secondary passivated silicon wafer 1, and when performing the first cut as Figure 9 shown, the cutting focus is located 30 um below the groove 14 on the first surface 11. The secondary passivated silicon wafer 1 after the first cut is as Figure 10 shown.
[0110] 14.2 Use an SD laser dicing machine to perform a second cut along the groove 14 on the surface of the secondary passivated silicon wafer 1 where the first cut is performed.
[0111] As a specific implementation manner, as Figure 9 shown, when performing the second cut in this embodiment, the cutting focus is located at 2 / 3 of the thickness of the secondary passivated silicon wafer 1. That is, the distance A from the first surface 11 to the cutting focus when performing the second cut is 2 / 3 of the thickness B of the secondary passivated silicon wafer 1. The secondary passivated silicon wafer 1 after the second cut is as Figure 11 shown.
[0112] As a specific implementation manner, the cutting speed in steps 14.1 and 14.2 in this embodiment is 600 mm / S, and the cutting power is 2 W.
[0113] 14.3 Use a splitting machine to split the secondary passivated silicon wafer 1 that has completed two cuts, so as to obtain the die 5 as Figure 12 shown.
[0114] The transient suppression diode uses glass passivation. The traditional diamond knife cutting method is prone to chipping, which affects the appearance. In severe cases, it will also cause leakage problems. The embodiment of this application adopts a combination of laser dicing machine cutting and splitting machine splitting, which can effectively avoid chipping and the failure of leakage parameters caused by chipping.
[0115] Based on the embodiments provided in this application, other embodiments obtained by those skilled in the art through means such as combination, splitting, and recombination of the embodiments of this application do not exceed the protection scope of this application.
[0116] The above specific implementation manners have elaborated in detail the objectives, technical solutions and beneficial effects of the embodiments of the present application. The above are only the specific implementation manners of the embodiments of the present application, and are not used to limit the protection scope of the embodiments of the present application. That is, any modifications, equivalent replacements, improvements, etc. made on the basis of the embodiments of the present application shall be included within the protection scope of the embodiments of the present application.
Claims
1. A method for manufacturing a transient voltage suppressor diode chip, characterized in that: The following steps are included: S1, cleaning impurities on the surface of the silicon wafer (1); S2, forming a SiO2 film (3) on the first surface (11) of the silicon wafer (1); S3, performing N-type doping phosphorus source diffusion on the second surface (12) of the silicon wafer (1) to obtain a primary diffusion wafer; S4, dividing the primary diffusion wafer to obtain primary diffusion silicon wafers (1); S5, performing P-type doping boron source diffusion on the second surface (12) of the primary diffusion silicon wafer (1) opposite to the first surface (11) to obtain a secondary diffusion wafer; S6, dividing the secondary diffusion wafer to obtain secondary diffusion silicon wafers (1); S7, performing a photolithography process on the phosphorus-diffused side of the secondary diffusion silicon wafer (1), thereby forming a plurality of latent images (13); S8, performing an etching operation to form a groove (14) between adjacent latent images (13); S9, laying glass powder on the phosphorus-diffused surface of the secondary diffusion silicon wafer (1), and performing glass passivation to obtain a primary passivated silicon wafer (1); S10, cleaning the primary passivated silicon wafer (1); S11, repeating the operations of steps S7 to S10 on the boron-diffused side of the primary passivation silicon wafer (1), thereby obtaining a secondary passivation silicon wafer (1); S12, performing metal film evaporation on the secondary passivation silicon wafer (1); S13, peeling off the metal film deposited in the groove (14); S14, dividing to obtain the tube core (5).
2. The method for manufacturing a transient suppression diode chip according to claim 1, characterized in that: Step S1 includes the following steps, 1.1 Heat the 1# solution, soak the silicon wafer (1) in the 1# solution, and then flush with overflow water. The 1# solution is a mixed solution of hydrogen peroxide, ammonia water and deionized water, and the volume ratio thereof is: hydrogen peroxide (hydrogen peroxide): ammonia water: deionized water = 1:1:6; 1.2 Heat the 2# solution, and soak the silicon wafer (1) in the 2# solution, and then flush it with overflow water. The 2# solution is a mixed solution of hydrogen peroxide, hydrochloric acid and deionized water, and the volume ratio thereof is: hydrogen peroxide (hydrogen peroxide): hydrochloric acid: deionized water = 1:1:6; 1.3 Drying.
3. The method for manufacturing a transient suppression diode chip according to claim 1, characterized in that: The growth conditions of the SiO2 film (3) in step S2 are: the oxidation furnace temperature is 600°C, wet oxygen is introduced first, and then dry oxygen is introduced, the flow rate of wet oxygen is 2-3L / min, and the time is 8-10h; The flow rate of dry oxygen is 2-3 L / min, and the time is 1-2 h.
4. The method for manufacturing a transient voltage suppressor diode chip according to claim 1, characterized in that: In step S3, the diffusion temperature for N-type doping phosphorus source diffusion is 1200-1300° C., and the diffusion time is 30-50 hours.
5. The method for manufacturing a transient suppression diode chip according to claim 1, characterized in that: In step S5, the diffusion temperature for the P-type doped boron source diffusion is 1100-1300° C., and the diffusion time is 10-20 hours.
6. The method for manufacturing a transient voltage suppressor diode chip according to claim 1, characterized in that: Step S9 includes the following steps, 9.1 Cleaning the secondary diffusion silicon wafer (1) obtained in step S8; 9.2 Place the secondary diffusion silicon wafer (1) on the suction cup, with the phosphorus diffusion side of the secondary diffusion silicon wafer (1) facing upwards; 9.3 Take the glass powder and place it on the secondary diffusion silicon wafer (1) and spread it evenly with a scraper; 9.4 Push it into a glass sintering furnace for glass passivation to obtain a primary passivated silicon wafer (1), the glass passivation thickness of which is 35 um.
7. The method for manufacturing a transient voltage suppressor diode chip according to claim 1, characterized in that: Step S10 includes the following steps: 10.1 Soak the primary passivated silicon wafer (1) in a hydrofluoric acid solution and then flush it with overflow water; 10.2 Soak the primary passivated silicon wafer (1) in a mixed acid, and then flush with overflow water. The mixed acid is composed of nitric acid, hydrofluoric acid and glacial acetic acid, and the volume ratio is nitric acid: hydrofluoric acid: glacial acetic acid = 5:3:1; 10.3 Place the primary passivated silicon wafer (1) in a hot cleaning solution for ultrasonic cleaning for 10-15 minutes, and then use pure water overflow for ultrasonic cleaning for 10-15 minutes.
8. The method for manufacturing a transient suppression diode chip according to claim 1, characterized in that: In step S12, TiAl is vapor-deposited on the side where boron is diffused, and TiNiAg is vapor-deposited on the side where phosphorus is diffused.
9. The method for manufacturing a transient voltage suppressor diode chip according to claim 8, characterized in that: In the metal film TiNiAg, the thickness of Ti is The thickness of Ni is The thickness of Ag is In the metal film TiAl, the thickness of Ti is The thickness of Al is 10. The method for manufacturing a transient voltage suppressor diode chip according to claim 1, characterized in that: Step S14 includes the following steps, 14.1 Using an SD laser scriber to perform a cut along the groove (14) on the first surface (11) or the second surface (12) of the secondary passivated silicon wafer (1); 14.2 Using an SD laser scriber, a second cut is made along the groove (14) on the side of the second passivated silicon wafer (1) where the first cut was made; 14.3 Using a wafer splitter, the secondary passivated silicon wafer (1) that has been cut twice is split to obtain a tube core (5).