Novel bipolar transistor with strong magnetic resistance

Abstract

The invention discloses a novel bipolar transistor with strong magnetic resistance, a control chip and a transistor manufacturing method. The novel bipolar transistor comprises a P-type substrate, an N-type buried layer, three first STI regions, a second STI region, an active region and an N-type deep trap, the three first STI regions are arranged on one side, far away from the P-type substrate, of the N-type buried layer in parallel; the active region, the N-type deep well and the three first STI regions are arranged in the horizontal direction at intervals, the two first STI regions are located on the peripheries of all the source regions and the N-type deep well respectively, the active region comprises a collector electrode, a base electrode, a second STI region and an emitter electrode, the collector electrode and the base electrode are sequentially stacked, the second STI region and the emitter electrode are located on the side, away from the collector electrode, of the base electrode, and the second STI region is located between the emitter electrode and the peripheral first STI regions. A BE junction is formed on the interface of the emitter and the base; and the amplification factor stability and the anti-magnetic interference capability of the transistor in strong magnetic field environments with different frequencies are effectively improved.

Description

Technical Field

[0001] This application relates to the field of transistor design, and particularly to a novel bipolar transistor with strong magnetic field resistance, a control chip, and a manufacturing method of the transistor. Background Art

[0002] With the rapid development of integrated circuit technology, the feature size of chips has been continuously reduced, the integration degree has been significantly improved, and the performance and adaptability requirements of devices have also increased day by day. In addition to pursuing more efficient computing power, electronic devices also need to adapt to a variety of complex and harsh working environments, such as special conditions like space radiation, electromagnetic interference, high temperature and high humidity. In these harsh environments, strong magnetic field interference, especially pulsed strong magnetic field, has become a key challenge.

[0003] Pulsed strong magnetic field is one of the important physical environments generated during the operation of high-power devices such as electromagnetic railguns. During the launch process of an electromagnetic railgun, a large current will instantaneously pass through the coil, generating a strong pulsed magnetic field. The control chip needs to maintain stable operation in this environment. Therefore, how to improve the reliability of electronic components in a strong magnetic environment has become a research topic with great application value.

[0004] Regarding the improvement of the strong magnetic field resistance of electronic devices, the current main research direction focuses on magnetic shielding technology, that is, reducing the interference of the magnetic field to the lowest level through physical isolation. These technical solutions usually include magnetic shielding materials and magnetic shielding structures, covering high-permeability materials (such as iron-nickel alloys or soft magnetic materials) outside the device to absorb or deflect the magnetic field to protect the internal circuit, and designing a special packaging form to completely enclose the device in a magnetic shielding cover to isolate the external magnetic field. For example, Renesas Electronics Corporation once proposed an improved magnetic shielding packaging technology, which effectively improved the shielding ability of the device to the external magnetic field by embedding multiple layers of magnetic shielding materials in the chip packaging layer. However, such methods mainly solve the problem through physical isolation and do not improve the internal structure of semiconductor devices. To sum up, the existing technology mainly relies on external shielding means and lacks an optimization scheme for the internal structure of semiconductor devices. Summary of the Invention

[0005] The main purpose of this application is to provide a novel bipolar transistor with strong magnetic field resistance, a control chip, and a manufacturing method of the transistor, aiming to effectively improve the stability of the amplification factor and the anti-magnetic interference ability in strong magnetic field environments with different frequencies.

[0006] To achieve the above object, a first aspect of the present application provides a novel bipolar transistor with strong magnetic resistance, including: a P-type substrate, an N-type buried layer stacked in sequence, and three first STI regions, a second STI region, an active region, and an N-type deep well stacked on the side of the N-type buried layer away from the P-type substrate; the three first STI regions are all arranged side by side on the side of the N-type buried layer away from the P-type substrate; the active region and the N-type deep well are arranged at intervals along the horizontal direction, and two of the first STI regions are respectively located on the periphery of the active region and the N-type deep well, wherein the horizontal direction is perpendicular to the stacking direction; the active region includes: a collector, a base stacked in sequence, and the second STI region and an emitter located on the side of the base away from the collector, the second STI region is located between the emitter and the peripheral first STI region, and the interface between the emitter and the base forms a BE junction; wherein, the depth of the three first STI regions is greater than the depth of the active region and the N-type deep well; the depth of the second STI region is greater than the depth of the BE junction.

[0007] To achieve the above object, a second aspect of the present application further provides a manufacturing method of the novel bipolar transistor with strong magnetic resistance as described in the first aspect, including: manufacturing a P-type substrate, and performing N-type heavy doping on one side of the P-type substrate to obtain an N-type buried layer; growing a silicon layer on the side of the N-type buried layer away from the P-type substrate; forming the three spaced-apart first STI regions as described in the claims on the side of the silicon layer away from the N-type buried layer respectively, so as to change the movement trajectory of the emitter electrons, re-divide the base electric field distribution, and respectively form a second STI region located between two adjacent first STI regions, so as to correct the carrier movement trajectory, thereby reducing the interference of the magnetic field on the device, wherein the bottoms of the three first STI regions all extend into the N-type buried layer; performing N-type heavy doping on the deep well between the two first STI regions without the second STI region in the middle to obtain an N-type deep well; performing N-type doping on the collector region around the second STI region to obtain a collector; performing P-type doping on the region on the side of the collector away from the N-type buried layer to obtain a base; performing N+-type doping on a partial region on the side of the base away from the N-type buried layer to obtain an emitter.

[0008] Optionally, the depth of the N-type deep well is less than the depth of the first STI.

[0009] Optionally, the depth of the second STI region is lower than the depth of the first STI region.

[0010] Optionally, the depth of the collector region is lower than the first STI region.

[0011] Optionally, a new bipolar transistor with strong magnetic field resistance as described in claim 1;

[0012] In addition, to achieve the above object, the present application also provides a control chip, and the third aspect of the present application also has the new bipolar transistor with strong magnetic field resistance described in the first aspect.

[0013] The present application provides a new bipolar transistor with strong magnetic field resistance, a control chip, and a transistor manufacturing method. By sequentially stacking a P-type substrate, an N-type buried layer, and three first STI regions, a second STI region, an active region, and an N-type deep well stacked on the side of the N-type buried layer away from the P-type substrate; the three first STI regions are all arranged side by side on the side of the N-type buried layer away from the P-type substrate; the active region and the N-type deep well are arranged at intervals along the horizontal direction with the three first STI regions, and two first STI regions are respectively located on the periphery of all source regions and the N-type deep well, wherein the horizontal direction is perpendicular to the stacking direction; the active region includes: a collector, a base, and a second STI region and an emitter located on the side of the base away from the collector, the second STI region is located between the emitter and the peripheral first STI region, and the interface between the emitter and the base forms a BE junction; wherein, the depth of the three first STI regions is greater than the depth of the active region and the N-type deep well; the depth of the second STI region is greater than the depth of the BE junction, effectively improving the amplification factor stability and anti-magnetic interference ability of the transistor in a strong magnetic field environment at different frequencies. Description of the Drawings

[0014] Figure 1 It is a vertical cross-sectional structure diagram provided for an embodiment of the new bipolar transistor with strong magnetic field resistance of the present application;

[0015] Figure 2 It is a horizontal cross-sectional structure diagram provided for an embodiment of the new bipolar transistor with strong magnetic field resistance of the present application;

[0016] Figure 3 It is an improved transistor performance comparison diagram provided for an embodiment of the new bipolar transistor with strong magnetic field resistance of the present application.

[0017] The realization, functional characteristics, and advantages of the object of the present application will be further described in conjunction with the embodiments with reference to the drawings. Detailed Embodiments

[0018] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0019] In a strong magnetic field environment, especially under the action of a magnetic field in a specific sensitive direction, the movement direction of carriers in a traditional bipolar junction transistor (BJT) is greatly disturbed, resulting in a change in the electric field distribution of the BJT device, thus seriously affecting the amplification performance and stability of the device. For the anti-strong magnetic design of semiconductor devices, the existing protection methods mainly rely on magnetic shielding. This method is expensive, has low integration, and mainly focuses on the protection of high-frequency magnetic fields, and it is difficult to play an anti-strong magnetic role in the use environment of low-frequency and static magnetic fields.

[0020] The purpose of this application is to optimize the device structure, reduce the influence of the magnetic field on the performance of the BJT, and effectively improve its amplification factor stability and anti-magnetic interference ability in strong magnetic field environments with different frequencies.

[0021] This application provides a new type of bipolar junction transistor with anti-strong magnetic ability, including:

[0022] A P-type substrate 1, an N-type buried layer 2 stacked in sequence, and three first STI regions 3, a second STI region 4, an active region 5, and an N-type deep well 6 stacked on the side of the N-type buried layer away from the P-type substrate;

[0023] All three first STI regions 3 are arranged side by side on the side of the N-type buried layer 2 away from the P-type substrate 1;

[0024] The active region 5 and the N-type deep well 6 are arranged at intervals along the horizontal direction, and two of the first STI regions 3 are respectively located on the periphery of the active region 5 and the N-type deep well 6, where the horizontal direction is perpendicular to the stacking direction;

[0025] The active region 5 includes:

[0026] A collector 51, a base 52 stacked in sequence, and the second STI region 4 and an emitter 53 located on the side of the base 52 away from the collector 51. The second STI 4 region is located between the emitter 53 and the peripheral first STI region 3. The interface between the emitter 53 and the base 52 forms a BE junction, and the interface between the base 52 and the collector 51 forms a BC junction;

[0027] Among them, the depth of the three first STI regions 3 is greater than the depth of the active region 5 and the N-type deep well 6;

[0028] The depth of the second STI region 4 is greater than the depth of the BE junction.

[0029] The purpose of this application is to provide a BJT device structure and its manufacturing method for solving the problem of the decrease in the amplification factor of the BJT in a strong magnetic environment. The BJT device structure is as Figure 1 and Figure 2 shown, whereFigure 1 Shown is a cross-sectional schematic diagram of the BJT device structure of the present application; Figure 2 The longitudinal cross-sectional view of the BJT device structure of the present application is shown. The BJT device structure of the present application at least comprises: a P-type substrate 1 (PSUB), an N-type buried layer 2 (DNW) located on the P-type substrate 1, an N-type deep well 6 (NW) located to the upper right of the N-type buried layer, and a first STI region 3; Figure 2 Yes Figure 1 The central region has an N region as a collector 51 ; the central region has a P region as a base, the central region has an N+ region as an emitter 53 , and the base 52 has a second STI region 4 .

[0030] This application has the following advantages:

[0031] 1. Double-depth STI design. Based on the traditional STI structure for isolation, a shallower STI structure was designed. By placing the double-depth STI on the left and right sides of the base region, the movement trajectory of electrons in the emission region is changed, and the base region electric field distribution is redivided, thereby optimizing device performance.

[0032] 2. Compatibility with mainstream BCD processes. The shallow trench isolation technology and ion implantation process used in this application are fully compatible with mainstream BCD processes, and can efficiently integrate BJT, MOS and DMOS devices to meet the needs of high-performance analog and power drive circuits.

[0033] 3. Performance optimization in strong magnetic field environment. Through specific structural design, the influence of strong magnetic field on BJT devices is effectively reduced, so that the decrease of BJT amplification factor in high magnetic field is significantly reduced, and the reliability and environmental adaptability of the device are enhanced.

[0034] As for the technology of anti-strong magnetic design, the previous technology all used magnetic shielding technology to protect the periphery of the chip, which increased the cost, reduced the integration, and made it difficult to shield the low-frequency magnetic field. This application is based on the consideration of improving the device structure, and invents a new structure using the existing BJT process to solve the magnetic field problem at the device level, without the need for redundant packaging, reducing costs, improving integration, and effectively reducing the impact of low-frequency magnetic fields and static magnetic fields.

[0035] refer to Figure 3 The dual-depth STI structure designed in this application has higher reliability in working under strong magnetic environment. Compared with the BJT with a single-depth STI of similar structure, the attenuation of collector current of the BJT in this application is suppressed under strong magnetic field, and the degree of attenuation of BJT amplification factor is reduced by 75%.

[0036] Based on the above embodiments, a manufacturing method of a novel bipolar transistor with strong magnetic resistance includes:

[0037] S10. Fabricate a P-type substrate 1, and perform N-type heavy doping on one side of the P-type substrate to obtain an N-type buried layer 2;

[0038] S20. Grow a silicon layer on the side of the N-type buried layer 2 away from the P-type substrate 1;

[0039] S30. Respectively form three spaced-apart first STI regions 3 on the side of the silicon layer away from the N-type buried layer 2 to change the movement trajectory of the emitter electrons, re-divide the base electric field distribution, and respectively form a second STI region 4 between two adjacent first STI regions 3 to correct the carrier movement trajectory, thereby reducing the interference of the magnetic field on the device. Among them, the bottoms of the three first STI regions 3 all extend into the N-type buried layer, and the depth of the second STI region is lower than the depth of the first STI region;

[0040] S40. Perform N-type heavy doping on the deep well between two first STIs 3 that do not have the second STI region 4 in the middle to obtain an N-type deep well 6, and the depth of the N-type deep well is less than the depth of the first STI.

[0041] S50. Perform N-type doping on the collector region around the second STI region 4 to obtain a collector 51, and the depth of the collector 51 is lower than the depth of the first STI region 3.

[0042] S60. Perform P-type doping on the region of the collector 51 away from the N-type buried layer to obtain a base 52;

[0043] S70. Perform N+-type doping on a partial region of the base 52 away from the N-type buried layer 2 to obtain an emitter 53.

[0044] Based on the above embodiments, the present application further provides a control chip, including the novel bipolar transistor with strong magnetic resistance provided in any of the previous embodiments.

[0045] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A novel bipolar transistor with strong magnetic resistance, characterized in that: include: A P-type substrate and an N-type buried layer stacked in sequence, and three first STI regions, a second STI region, an active region and an N-type deep well stacked on a side of the N-type buried layer away from the P-type substrate; The three first STI regions are all arranged in parallel on a side of the N-type buried layer away from the P-type substrate; The active region and the N-type deep well are arranged in a horizontal direction with intervals from the three first STI regions, and the outermost two first STI regions are respectively located at the peripheries of the active region and the N-type deep well, wherein the horizontal direction is perpendicular to the stacking direction; The active region comprises: A collector and a base are stacked in sequence, and the second STI region and an emitter are located at a side of the base away from the collector, the second STI region is located between the emitter and the first STI region at the periphery, and a BE junction is formed at an interface between the emitter and the base; Wherein, the depths of the three first STI regions are greater than the depths of the active region and the N-type deep well; The depth of the second STI region is greater than the depth of the BE junction.

2. A method for manufacturing a novel bipolar transistor with strong magnetic resistance as claimed in claim 1, characterized in that: include: Manufacturing a P-type substrate, and performing N-type heavy doping on one side of the P-type substrate to obtain the N-type buried layer; Growing a silicon layer on a side of the N-type buried layer away from the P-type substrate; Three first STI regions are formed on the side of the silicon layer away from the N-type buried layer to change the motion trajectory of the emitter electrons and re-divide the base electric field distribution, and second STI regions are formed between two adjacent first STI regions to correct the carrier motion trajectory, wherein the bottoms of the three first STI regions extend into the N-type buried layer; Performing N-type heavy doping on a deep well between two first STI regions without the second STI region in between to obtain an N-type deep well; Performing N-type doping on the collector region around the second STI region to obtain a collector; Performing P-type doping on a region of the collector away from the N-type buried layer to obtain a base; N+ type doping is performed on a partial area of ​​the base electrode away from the N type buried layer to obtain an emitter electrode.

3. The method for manufacturing a novel bipolar transistor with strong magnetic resistance as claimed in claim 2, characterized in that: The depth of the N-type deep well is smaller than the depth of the first STI.

4. The method for manufacturing a novel bipolar transistor with strong magnetic resistance as claimed in claim 2, characterized in that: A depth of the second STI region is lower than a depth of the first STI region.

5. The method for manufacturing the novel bipolar transistor with strong magnetic resistance as claimed in claim 2, characterized in that: The collector region has a depth lower than that of the first STI region.

6. A control chip, characterized in that: A novel bipolar transistor having strong magnetic resistance as claimed in claim 1.

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