Semiconductor structure preparation method and power semiconductor device

Abstract

The invention relates to a semiconductor structure preparation method and a power semiconductor device. The method comprises the following steps: providing a substrate; the substrate internally comprises first grooves and doped regions which are arranged at intervals along a first direction parallel to the top surface of the substrate; the bottom surface of the first groove is lower than the bottom surface of the doped region; forming an oxide layer of which the top surface does not exceed the top surface of the doped region in the first trench; forming a second trench between adjacent doped regions; the size of the second groove in the first direction is gradually reduced in the direction towards the substrate; removing part of the oxide layer to form a gate oxide layer covering the exposed outer surface of the substrate; and after a gate structure is formed in the second trench, forming a contact hole in the doped region between the adjacent gate oxide layers. The alignment precision requirement of the contact hole mask and the trench gate mask is reduced, and the in-chip and inter-chip saturation voltage drop Vcesat consistency of IGBT wafers is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and particularly to a method for fabricating a semiconductor structure and a power semiconductor device. Background Art

[0002] An Insulated Gate Bipolar Transistor (IGBT) is a hybrid power device that combines the input characteristics of a MOS structure and the output characteristics of a bipolar structure. It has advantages such as a high input impedance, a small driving circuit power, simple driving, a strong current handling ability, and a low conduction saturation voltage. Since the early 1980s, it has received extensive attention and research at home and abroad, and its application fields cover multiple industries such as new energy vehicles, industrial frequency conversion, photovoltaic, smart grid, and locomotives.

[0003] Currently, IGBTs have gradually evolved from planar types to trench types. To meet the requirements of high circuit integration, the pitch (minimum repeating unit) of the cells is continuously reduced, and the distance from the active region contact hole to the trench gate is also continuously shortened. This places higher requirements on the alignment accuracy between the contact hole mask and the trench gate mask. Therefore, for IGBTs with a small cell pitch, especially those with a distance between the contact hole and the trench gate < 0.2 um, how to improve the alignment consistency between the mask and the trench gate mask has become one of the technical problems that need to be urgently solved by researchers in this field. Summary of the Invention

[0004] Based on this, in view of the technical problems in the prior art, it is necessary to provide a method for fabricating a semiconductor structure and a power semiconductor device, which can at least reduce the alignment accuracy requirements between the contact hole mask and the trench gate mask and improve the alignment consistency between the mask and the trench gate mask.

[0005] In a first aspect, the present application provides a method for fabricating a semiconductor structure, including: providing a substrate; the substrate includes first trenches and doping regions arranged at intervals along a first direction parallel to the top surface of the substrate; the bottom surface of the first trenches is lower than the bottom surface of the doping regions;

[0006] forming an oxide layer in the first trenches with a top surface not exceeding the top surface of the doping regions;

[0007] forming second trenches between adjacent doping regions; the size of the second trenches in the first direction gradually decreases in the direction towards the substrate;

[0008] removing a part of the oxide layer to form a gate oxide layer covering the exposed outer surface of the substrate;

[0009] after forming a gate structure in the second trenches, forming contact holes in the doping regions between adjacent gate oxide layers.

[0010] In the method for preparing the semiconductor structure in the above embodiments, by designing the second trench with a top-down reduced size, the spacing between adjacent gate structures on both sides of the second trench is effectively defined, the process window of subsequent contact hole etching is improved, so as to accurately control the distance between the contact hole and the gate structure, reduce the alignment accuracy requirements of the contact hole mask and the trench gate mask, provide a new solution for the high-precision preparation of micro-pitch IGBT devices, and have important engineering application value.

[0011] In some embodiments, the doped region includes a storage region, a body doped region, and a source doped region arranged in sequence along the direction away from the substrate;

[0012] The conductive types of the storage region and the source doped region are the same as that of the substrate;

[0013] The conductive type of the body doped region is different from that of the storage region.

[0014] In some embodiments, a first mask layer, a second mask layer, and a third mask layer are sequentially stacked on the top surface of the doped region along the direction away from the substrate;

[0015] The thickness of the first mask layer is less than that of the second mask layer;

[0016] The thickness of the second mask layer is less than that of the third mask layer.

[0017] In some embodiments, the height from the top surface of the oxide layer to the top surface of the source doped region is 200 Å - 1000 Å.

[0018] In some embodiments, forming a second trench between adjacent doped regions includes:

[0019] Using wet etching to remove part of the oxide layer, the first mask layer, and the source doped region located between the doped regions to form the second trench;

[0020] Wherein, the bottom surface of the second trench is higher than the top surface of the body doped region, and the top surface of the remaining first mask layer is within the bottom surface of the second mask layer.

[0021] In some embodiments, removing part of the oxide layer to form a gate oxide layer covering the exposed outer surface of the substrate includes:

[0022] Removing part of the oxide layer at the bottom of the second trench, and the height from the top surface of the remaining oxide layer to the bottom surface of the body doped region is 0.5 μm - 1.0 μm;

[0023] Removing the first mask layer and the second mask layer;

[0024] Forming a gate oxide layer covering the exposed outer surface of the substrate.

[0025] In some embodiments, after forming a gate structure in the second trench, a contact hole is formed in the doped region between adjacent gate oxide layers, including:

[0026] Form a gate conductive layer in the second trench; the top surface of the gate conductive layer is located between the top surface and the bottom surface of the source doped region;

[0027] Form a dielectric material layer covering the outer surface of the gate oxide layer and filling the second trench;

[0028] Etch back the dielectric material layer and the gate oxide layer to form a dielectric layer and expose a part of the top surface of the source doped region; the top surface of the dielectric layer is flush with the top surface of the source doped region;

[0029] Perform self-aligned etching on the source doped region between adjacent gate oxide layers to form a contact hole extending along the substrate towards the body doped region.

[0030] In some embodiments, after forming the contact hole, it further includes:

[0031] Fill the contact hole to form a metal filling layer;

[0032] Form a front metal layer covering the gate structure and the top surface of the metal filling layer;

[0033] After performing a thinning process on the substrate, a buffer layer, a collector doped region, and a back metal layer are formed on the side of the substrate away from the doped region in sequence along the direction towards the substrate.

[0034] In some embodiments, the material of the dielectric layer includes borophosphosilicate glass.

[0035] In a second aspect, the present application further provides a power semiconductor device, including a semiconductor structure prepared by the preparation method of any one of the above embodiments. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0037] Figure 1 It is a flowchart of a preparation method of a semiconductor structure provided in an embodiment;

[0038] Figure 2 It is a cross-sectional schematic diagram of the obtained structure after forming the doped region in step S102 in the preparation method of the semiconductor structure provided in an embodiment;

[0039] Figure 3Schematic cross-sectional view of the structure obtained after forming the first trench in step S102 of the method for fabricating a semiconductor structure provided in an embodiment;

[0040] Figure 4 Schematic cross-sectional view of the structure obtained after forming the oxidation material layer in step S104 of the method for fabricating a semiconductor structure provided in an embodiment;

[0041] Figure 5 Schematic cross-sectional view of the structure obtained after forming the oxide layer in step S104 of the method for fabricating a semiconductor structure provided in an embodiment;

[0042] Figure 6 Schematic cross-sectional view of the structure obtained after forming the second trench in step S106 of the method for fabricating a semiconductor structure provided in an embodiment;

[0043] Figure 7 Schematic cross-sectional view of the structure obtained after removing a part of the oxide layer in step S202 of the method for fabricating a semiconductor structure provided in an embodiment;

[0044] Figure 8 Schematic cross-sectional view of the structure obtained after forming the gate oxide layer in step S206 of the method for fabricating a semiconductor structure provided in an embodiment;

[0045] Figure 9 Schematic cross-sectional view of the structure obtained after forming the gate conductive layer in step S302 of the method for fabricating a semiconductor structure provided in an embodiment;

[0046] Figure 10 Schematic cross-sectional view of the structure obtained after forming the dielectric layer in step S306 of the method for fabricating a semiconductor structure provided in an embodiment;

[0047] Figure 11 For Figure 10 Schematic cross-sectional view of the structure obtained after forming contact holes in the semiconductor structure;

[0048] Figure 12 Schematic cross-sectional view of the structure obtained after forming the front metal layer in the method for fabricating a semiconductor structure provided in an embodiment;

[0049] Figure 13 Schematic cross-sectional view of the structure obtained after backside thinning, and forming the backside buffer layer and the backside metal layer in the method for fabricating a semiconductor structure provided in an embodiment.

[0050] Explanation of reference numerals:

[0051] 1. Substrate; 2. Storage area; 3. Body doping region; 4. Source doping region; 5. First mask layer; 6. Second mask layer; 7. Third mask layer; 8. First trench; 8a. Second trench; 9. Oxide layer; 10. Gate oxide layer; 11. Gate conductive layer; 102. Dielectric material layer; 12. Dielectric layer; 13. Contact hole; 14. Metal filling layer; 15. Front metal layer; 16. Collector doping region; 17. Buffer layer; 18. Back metal layer. Detailed implementation manners

[0052] For ease of understanding the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0054] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type or part discussed below can be referred to as the second element, component, region, layer or part; for example, the first doping type can be referred to as the second doping type, and similarly, the second doping type can be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type can be P-type and the second doping type can be N-type, or the first doping type can be N-type and the second doping type can be P-type.

[0055] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the figures is flipped, an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0056] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be ascertained, but one or more other features, integers, steps, operations, elements, components and / or groups thereof are not precluded from existence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0057] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, and such variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Accordingly, embodiments of the present application should not be limited to the specific shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present application.

[0058] Please refer to Figure 1 , the present application provides a method for preparing a semiconductor structure, comprising: step S102 - step S110.

[0059] Step S102: Provide a substrate 1; the substrate 1 includes a first trench 8 and a doped region arranged at intervals in a first direction parallel to the top surface of the substrate 1; the bottom surface of the first trench 8 is lower than the bottom surface of the doped region.

[0060] Step S104: Form an oxide layer 9 in the first trench 8 with a top surface not exceeding the top surface of the doped region.

[0061] Step S106: Form a second trench 8a between adjacent doped regions; the dimension of the second trench 8a in the first direction gradually decreases in the direction towards the substrate.

[0062] Step S108: Remove a part of the oxide layer 9 to form a gate oxide layer 10 covering the exposed outer surface of the substrate.

[0063] Step S110: After forming a gate structure in the second trench 8a, form contact holes 13 in the doped regions between adjacent gate oxide layers 10. The above method only takes an N-type silicon substrate as an example. If you want to take a P-type silicon substrate as an example, you can follow the above method and just interchange "P" and "N" in each step of the above method.

[0064] It should be understood that although Figure 1 the steps in the flowchart are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, Figure 1 at least a part of the steps in

[0065] can include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential either, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0066] For the above steps, specific descriptions are made with reference to the accompanying drawings.

[0066] Please refer to Figures 2 - 3 , before forming the first trench 8 in step S102, ion implantation can be performed on the substrate 1 through a high-temperature ion implantation device to form a doped region, so as to reduce the damage to the lattice of the substrate material.

[0067] Exemplarily, the substrate 1 can be a bulk semiconductor substrate such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), etc. In this embodiment, the substrate 1 is an N-type doped silicon wafer substrate, and its doping concentration and thickness depend on the breakdown voltage requirement of the IGBT device.

[0068] In some embodiments, the doped region includes a storage region 2, a body doped region 3, and a source doped region 4 arranged in sequence in the direction away from the substrate; the conduction types of the storage region 2 and the source doped region 4 are the same as that of the substrate 1, and the conduction type of the body doped region 3 is different from that of the storage region 2.

[0069] Specifically, please refer to Figure 2, implant a phosphorus (P) ion storage region 2, wherein the implantation dose of the implanted phosphorus (P) ions is 5e 12 cm -2 -5e 13 cm -2 , the implantation energy is 80 keV - 2 MeV, the annealing temperature is 1050 °C - 1250 °C, and the time is 30 - 300 min; implant boron (B) ions above the position where the phosphorus (P) ions are implanted to form a bulk doping region 3, and the implantation dose of the implanted boron (B) ions is 1e 14 cm -2 -6e 14 cm -2 , the implantation energy is 60 keV - 200 keV, the annealing temperature is 1000 °C - 1150 °C, and the time is 5 min - 120 min; then perform an arsenic (As) source doping region 4 implantation, and its implantation dose is 3e 15 cm -2 -2e 16 cm -2 , the implantation energy is 60 keV - 600 keV, the annealing temperature is 900 °C - 1000 °C, and the time is 0.5 min - 120 min.

[0070] Please refer to Figure 3 , in the step of forming the first trench 8, any one of deposition processes such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), and High Density Plasma (HDP) process can be first used to form a first mask layer 5, a second mask layer 6, and a third mask layer 7 that are stacked in sequence in a direction away from the substrate on the top surface of the doping region; wherein, the thickness of the first mask layer 5 is 100 Å - 300 Å, the thickness of the second mask layer 6 is 500 Å - 2000 Å, and the thickness of the third mask layer 7 is 4000 Å - 8000 Å. Then, a photoresist is coated on the third mask layer 7, and through a series of steps such as exposure, development, and etching, based on the patterned first mask layer 5, second mask layer 6, and third mask layer 7, a first trench 8 with a depth of 2 μm - 6 μm is formed. The first trench 8 penetrates the doping region in a direction towards the substrate 1, and the bottom surface is lower than the bottom surface of the storage region 2.

[0071] Exemplarily, the materials of the first mask layer 5, the second mask layer 6, and the third mask layer 7 are the same or different. Preferably, the first mask layer 5 is silicon oxide, the second mask layer 6 is silicon nitride, and the third mask layer 7 is silicon oxide.

[0072] In the above embodiments, the thickness of the first mask layer 5 is less than that of the second mask layer 6; the thickness of the second mask layer 6 is less than that of the third mask layer 7. The relatively thin first mask layer 5 can serve as a good adhesion layer and be tightly bonded to the silicon substrate 1, while the gradually thickening second mask layer 6 and third mask layer 7 can increase the strength and toughness of the entire structure and reduce the possibility of cracking, peeling, etc. during subsequent processes or use.

[0073] Please refer to Figures 4 - 5 , in the extension step of step S104, a CVD process is used to form an oxidation material layer with a thickness of 5000 Å - 10000 Å in the first trench 8, and the resulting structure is as Figure 4 shown. Subsequently, the oxidation material layer is etched dry to form the oxide layer 9, and the third mask layer 7 is also etched and removed in this step, obtaining the semiconductor structure as Figure 5 described. The third mask layer 7 can be removed by dry etching before depositing the oxidation material layer.

[0074] Among them, in some embodiments, the height from the top surface of the oxide layer 9 to the top surface of the source doping region 4 is 200 Å - 1000 Å, that is, the height of the oxide layer 9 is 200 Å - 1000 Å lower than the surface of the silicon substrate 1.

[0075] In the above embodiments, by utilizing the etching time difference characteristics caused by the height difference of the top surface of the oxide layer 9, the distance between the top surface of the oxide layer 9 and the top surface of the silicon substrate 1 is reasonably planned, and the etching amount is controlled to meet the subsequent process requirements.

[0076] Please refer to Figure 6 , on the basis of the above embodiments, step S106 further includes: using wet etching to remove part of the oxide layer 9, the first mask layer 5, and the source doping region 4 located between the doping regions to form a second trench 8a; wherein, the bottom surface of the second trench 8a is higher than the top surface of the body doping region 3, and the top surface of the remaining first mask layer 5 is within the bottom surface of the second mask layer 6, and the height of the top of the remaining oxide layer 9 from the silicon surface is 0.3 um - 0.6 um.

[0077] Specifically, as described above, there is a height difference between the top surface of the oxide layer 9 and the top surface of the doping region. The silicon substrate 1 on the sidewall of the second trench 8a contacts the wet etching solution for different times, and the etching amount gradually decreases from top to bottom. Therefore, the size of the second trench 8a in the first direction gradually decreases in the direction towards the substrate, that is, the width gradually becomes narrower, providing the basic conditions for subsequent self-alignment processes.

[0078] Please refer to Figures 7 - 8 , on the basis of the above embodiments, step S108 further includes:

[0079] Step S202: Remove part of the oxide layer 9 located at the bottom of the second trench 8a. The height from the top surface of the remaining oxide layer 9 to the bottom surface of the body doping region 3 is 0.5um - 1.0um.

[0080] Specifically, part of the oxide layer 9 can be removed by dry etching. Figure 7 This is a cross-sectional schematic diagram of the structure obtained after removing part of the oxide layer in this embodiment.

[0081] Step S204: Remove the first mask layer 5 and the second mask layer 6.

[0082] Step S206: Form a gate oxide layer 10 covering the exposed outer surface of the substrate 1.

[0083] Specifically, please refer to Figure 8 , and use an etching process to remove the first mask layer 5 and the second mask layer 6, and form a gate oxide layer 10 with a thickness of 1000Å - 1500Å on the sidewalls of the first trench 8, the second trench 8a, and the exposed top surface of the substrate 1 through a thermal growth process. The gate oxide layer 10 and the remaining oxide layer 9 together constitute the gate oxide layer of the subsequent gate structure.

[0084] Please refer to Figures 9 - 10 , in step S110, forming the gate structure includes:

[0085] Step S302: Form a gate conductive layer 11 in the first trench 8 and the second trench 8a; the top surface of the gate conductive layer 11 is located between the top surface and the bottom surface of the source doping region 4.

[0086] Please refer to Figure 9 , deposit polysilicon by any deposition method, and then etch back, and ensure that the depth of the polysilicon etch-back amount (Recess) is greater than 0.3um and less than the depth of the source doping region 4.

[0087] Step S304: Form a dielectric material layer covering the outer surface of the gate oxide layer 10 and filling the second trench 8a.

[0088] Step S306: Etch back the dielectric material layer and the gate oxide layer 10 to form a dielectric layer 12 and expose part of the top surface of the source doping region 4; the top surface of the dielectric layer 12 is flush with the top surface of the source doping region 4.

[0089] Please refer to Figure 10 , similarly, form a dielectric material layer by any deposition method and etch back until the surface of the silicon substrate 1 is exposed. At this time, the remaining dielectric material layer is used to form the dielectric layer 12, and the top surfaces of the gate oxide layer 10, the dielectric layer 12, and the source doping region 4 are flush. The silicon substrate 1 between adjacent gate oxide layers 10 is used to prepare contact holes.

[0090] Exemplarily, in some embodiments, the material of the dielectric layer 12 includes borophosphosilicate glass (BPSG).

[0091] In the above structure, boron phosphosilicate glass (BPSG) has high insulation, can effectively isolate the circuit, and prevent signal crosstalk; the low dielectric constant can reduce capacitive coupling, reduce signal transmission delay and distortion, and has good compatibility with existing semiconductor manufacturing processes.

[0092] After forming the gate structure, self-aligned etching is performed on the source doping region 4 located between adjacent gate oxide layers 10 to form a contact hole 13 extending along the direction towards the substrate 1 to the body doping region 3.

[0093] Specifically, the contact hole angle is 75° - 90°.

[0094] In the traditional process, the alignment accuracy between the contact hole mask and the trench gate mask is low, and the consistency of the distance between the prepared contact holes and the trench gates is poor. In this application, by designing the size of the second trench to limit the position of the contact hole in advance, the dielectric layer 12 and the contact hole are prepared synchronously in the same process step. Utilizing the process feature that the self-aligned etching process can automatically align with the existing device structure, high-precision etching is achieved in the source doping region with an exposed top surface, forming contact holes with a consistent distance from the gate structure, effectively avoiding problems such as the discrete and increased saturation voltage Vcesat in the IGBT wafer due to insufficient distance between the contact holes and the trench gates.

[0095] In some embodiments, after step S110, it further includes:

[0096] Step S402: Fill the contact hole 13 to form a metal filling layer 14;

[0097] Exemplarily, the material of the metal filling layer 14 includes but is not limited to titanium (Ti), titanium nitride (TiN), tungsten (W), or a composition.

[0098] Step S404: Form a front metal layer 15 covering the gate structure and the top surface of the metal filling layer 14;

[0099] Exemplarily, the material of the front metal layer 15 includes but is not limited to aluminum (Al), aluminum copper (Al - Cu).

[0100] Step S406: After performing a thinning process on the substrate 1, a buffer layer 17, a collector doping region 16, and a back metal layer 18 are formed on the side of the substrate 1 away from the doping region in an order arranged along the direction towards the substrate.

[0101] Specifically, the silicon wafer is inverted and thinned to a certain thickness. The specific thinning thickness can be determined according to the actual voltage withstand requirements of the IGBT device and is not limited in this embodiment.

[0102] On one side of the substrate 1 away from the doped region, boron (B) ions are implanted to form the collector doped region 16, with an implantation energy of 60 KeV - 20 KeV and an implantation dose of 1e 12 cm -2 -1e 14 cm -2 , and the implanted boron ions are activated using a laser annealing device; hydrogen (H) ions or phosphorus (P) ions are implanted above the position where the boron (B) ions are implanted and close to the top surface, and then annealed to form the buffer layer 17; finally, the back metal layer 18 is deposited.

[0103] Exemplarily, the material of the back metal layer 18 includes but is not limited to aluminum (Al), titanium (Ti), nickel (Ni), silver (Ag), or a composition thereof.

[0104] The semiconductor structure obtained after the above steps can be referred to Figure 13 . For the convenience of understanding this application, Figure 13 An example of the semiconductor structure prepared by the preparation method of this application is adopted. There can be other suitable examples of the semiconductor structure prepared by this application, and this application does not limit them here.

[0105] Please continue to refer to Figure 13 , this application also provides a semiconductor device, including the semiconductor structure prepared by the preparation method described in any of the above embodiments.

[0106] In the above embodiment, for the semiconductor device obtained based on the preparation method provided by this application, the distance consistency between the contact hole and the trench gate is good, reducing the performance abnormality caused by the distance deviation, improving the reliability, avoiding early failure or performance degradation, reducing the cost and extending the service life.

[0107] A semiconductor structure preparation method and a power semiconductor device provided by this application have the following unexpected technical effects:

[0108] This application proposes a semiconductor preparation method for small cell pitch, especially for IGBTs with a distance between the contact hole and the trench gate < 0.2 um. Before preparing the contact hole, a second trench with a top-down shrinking size is formed by using the etching time difference characteristic caused by the height difference to define the etching position of the contact hole. At the same time, a self-alignment process is adopted to further improve the alignment accuracy between the contact hole and the trench gate, overall reducing the alignment accuracy requirements for the contact hole mask and the trench gate mask, providing a guarantee for obtaining high consistency of Vcesat, successfully solving the distance deviation caused by poor alignment accuracy in the traditional process, significantly improving the consistency, and effectively reducing the performance fluctuation and reliability problems of the power semiconductor device due to process fluctuations.

[0109] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0110] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; The substrate comprises first grooves and doping regions arranged at intervals along a first direction parallel to the top surface of the substrate; the bottom surface of the first groove is lower than the bottom surface of the doping region; forming an oxide layer in the first trench whose top surface does not exceed the top surface of the doped region; forming a second trench between adjacent doped regions; The dimension of the second groove along the first direction gradually decreases in the direction toward the substrate; removing a portion of the oxide layer to form a gate oxide layer covering the exposed outer surface of the substrate; After forming a gate structure in the second trench, a contact hole is formed in the doping region between adjacent gate oxide layers.

2. The preparation method according to claim 1, characterized in that: The doped region includes a storage region, a body doped region, and a source doped region which are sequentially arranged in a direction away from the substrate; The storage area and the source doping area have the same conductivity type as the substrate; The body doping region and the storage region have different conductivity types.

3. The preparation method according to claim 2, characterized in that: Also includes: Located on the top surface of the doped region, a first mask layer, a second mask layer and a third mask layer are sequentially stacked in a direction away from the substrate; The thickness of the first mask layer is smaller than that of the second mask layer; The second mask layer has a thickness smaller than that of the third mask layer.

4. The preparation method according to claim 2, characterized in that: The height between the top surface of the oxide layer and the top surface of the source doping region is 200Å-1000Å.

5. The preparation method according to claim 3, characterized in that: The forming of a second trench between adjacent doping regions comprises: Using wet etching to remove a portion of the oxide layer, the first mask layer, and the source doping region between the doping regions to form the second trench; The bottom surface of the second trench is higher than the top surface of the body doping region, and the top surface of the remaining first mask layer is located within the bottom surface of the second mask layer.

6. The preparation method according to claim 3, characterized in that: The step of removing a portion of the oxide layer to form a gate oxide layer covering the exposed outer surface of the substrate comprises: Removing a portion of the oxide layer at the bottom of the second trench, so that the height between the top surface of the remaining oxide layer and the bottom surface of the body doping region is 0.5 um-1.0 um; removing the first mask layer and the second mask layer; A gate oxide layer is formed to cover the exposed outer surface of the substrate.

7. The preparation method according to claim 6, characterized in that: After forming the gate structure in the second trench, forming a contact hole in the doped region between adjacent gate oxide layers includes: forming a gate conductive layer in the second trench; wherein the top surface of the gate conductive layer is located between the top surface and the bottom surface of the source doped region; forming a dielectric material layer covering the outer surface of the gate oxide layer and filling the second trench; The dielectric material layer and the gate oxide layer are etched back to form a dielectric layer, and a portion of the top surface of the source doped region is exposed; the top surface of the dielectric layer is flush with the top surface of the source doped region; The source doping region located between adjacent gate oxide layers is subjected to self-aligned etching to form the contact hole extending toward the substrate to the body doping region.

8. The preparation method according to any one of claims 1 to 7, characterized in that: After the contact hole is formed, the method further comprises: Filling the contact hole to form a metal filling layer; forming a front metal layer covering the gate structure and the top surface of the metal filling layer; After the substrate is thinned, a buffer layer, a doping region, and a back metal layer are sequentially arranged along a direction toward the substrate and formed on a side of the substrate away from the doping region.

9. The preparation method according to any one of claims 1 to 7, characterized in that: The material of the dielectric layer includes borophosphosilicate glass.

10. A power semiconductor device, characterized in that: A semiconductor structure prepared by the preparation method according to any one of claims 1 to 9.

Images