Preparation method of semiconductor device structure

Abstract

The invention provides a preparation method of a semiconductor device structure. The preparation method comprises the following steps: forming grooves arranged at intervals in a substrate; forming a protective liner on the surface of the groove; a mask layer is formed on the substrate, an injection window for defining an LDD area is arranged in the mask layer, and the injection window at least exposes the active area and the side wall, close to the active area, of the groove; ion implantation is carried out on the active region through the implantation window at a preset inclination angle, so that an LDD region is formed in the active region, and the LDD region is formed by jointly overlapping ions implanted from the upper portion of the active region and ions implanted from the side wall of the groove. The LDD region is formed by overlapping ions injected from the upper part of the active region and ions injected from the side wall of the trench, so that the overlapping area of the gate structure and the LDD region can be effectively increased, and meanwhile, the doping concentration of the LDD region corner region at the edge of the trench region is improved, thereby improving the gate-induced drain leakage (GIDL) effect, reducing the electric leakage of the device, and improving the reliability of the device. And the overall performance of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and particularly relates to a method for preparing a semiconductor device structure. Background Art

[0002] For devices with an LDD region fabricated using a non-self-aligned process, such as medium-voltage (MV) devices, before forming the source and drain regions, the LDD region is first formed by ion implantation. The LDD region needs to have a certain overlap area with the gate structure, as shown in Figure 1 For devices with an LDD region fabricated using a non-self-aligned process, the LDD (lightly doped drain) region is defined by a mask before the growth of the gate structure, that is, by patterning photoresist (PR), rather than being formed by self-alignment using the gate and sidewall as masks after the gate structure is fabricated. Devices with an LDD region fabricated using a non-self-aligned process usually require a relatively high-energy LDD implant, and there will be a problem of rounding at the LDD region under the gate structure. This is because photoresist patterning and ion implantation are used, so when the photoresist is exposed and developed, it may lead to insufficient overlap area (overlap) between the gate structure and the LDD region, resulting in an increase in gate-induced drain leakage (GIDL), etc. Figure 2 When the node is small, after photoresist (PR) patterning, there is often a situation of corner rounding, especially the rounding near the channel side, which will have an unacceptable impact on subsequent ion implantation towards or near the channel.

[0003] Generally speaking, directly increasing the size (CD) of the LDD region will improve the insufficient overlap area between the gate structure and the LDD region, but it will sacrifice the channel length, change the target size of the device, and cause too many process parameters to be re-established in subsequent processes, thus greatly increasing the manufacturing cost of the device.

[0004] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for preparing a semiconductor device structure, which is used to solve the problem of insufficient overlap area between the gate structure and the LDD region in the prior art. The present invention focuses on improving the situation of photoresist (PR) rounding near the channel side.

[0006] To achieve the above and other related objectives, the present invention provides a method for preparing a semiconductor device structure. The preparation method includes: providing a substrate, forming trenches arranged at intervals in the substrate; forming a protective liner on the surface of the trenches; forming a mask layer on the substrate, and providing an implantation window for defining the LDD region in the mask layer, where the implantation window exposes at least the active regions on both sides of the channel and the sidewalls of the trenches close to the channel side; performing ion implantation on the active regions at a predetermined tilt angle through the implantation window to form an LDD region in the active regions. The LDD region is formed by the superposition of ions implanted from above the active regions and ions implanted from the sidewalls of the trenches. The ions implanted from the sidewalls of the trenches are used to increase the ion doping concentration at the edges of the LDD region; after ion implantation, an insulating material is filled in the trenches to form a shallow trench isolation structure.

[0007] Optionally, the tilt angle of the ion implantation is greater than 10°.

[0008] Optionally, the implantation dose range of the ion implantation is 1E12 / cm 2 ~1E15 / cm 2 , the implantation energy range is 10 KeV to 500 KeV, and the implanted elements include one or more of P, As, F, B, and BF 2 among them.

[0009] Optionally, the ion implantation is a single implantation; or the ion implantation is multiple implantations, where the energy, dose, and elements of each implantation are the same or different.

[0010] Optionally, the semiconductor device structure is an NMOS device, and the ions implanted into the active regions are N-type ions to form an N-type LDD region; or the semiconductor device structure is a PMOS device, and the ions implanted into the active regions are P-type ions to form a P-type LDD region.

[0011] Optionally, after forming the shallow trench isolation structure, the method further includes the steps of: forming a second mask layer on the substrate, providing a second implantation window for defining the LDD region in the second mask layer, where the second implantation window exposes at least the active regions on both sides of the channel; performing a second ion implantation on the active regions at a predetermined tilt angle through the second implantation window to adjust the ion concentration in the LDD region.

[0012] The implantation dose range of the second ion implantation is 1E12 / cm 2 ~1E15 / cm 2 , the implantation energy range is 10 KeV to 500 KeV, and the implanted elements include one or more of P, As, F, B, and BF 2 among them.

[0013] Optionally, after filling the trench with an insulator, it further includes a step of annealing and repairing the insulator, and the annealing and repairing step is arranged between the ion implantation step and the second ion implantation step.

[0014] Optionally, the protective liner includes a silicon dioxide layer, and the silicon dioxide layer is formed on the surface of the trench by an in-situ steam generation process or a furnace tube process, and the thickness of the silicon dioxide layer is 30-50 angstroms.

[0015] Optionally, the preparation method further includes the steps of: forming a well region in the substrate; forming a gate structure on the substrate, and the gate structure has an overlapping region with the LDD region; forming a source region and a drain region in the substrate on both sides of the gate structure by an ion implantation process, wherein the source region and the drain region are completely wrapped by the corresponding LDD regions.

[0016] As described above, the preparation method of the semiconductor device structure of the present invention has the following beneficial effects:

[0017] After forming the trench for the shallow trench isolation structure of the medium-voltage semiconductor device and growing the protective liner in the present invention, an additional ion implantation process is added without adding a new mask, and the active region of the medium-voltage semiconductor device is implanted with ions at an angle to form an LDD region. The LDD region is formed by the superposition of ions implanted from above the active region and ions implanted from the sidewalls of the trench, thereby increasing the overlapping area between the gate structure and the LDD region, and at the same time increasing the doping concentration of the corner region of the LDD region at the edge of the channel region, so as to improve the gate-induced drain leakage (GIDL) effect, reduce device leakage, and improve the overall performance of the device. Description of the Drawings

[0018] The included drawings are used to provide a further understanding of the embodiments of the present application, which form a part of the specification, are used to illustrate the implementation manners of the present application, and are used to explain the principles of the present application together with the text description. Obviously, the drawings in the following description are only some embodiments of the present application.

[0019] Figure 1 Schematic structural diagram showing that the LDD region has an overlapping region with the gate structure.

[0020] Figure 2 Schematic structural diagram showing that the LDD region formed by implantation through a photolithography mask has a rounding defect.

[0021] Figures 3 to 12 Schematic structural diagram showing the structures presented in each step of the preparation method of the semiconductor device structure according to the embodiment of the present invention.

[0022] Element Label Description

[0023] 101 Substrate

[0024] 102 Trench

[0025] 103 Protection gasket

[0026] 104 Active region

[0027] 105 Mask layer

[0028] 106 LDD region

[0029] 107 Insulator

[0030] 108 Well region

[0031] 109 Gate structure

[0032] 110 Sidewall structure

[0033] 111 Source region

[0034] 112 Drain region Detailed implementation manners

[0035] The following describes the implementation manners of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] It should be emphasized that the term "comprising / including" when used herein refers to the presence of features, whole parts, steps or components, but does not exclude the presence or addition of one or more other features, whole parts, steps or components.

[0037] Features described and / or illustrated for one implementation manner can be used in the same or similar manner in one or more other implementation manners, combined with features in other implementation manners, or replace features in other implementation manners.

[0038] When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally out of the general scale, and the schematic diagrams are only examples and should not limit the protection scope of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width and depth should be included.

[0039] For convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" etc. may be used herein to describe the relationship of one element or feature shown in the drawings with other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation, in addition to the directions depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0040] In the context of the present application, the structure in which the first feature is "above" the second feature as described may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0041] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0042] As Figures 3 to 12 shown, this embodiment provides a method for preparing a semiconductor device structure, and the preparation method includes the following steps:

[0043] As Figure 3 shown, first, step 1) is carried out, providing a substrate 101, and forming spaced-apart trenches 102 in the substrate 101.

[0044] In some embodiments, the substrate 101 can be a semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a group III-V compound (such as gallium nitride, gallium arsenide, etc.), and is not limited to the examples listed above. Element doping can also be pre-set in the substrate 101 to adjust the substrate 101 to a suitable resistivity.

[0045] In a specific example, forming the spaced-apart trenches 102 on the substrate 101 includes the following steps:

[0046] Step 1-1), depositing a hard mask layer on the substrate 101. Specifically, a silicon dioxide thin film and a silicon nitride thin film can be sequentially deposited on the substrate 101 by a chemical vapor deposition process, such as a plasma-enhanced chemical vapor deposition process (PECVD), etc., to form the hard mask layer.

[0047] Step 1-2), forming a photolithography pattern on the hard mask layer, and the photolithography pattern has a photolithography window corresponding to the trench 102.

[0048] Step 1-3): Etch the hard mask layer based on the lithography window to form an etch window in the hard mask layer.

[0049] Step 1-4): Etch trenches 102 in the substrate 101 based on the etch window, and remove the hard mask layer.

[0050] In one embodiment, the cross-sectional shape of the trench 102 may be an inverted trapezoid, and the angle between the side wall of the trench 102 and the bottom of the trench 102 may be, for example, 95° - 105°, etc. The depth of the trench 102 can be set according to the actual device size and isolation requirements.

[0051] As Figure 4 shown, then perform Step 2): Form a protective liner 103 on the surface of the trench 102.

[0052] In one embodiment, the protective liner 103 includes a silicon dioxide layer. The silicon dioxide layer can be formed on the surface of the trench 102 by in-situ steam generation (ISSG) or furnace tube process. The thickness of the silicon dioxide layer is 30 - 50 angstroms. As the protective liner 103, on the one hand, the silicon dioxide layer can repair the defects introduced on the surface of the trench 102 during the previous etching process by oxidation, improving the surface quality of the trench 102. On the other hand, the protective liner can protect the surfaces of the trench 102 and the substrate 101 during the subsequent ion implantation process, avoiding the defects caused by the ion implantation process to the surfaces of the substrate 101 and the trench 102. Further, by forming the protective liner through a thermal oxidation process, the corners of the trench 102 can be made rounded, reducing the influence of device tip discharge.

[0053] As Figure 5 shown, then perform Step 3): Form a mask layer 105 on the substrate 101, and set an implantation window (the region morphology in the figure is only for illustration) for defining the LDD region 106 in the mask layer 105. The implantation window exposes at least the active regions 104 on both sides of the channel and the side wall of the trench 102 close to the channel side.

[0054] In one embodiment, a photoresist layer can be formed on the substrate 101 by spin coating process, etc., and then an implantation window is defined in the photoresist layer through exposure - development process. On the one hand, this implantation window exposes the surface of the active region 104, and on the other hand, it exposes at least the upper part of the side wall of the trench 102 corresponding to the LDD region 106. For this LDD implantation region, the mask plate used for LDD that should have been done after STI filling in the existing process is used.

[0055] As Figures 6 to 7As shown, then perform step 4), and perform ion implantation on the active region 104 at a predetermined tilt angle θ through the implantation window to form an LDD region 106 in the active region 104. The LDD region 106 is formed by the superposition of ions implanted from above the active region 104 and ions implanted from the sidewalls of the trench 102.

[0056] In one embodiment, the ions implanted from the sidewalls of the trench 102 are used to increase the ion doping concentration at each edge of the LDD region 106. Because even though it is still affected by the rounded opening of the patterned photoresist (PR) near the channel region, but because the shallow trench isolation structure (STI) is not filled, the shielding of the implanted ions is less, that is, a smaller dose of ion implantation can be used to optimize the problem of insufficient corner concentration of the LDD caused by the rounded corners of the patterned PR (or it can be said that the overlapping area between the vertical projection of the gate in the channel region and the corners of the LDD region is insufficient), further reducing the cost and avoiding the increase of uncontrollable factors caused by expanding the critical dimension (CD) of the PR opening to solve the problem of insufficient concentration at the corners in the prior art.

[0057] In one embodiment, the tilt angle θ of the ion implantation is greater than 10°. For example, the tilt angle θ of the ion implantation can be 10° to 50°. Since the trench 102 is not yet filled with the insulator 107, this tilt angle of ion implantation can ensure that the ions implanted from the sidewalls of the trench 102 increase the ion doping concentration at each edge of the LDD region 106 (especially at the corners near the channel region) after subsequent activation and diffusion.

[0058] In one embodiment, the implantation dose range of the ion implantation is 1E12 / cm 2 ~1E15 / cm 2 , the implantation energy range is 10 keV to 500 keV, and the implanted elements include one or more of P, As, F, B, and BF 2 , where when the semiconductor device structure is an NMOS device, the ions implanted into the active region 104 are N-type ions, such as P and As, etc., to form an N-type LDD region 106; or when the semiconductor device structure is a PMOS device, the ions implanted into the active region 104 are P-type ions, such as B and BF 2 , etc., to form a P-type LDD region 106.

[0059] In one embodiment, the ion implantation is a single implantation; or the ion implantation is multiple implantations to obtain a more uniform implantation region, and thus obtain better device process reliability. Among them, the energy, dose, and elements of each implantation are the same or different to meet the requirements of different doping concentrations of the LDD region 106.

[0060] In one embodiment, the ion doping concentration at the corners of the LDD region 106 is greatly increased. Since ion implantation is performed before STI filling in the present invention, the problem of insufficient corner concentration in the LDD region caused by shielding in the PR corner rounding region is improved. Moreover, the projection of the corner target implantation region and the gate in the channel region overlaps more, which can reduce the electric field strength in this region and thus reduce GIDL leakage.

[0061] As Figure 8 described, then step 5) is performed. After ion implantation, an insulator 107 is filled in the trench 102 to form a shallow trench isolation structure.

[0062] In one embodiment, the insulator 107, such as silicon dioxide, can be filled in the trench 102 by processes such as high-density plasma chemical vapor deposition (HDP) and chemical vapor deposition (CVD), and planarization can be achieved by processes such as chemical mechanical polishing (CMP) or etch-back. After filling, an annealing step can also be included to repair the defects of the deposited oxide.

[0063] As Figures 9 to 12 shown, the method for preparing a semiconductor device structure further includes the following steps:

[0064] As Figure 9 shown, step 6) is performed to form a well region 108 in the substrate 101.

[0065] For example, for an NMOS device, P-type ions such as B and BF 2 can be implanted into the substrate 101 to form a P-type well region; for a PMOS device, N-type ions such as P and As can be implanted into the substrate 101 to form an N-type well region.

[0066] As Figure 10 shown, step 7) is performed to form a gate structure 109 on the substrate 101, and the gate structure 109 has an overlapping region with the LDD region 106.

[0067] Specifically, forming the gate structure 109 may include forming a gate oxide layer and a polysilicon layer, then etching the polysilicon layer and the gate oxide layer to form the gate structure 109, and finally forming spacer structures 110 on both sides of the gate structure 109.

[0068] In one embodiment, after forming the spacers, the following steps may further be included:

[0069] A second mask layer is formed on the substrate, and a second implantation window defining the LDD region is set in the second mask layer, and the second implantation window exposes at least the active regions on both sides of the channel; wherein the mask used for the second mask layer is the same as the mask used for the above-mentioned ion implantation for forming the LDD region for the first time.

[0070] The active region is subjected to a second ion implantation at a predetermined tilt angle through the second implantation window to adjust the ion concentration in the LDD region. The implantation dose range of the second ion implantation is 1E12 / cm 2 ~1E15 / cm 2 , the implantation energy range is 10 keV to 500 keV, and the implanted elements include one or more of P, As, F, B, and BF 2 .

[0071] Wherein, if an annealing repair step for the insulator is further included after filling the trench with the insulator, the annealing repair step can be arranged between the ion implantation step and the second ion implantation step.

[0072] Wherein, if the final LDD region is formed by two ion implantations, at this time, the implantation dose of the ion implantation (also called the first ion implantation) before the second ion implantation can be less than the implantation dose of the second ion implantation. For example, the implantation dose of the first ion implantation can be more than one order of magnitude less than the implantation dose of the second ion implantation.

[0073] In the present invention, after filling the trench with the insulator, the LDD region is implanted again. The mask used for the second mask layer can be the same as the mask for the ion implantation for forming the LDD region for the first time above. Through two LDD implantations, it can be ensured that when ion implantation is performed through the sidewall of the trench for the first time, a smaller dose is used, so as to solve the problem that the injection cannot reach the required area due to the corner rounding after PR patterning, and at the same time, the influence on other places is minimized as much as possible. At the same time, the second LDD implantation can be slightly adjusted to achieve the minimum adjustment of the original process flow, reducing the cost and time of adjustment. In addition, between the two separate LDD implantations with different doses and energies, there is also a repair annealing process for STI. Therefore, the precise position injection with a smaller dose for the first time can avoid large uncontrollable diffusion in the channel region due to the repair annealing of STI.

[0074] Of course, it can also be carried out only through one LDD before STI filling. At this time, the optimal embodiment should be to perform multiple ion implantations to form a good improvement for the problem corners caused by PR rounding, and at the same time, make the implantation in other normal areas that do not need to be improved more uniform. And in combination with the subsequent repair annealing process of STI, the angles, energies, and doses of multiple LDD implantations can be adjusted to achieve the optimal LDD layout.

[0075] Such as Figures 11 to 12As shown, step 8) is performed. Using the gate structure 109 and the sidewall structure 110 as self-aligned masks, source regions 111 and drain regions 112 are respectively formed in the substrate 101 on both sides of the gate structure 109 through an ion implantation process. In this embodiment, a medium-voltage device is used (the voltage range of the medium-voltage device is usually 1.8V to 10V), and the general structure of the medium-voltage device is that the source regions 111 and drain regions 112 are completely wrapped by the corresponding LDD regions 106.

[0076] For example, for an NMOS device, N-type ions such as P and As can be implanted in the LDD region 106 to form N-type source and drain regions; for a PMOS device, P-type ions such as B and BF 2 can be implanted in the substrate 101 to form P-type source and drain regions.

[0077] As described above, the method for preparing the semiconductor device structure of the present invention has the following beneficial effects:

[0078] After forming the trenches for the shallow trench isolation structure and growing the protective liner for the medium-voltage semiconductor device of the present invention (the protective liner can be silicon dioxide (OX), or a composite film layer to increase the STI isolation effect), the implantation concentration of the LDD region is adjusted. That is, on the basis of not adding a new mask (using the mask for ion implantation in the LDD region in the prior art), one or two ion implantation processes are used to perform angled ion implantation on the active region of the medium-voltage semiconductor device to form the LDD region. The LDD region is formed by the superposition of ions implanted from above the active region and ions implanted from the sidewalls of the trenches, thereby increasing the overlapping area between the gate structure and the LDD region, and at the same time increasing the doping concentration in the corner regions of the LDD region at the edge of the channel region, so as to improve the gate-induced drain leakage (GIDL) effect, reduce device leakage, and improve the overall performance of the device.

[0079] Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0080] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor device structure, characterized in that, the fabrication method comprises: providing a substrate, and forming trenches arranged at intervals in the substrate; forming a protective liner on the surface of the trenches; forming a mask layer on the substrate, and providing implantation windows for defining LDD regions in the mask layer, where the implantation windows expose at least the active regions on both sides of the channel and the sidewalls of the trenches close to the channel; performing ion implantation on the active regions at a predetermined tilt angle through the implantation windows to form LDD regions in the active regions, where the LDD regions are formed by the superposition of ions implanted from above the active regions and ions implanted from the sidewalls of the trenches, and the ions implanted from the sidewalls of the trenches are used to increase the ion doping concentration at the edges of each of the LDD regions; after the ion implantation, filling the trenches with an insulating material to form a shallow trench isolation structure.

2. The method for fabricating a semiconductor device structure according to claim 1, characterized in that: the tilt angle of the ion implantation is greater than 10°.

3. The method for fabricating a semiconductor device structure according to claim 1, characterized in that: The implantation dose range of the ion implantation is 1E12 / cm 2 ~1E15 / cm 2 , the implantation energy range is 10 keV to 500 keV, and the implanted elements include one or more of P, As, F, B, and BF 2 .

4. The method for fabricating a semiconductor device structure according to claim 1, characterized in that: the ion implantation is a single implantation; or the ion implantation is multiple implantations, where the energy, dose, and element of each implantation are the same or different.

5. The method for fabricating a semiconductor device structure according to claim 1, characterized in that: the semiconductor device structure is an NMOS device, and the ions for performing ion implantation on the active regions are N-type ions to form an N-type LDD region; or the semiconductor device structure is a PMOS device, and the ions for performing ion implantation on the active regions are P-type ions to form a P-type LDD region.

6. The method for fabricating a semiconductor device structure according to claim 1, characterized in that: after forming the shallow trench isolation structure, the method further comprises the steps of: forming a second mask layer on the substrate, and providing second implantation windows for defining LDD regions in the second mask layer, where the second implantation windows expose at least the active regions on both sides of the channel; performing a second ion implantation on the active regions at a predetermined tilt angle through the second implantation windows to adjust the ion concentration in the LDD regions.

7. The method for fabricating a semiconductor device structure according to claim 6, characterized in that: The implantation dose range of the second ion implantation is 1E12 / cm 2 ~1E15 / cm 2 , the implantation energy range is 10 keV to 500 keV, and the implanted elements include one or more of P, As, F, B, and BF 2 .

8. The method for fabricating a semiconductor device structure according to claim 6, characterized in that: after filling the trenches with the insulating material, the method further comprises a step of annealing and repairing the insulating material, and the annealing and repairing step is arranged between the ion implantation step and the second ion implantation step.

9. The method for fabricating a semiconductor device structure according to claim 1, characterized in that: the protective liner comprises a silicon dioxide layer, the silicon dioxide layer is formed on the surface of the trenches by an in-situ steam generation process or a furnace tube process, and the thickness of the silicon dioxide layer is 30 to 50 angstroms.

10. The method for fabricating a semiconductor device structure according to claim 1, characterized in that: the method further comprises the steps of: Form a well region in the substrate; Form a gate structure on the substrate, the gate structure having an overlapping region with the LDD region; Form a source region and a drain region in the substrate on both sides of the gate structure through an ion implantation process, wherein the source region and the drain region are completely wrapped by corresponding LDD regions.

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