Silicon carbide power device and manufacturing method thereof

Abstract

The invention provides a silicon carbide power device and a manufacturing method thereof, and relates to the technical field of semiconductor devices. The N-type substrate is arranged on the drain electrode; the N-type drift layer is arranged on the N-type substrate; the first current expansion layer is arranged on the N-type drift layer; a second current spreading layer on the first current spreading layer; the first P-type well is arranged on the second current expansion layer; the first P-type source region and the first N-type source region are arranged between the first P-type well and the source electrode; a second P-type well, a second P-type source region and a second N-type source region are arranged in the first current expansion layer; the second P-type well surrounds the second P-type source region and the second N-type source region; the source electrode forms a groove extending towards the first current expansion layer, and the grid electrode is arranged in the groove; the grid electrode is located above the second N-type source region.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a silicon carbide power device and a manufacturing method thereof. Background Art

[0002] A silicon carbide MOSFET is a metal oxide semiconductor field effect power device based on silicon carbide material, and has excellent high temperature, high voltage and high frequency performance. Compared with the traditional silicon MOSFET, the SiC MOSFET can withstand higher voltage and temperature, has lower on-resistance, faster switching speed and higher efficiency, and thus is widely used in electronic devices under high power, high frequency and harsh environments.

[0003] Current silicon carbide MOSFETs often form a P-type well by setting a P-type region under the gate to enhance the threshold control of the device.

[0004] However, although the P-type well design can help control the threshold voltage, in some cases, especially when the electric field between the gate and the P-type well may be uneven or too high, the current silicon carbide MOSFET is prone to the problem of local electric field concentration, especially under high voltage or high current. This uneven electric field distribution may lead to the breakdown of the gate oxide layer or the increase of leakage current, affecting the reliability of the device. Summary of the Invention

[0005] In view of the above deficiencies of the prior art, the purpose of the embodiments of the present invention is to provide a silicon carbide power device and a manufacturing method thereof, which can solve the technical problems existing in the prior art that although the P-type well design can help control the threshold voltage, in some cases, especially when the electric field between the gate and the P-type well may be uneven or too high, the current silicon carbide MOSFET is prone to the problem of local electric field concentration, especially under high voltage or high current. This uneven electric field distribution may lead to the breakdown of the gate oxide layer or the increase of leakage current, affecting the reliability of the device.

[0006] In the first aspect of the embodiments of the present invention, a silicon carbide power device is proposed, including: a gate, a drain, a source, an N-type substrate, an N-type drift layer, a first current spreading layer, a second current spreading layer, a first P-type well, a first P-type source region, a first N-type source region, a second P-type well, a second P-type source region, and a second N-type source region;

[0007] The drain serves as the bottom layer of the device;

[0008] The N-type substrate is disposed on the drain;

[0009] The N-type drift layer is disposed on the N-type substrate;

[0010] The first current spreading layer is on the N-type drift layer;

[0011] The second current spreading layer is on the first current spreading layer;

[0012] The first P-type well is arranged on the second current spreading layer;

[0013] The first P-type source region and the first N-type source region are arranged between the first P-type well and the source electrode;

[0014] The second P-type well, the second P-type source region and the second N-type source region are arranged in the first current spreading layer;

[0015] The second P-type well surrounds the second P-type source region and the second N-type source region;

[0016] The source electrode forms a trench extending towards the first current spreading layer, and the gate is arranged in the trench;

[0017] The gate is located above the second N-type source region.

[0018] In a second aspect of the embodiments of the present invention, a manufacturing method of a silicon carbide power device is proposed, which is used to prepare the silicon carbide power device described in the first aspect. The manufacturing method includes:

[0019] S1: Through simulation technology, with the goal of improving the performance of the silicon carbide power device, determine the optimal structural parameters of the silicon carbide power device;

[0020] S2: Prepare an N-type substrate according to the optimal structural parameters;

[0021] S3: Through chemical vapor deposition technology, epitaxially grow an N-type drift layer, a first current spreading layer and a second current spreading layer on the N-type substrate;

[0022] S4: Through ion implantation technology, form a first P-type well, a first P-type source region and a first N-type source region on the upper part of the first current spreading layer;

[0023] S5: Through dry etching technology, form a trench for placing the gate;

[0024] S6: Through ion implantation technology, form a second P-type well, a second P-type source region and a second N-type source region in the first current spreading layer at the bottom of the trench;

[0025] S7: Set the gate, the drain electrode and the source electrode.

[0026] The beneficial effects brought by the technical solutions provided by the embodiments of the present invention at least include: (1) In the embodiments of the present invention, by providing a second P-type well, the second P-type well not only functions as a P-type shielding layer, but also jointly conducts carrier transport with the individual first P-type wells, achieving more uniform and efficient carrier transport, thereby improving the on-state performance of the device.

[0027] (2) In the embodiments of the present invention, in order to maintain good performance in the short-circuit state, a second current spreading layer is added, which helps to balance the on-state performance and short-circuit performance of the device, improve the short-circuit resistance of the device, and thus enhance the safety performance of the device. Description of the Drawings

[0028] The drawings are only for the purpose of illustrating specific embodiments and are not considered to be a limitation of the present invention. Throughout the drawings, the same reference numerals represent the same components. Obviously, the drawings in the following description are only some embodiments described in the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0029] Figure 1 is a schematic structural diagram of a silicon carbide power device provided by an embodiment of the present invention;

[0030] Figure 2 is a schematic structural diagram of a fin-shaped gate provided by an embodiment of the present invention;

[0031] Figure 3 is a schematic structural diagram of a PN junction type gate control device provided by an embodiment of the present invention;

[0032] Figure 4 is a schematic structural diagram of a channel layer provided by an embodiment of the present invention.

[0033] Description of the Reference Numerals: 1 - N-type substrate; 2 - N-type drift layer; 3 - first current spreading layer; 4 - second current spreading layer; 5 - first P-type well; 6 - first P-type source region; 7 - first N-type source region; 8 - second P-type well; 9 - second P-type source region; 10 - second N-type source region; 11 - third P-type source region; 12 - N-type base layer; 13 - channel layer; 131 - first sub-channel layer; 132 - second sub-channel layer; G - gate; S - source; D - drain. Detailed Embodiments

[0034] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0035] In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessarily confusing the concepts disclosed in the present invention.

[0036] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention.

[0037] Refer to the attached drawings of the specification Figure 1 , which shows a schematic structural diagram of a silicon carbide power device provided by an embodiment of the present invention.

[0038] A silicon carbide power device provided by an embodiment of the present invention includes: a gate G, a drain D, a source S, an N-type substrate 1, an N-type drift layer 2, a first current spreading layer 3, a second current spreading layer 4, a first P-type well 5, a first P-type source region 6, a first N-type source region 7, a second P-type well 8, a second P-type source region 9, and a second N-type source region 10.

[0039] The drain D serves as the bottom layer of the device. The drain D is usually the current output terminal of the device, which is connected to the external circuit and receives the current from the source. Setting the drain D as the bottom layer helps to directly transfer the heat of the device to the substrate, thereby avoiding device damage caused by heat accumulation.

[0040] The N-type substrate 1 is disposed on the drain D. The N-type substrate 1 is the core basic layer of the MOSFET structure, which is usually formed by doping with a relatively high concentration of electron-type impurities such as phosphorus or arsenic. The N-type substrate 1 enables the device to effectively control the current flow by providing a necessary conduction path for the device.

[0041] The N-type drift layer 2 is disposed on the N-type substrate 1. The N-type drift layer 2 is a key layer of the device. It is located above the N-type substrate and usually has a relatively low doping concentration. The main function of the drift layer is to extend the working area of the device, enabling electrons to flow freely over a longer path, and optimizing the breakdown voltage and on-resistance of the device by adjusting the doping concentration and thickness of the drift layer.

[0042] The first current spreading layer 3 is on the N-type drift layer 2. The doping concentration of the first current spreading layer 3 is generally high, aiming to further improve the conductivity of the device. The function of the first current spreading layer is to increase the current-carrying capacity and improve the overall performance by reducing the on-resistance of the device.

[0043] The second current spreading layer 4 is on the first current spreading layer 3. In order to maintain good performance in the short-circuit state, the second current spreading layer 4 is added as a compromise, which helps to balance the on-performance and short-circuit performance of the device, improve the short-circuit resistance of the device, and thus enhance the safety performance of the device. The introduction of the second current spreading layer 4 provides an additional conductive region for the device, reduces the on-resistance, improves the on-performance, and helps the device to work better in high-power and high-frequency applications.

[0044] The first P-type well 5 is arranged on the second current spreading layer 4. The first P-type well 5 is a key part for forming the P-type region in the silicon carbide MOSFET. The P-type well is formed by doping trivalent elements such as boron, and this layer provides the device with the ability to control charge carriers. The setting of the P-type well can effectively control the threshold voltage, thereby adjusting the switching characteristics of the device.

[0045] The first P-type source region 6 and the first N-type source region 7 are arranged between the first P-type well 5 and the source electrode S. The two source regions form different types of regions by adjusting the doping concentration to optimize the current conduction characteristics. The combination of the first P-type source region 6 and the first N-type source region 7 adjusts the on and off characteristics of the device by forming a PN junction. When switching, the change in the electric field between the P-type source region and the N-type source region controls the flow of electrons, thereby realizing the switching operation. By reasonably designing the doping concentration and position of these two source regions, the switching speed of the device can be effectively increased and the on-resistance can be reduced.

[0046] The second P-type well 8, the second P-type source region 9 and the second N-type source region 10 are arranged in the first current spreading layer 3. The second P-type well plays a role similar to that of the first P-type well. It helps to adjust the threshold voltage and form a PN junction, while the second P-type source region 9 and the second N-type source region 10 help to optimize the carrier transmission path and reduce the current loss. By adjusting the doping concentration of these regions, the on-performance and switching performance of the device can be further optimized, and the overheating problem can be avoided at the same time.

[0047] The second P-type well 8 surrounds the second P-type source region 9 and the second N-type source region 10, thereby forming a targeted PN junction region to optimize the electric field distribution.

[0048] The source electrode S forms a trench extending towards the first current spreading layer 3, and the gate G is arranged in the trench.

[0049] The gate G is located above the second N-type source region 10. Placing the gate G above the second N-type source region further enhances the accuracy of the gate G's on-off control and optimizes the switching characteristics. With this configuration, the device can achieve lower switching losses and higher efficiency in high-speed switching applications.

[0050] The working principle of the above-mentioned silicon carbide MOSFET is introduced as follows: When a voltage is applied to the gate G, the gate electric field forms an inversion layer between the source S and the drain D, enabling carriers (electrons or holes) to flow from the source to the drain. At this time, the device enters the on state, and current can flow through multiple regions, including the PN junction region between the P-type well and the source region, the current spreading layer, and the N-type drift layer. The configuration of the first P-type well, the second P-type well, and the source region ensures high conductivity while limiting the leakage current. When the voltage of the gate G is removed or reduced to a negative value, the inversion layer disappears, the current flow is blocked, and the device is in the off state. At this time, the current path between the source S and the drain D is cut off, and the device cannot conduct.

[0051] The beneficial effects brought by the technical solutions provided in the embodiments of the present invention at least include:

[0052] (1) In the embodiments of the present invention, by setting the second P-type well, the second P-type well not only acts as a P-type shielding layer but also jointly conducts carrier transport with the first P-type well individually, realizing more uniform and efficient carrier transport, thereby improving the on-state performance of the device.

[0053] (2) In the embodiments of the present invention, in order to maintain good performance in the short-circuit state, a second current spreading layer is added, which helps to balance the on-state performance and short-circuit performance of the device, improve the short-circuit withstand ability of the device, and thus enhance the safety performance of the device.

[0054] In a possible implementation manner, the gate G adopts a split-gate structure.

[0055] In the embodiments of the present invention, adopting a split-gate structure can effectively optimize the electric field distribution of the gate, thereby improving the switching performance of the device and reducing the gate-drain charge. By dividing the gate into multiple parts, the electric field intensity between the gate and the drain can be reduced, and the losses generated during the switching process can be reduced, especially in high-frequency or fast-switching applications. This design helps to improve the switching speed of the device, reduce the switching losses, and improve the control accuracy of the gate, thereby enhancing the overall performance and efficiency. In addition, the split-gate structure can also effectively reduce the electric field stress on the gate oxide layer, improve the long-term stability and reliability of the gate oxide layer, and extend the service life of the device.

[0056] Referring to the accompanying drawings of the specification Figure 2 , a schematic structural diagram of a fin-shaped gate provided in the embodiments of the present invention is shown.

[0057] In a possible implementation, the shape of the gate G is fin-shaped.

[0058] In the embodiments of the present invention, the fin-shaped gate design can enhance the control effect of the gate on the channel, thereby improving the switching performance and conduction ability of the device. The fin-shaped gate increases the surface area of contact between the gate and the semiconductor material, enabling the gate to more uniformly control the current flow in the channel, reducing gate-drain charge and switching losses. In addition, the fin-shaped structure helps to improve the electric field distribution, reducing the electric field stress on the gate oxide layer, thereby improving the reliability and stability of the device. Especially in high-frequency and high-power applications, the fin-shaped gate can significantly improve the efficiency and switching speed of the device.

[0059] In a possible implementation, the main impurity doping concentrations of the first P-type well 5 and the second P-type well 8 are the same.

[0060] Optionally, boron is used as the main impurity in the first P-type well 5 and the second P-type well 8.

[0061] In the embodiments of the present invention, keeping the main impurity doping concentrations of the first P-type well 5 and the second P-type well 8 the same can ensure that these two P-type regions have the same conductivity characteristics, thus ensuring that the threshold voltages of each channel in the device are consistent, helping to optimize the current flow path, reducing non-uniform current distribution, and avoiding performance instability caused by different conductivity characteristics.

[0062] Refer to the accompanying Figure 3 illustrates a schematic structural diagram of a PN junction type gate control device provided by the embodiments of the present invention.

[0063] In a possible implementation, the silicon carbide power device further includes: a third P-type source region 11 and an N-type base layer 12. The first N-type source region 7 is disposed between the first P-type source region 6 and the third P-type source region 11. The third P-type source region 11 is located on the side of the first P-type source region 6 away from the source electrode S, and the first P-type source region 6 is located on the side of the first P-type source region 6 away from the gate G. An N-type base layer 12 is provided between the first P-type well 5, the third P-type source region 11, and the first N-type source region 7 as a carrier transmission path. The first P-type well 5, the third P-type source region 11, the first N-type source region 7, and the gate G form a PN junction type gate to control the conduction ability of the device through the PN junction type gate control device.

[0064] It should be noted that in the PN junction type gate, the gate voltage adjusts the conduction ability by controlling the potential difference among the P-type well, P-type source region, and N-type source region. Specifically, when the gate voltage is applied, it affects the width of the depletion region within the PN junction area: when the gate voltage is positive, the gate electric field causes holes in the P-type region and electrons in the N-type region to attract each other, reducing the width of the depletion region, thereby enhancing conductivity and enabling the current to flow between the source and drain. When the gate voltage is negative, the gate electric field increases the width of the depletion region, further inhibiting the flow of carriers until the device is completely turned off and no current is allowed to flow.

[0065] This design can improve the conduction ability of the device and ensure effective current control under short-circuit or high-voltage conditions, optimizing the switching characteristics and enhancing stability. In the case of short-circuit and high voltage, the PN junction type gate can effectively limit the short-circuit current by adjusting the expansion of the depletion region, avoiding damage to the device caused by excessive current. When the voltage increases, the PN junction type gate expands the depletion region, making the current flow path narrower, increasing the resistance, thereby reducing the short-circuit current and helping to protect the device from problems such as thermal runaway.

[0066] In the embodiment of the present invention, the PN junction type gate can precisely control the opening degree of the channel. Especially under high-voltage and short-circuit conditions, it can promote the expansion of the depletion region by adjusting the potential of the PN junction, thereby effectively reducing the short-circuit current and saturation current, and enhancing the stability and safety of the device.

[0067] Refer to the attached Figure 4 illustrates a schematic structural diagram of a channel layer provided by an embodiment of the present invention.

[0068] In a possible implementation manner, a channel layer 13 is formed along the wall surface of the trench. The channel layer 13 is electrically connected to the first current spreading layer 3 and the second current spreading layer 4. The doping concentration of impurities in the channel layer 13 varies non-uniformly in the vertical direction.

[0069] In the embodiment of the present invention, through the non-uniform doping concentration, more precise current control can be achieved in the channel region, improving the conduction performance and switching characteristics of the device.

[0070] In a possible implementation manner, the channel layer 13 is divided into a first sub-channel layer 131 farther from the source S and a second sub-channel layer 132 closer to the source S in the vertical direction. The doping concentration of impurities in the second sub-channel layer 132 is greater than that in the first sub-channel layer 131.

[0071] In an embodiment of the present invention, the second sub-channel layer 132 can be used to adjust the threshold voltage through a relatively high doping concentration, for example, raising the threshold voltage to a certain specific level to avoid or mitigate the mis-switching of the MOSFET, thereby improving the performance in high-speed applications. By combining highly doped and lightly doped channel regions, an ideal threshold voltage can be achieved without sacrificing other electrical properties, thus optimizing the overall device performance.

[0072] An embodiment of the present invention provides a manufacturing method for manufacturing the above-mentioned silicon carbide power device. The manufacturing method includes S1 to S7: S1: Through simulation technology, with the goal of improving the performance of the silicon carbide power device, determine the optimal structural parameters of the silicon carbide power device.

[0073] Specifically, a simulation model can be constructed through Silvaco TCAD.

[0074] Furthermore, the structural parameters mainly include the dimensions of each layer and the doping concentration, etc.

[0075] In a possible implementation manner, S1 is specifically: with the goal of reducing the on-resistance of the silicon carbide power device and increasing the breakdown voltage of the silicon carbide power device, search and determine the optimal structural parameters of the silicon carbide power device through the honey badger optimization algorithm.

[0076] Optionally, with the goal of reducing the on-resistance of the silicon carbide power device and increasing the breakdown voltage of the silicon carbide power device, construct the fitness function of the honey badger optimization algorithm.

[0077] Initialize the honey badger individuals using the Sine chaotic map. Each honey badger individual represents a set of feasible structural parameters. Each honey badger individual consists of multiple dimensional components, and each component represents a structural parameter: , , where, x i represents the initial position of the i-th honey badger individual, lb i represents the lower bound of the i-th feasible solution, ub i represents the upper bound of the i-th feasible solution, y i represents the chaotic number corresponding to the i-th honey badger individual, y i-1 represents the chaotic number corresponding to the (i - 1)-th honey badger individual, and μ represents the chaotic parameter, generally taking 0.99.

[0078] In the embodiments of the present invention, the advantage of using the Sine chaotic map to initialize honey badger individuals is that it can improve the diversity and distribution uniformity of the initial population, thereby enhancing the global search ability of the honey badger optimization algorithm and the ability to jump out of local optima. Compared with the traditional random initialization method, the Sine chaotic map has characteristics such as strong ergodicity, good pseudo-randomness, and weak periodicity, which can more fully cover all possible structural parameter regions in the search space, help to accelerate the convergence speed and improve the optimization accuracy, laying a good foundation for subsequent structural parameter optimization.

[0079] Adopt an elite selection strategy to retain the first half of the honey badger individuals with higher fitness values and discard the other half of the honey badger individuals to filter the initial population.

[0080] In the embodiments of the present invention, adopting an elite selection strategy to retain the first half of the honey badger individuals with higher fitness values helps to retain the current optimal solution and excellent gene information during the iteration process, prevent excellent individuals from being randomly eliminated, and improve the convergence efficiency and stability of the algorithm.

[0081] In the mining stage, introduce a random number r 1 , and make a parallel selection between searching around the global optimal individual or the current individual to update the individual position: When , .

[0082] When , .

[0083] Among them, represents the position of the i-th honey badger individual at the (t + 1)-th iteration, ω t represents the non-linear weight factor at the t-th iteration, represents the position of the i-th honey badger individual at the t-th iteration, x best represents the position where the global optimal individual is located, F represents the search direction control parameter, β represents the food acquisition ability of the honey badger individual, generally taking a fixed value of 6, I i represents the intensity factor of the i-th honey badger individual, α represents the density factor, r 1 , r 2 , r 3 and r 4 all represent random numbers between 0 and 1.

[0084] In the embodiments of the present invention, the strategy of making a parallel selection of search paths between the global optimal individual and the current individual can achieve a dynamic balance between global exploration and local exploitation. When , the individual searches based on its own experience, which helps to enhance the diversity of the population and avoid premature convergence to local optima. When At this time, the individual searches around the current global optimal solution, which is beneficial to accelerating the convergence speed. By combining the non-linear weight, intensity factor, density factor, and periodic function term, the update of the individual's position has certain perturbation and directionality, further enhancing the algorithm's ability to jump out of local optimal values and global optimization effect, and enhancing the adaptability and robustness of the algorithm in complex optimization problems.

[0085] , Among them, t represents the current iteration number, and T represents the maximum iteration number.

[0086] It should be noted that as the number of iterations increases, the weight factor gradually decreases, prompting the individual to rely more on the current optimal solution in the later stage of the search, reducing excessive exploration, and increasing the weight of local fine search. This adjustment enables the algorithm to maintain a strong exploration ability in the early stage, avoid falling into local optima, and gradually converge to the global optimal solution in the later stage, improving the search efficiency, effectively avoiding premature convergence, and enhancing the stability and accuracy of the optimization process.

[0087] , Among them, r 5 represents a random number between 0 and 1, and S represents the concentration intensity.

[0088] It should be noted that the intensity factor changes with the distance between the individual's position and the global optimal solution. When the distance to the global optimal solution is relatively close, the search intensity is weak to avoid over-concentration on the known solution. When the individual is far from the global optimal solution, the intensity factor increases to enhance the exploration ability. This adaptive adjustment mechanism can balance the relationship between global search and local search, helping to widely explore the search space in the early stage and concentrate on local optimization in the later stage, thereby improving the convergence speed of the algorithm and avoiding falling into local optimal solutions.

[0089] , Among them, C represents the density constant, and exp represents the exponential function with the natural constant as the base.

[0090] It should be noted that as the number of iterations increases, the density factor gradually decreases, thereby reducing the degree of "dense exploration" in the search process and prompting the individual to gradually focus near the global optimal solution. This adjustment enables the optimization algorithm to widely explore the search space in the initial stage and gradually reduce exploration in the later stage, concentrating resources on fine search around the optimal solution. This method effectively balances the relationship between exploration and exploitation, improves the optimization efficiency, and enhances the convergence and stability of the algorithm.

[0091] , Among them, r 6Represents a random number between 0 and 1.

[0092] During the honey collection stage, update the individual positions: , where r 7 Represents a random number between 0 and 1.

[0093] In the embodiments of the present invention, the global optimal solution is used to guide the search direction to ensure that the individuals converge towards a better solution. By this way of balancing exploration and exploitation, the algorithm can conduct a detailed search near the global optimal solution, optimize the convergence process, improve the search efficiency and prevent premature convergence.

[0094] Update the fitness values of each honey badger individual and the global optimal individual.

[0095] Judge whether the current iteration number reaches the maximum iteration number. If so, output the set of structural parameters represented by the honey badger individual with the highest current fitness. Otherwise, return to continue the iteration.

[0096] In the embodiments of the present invention, through the honey badger optimization algorithm, aiming at reducing the on-resistance of the silicon carbide power device and increasing the breakdown voltage, it can effectively balance the on-state performance and the breakdown voltage in complex multi-objective optimization problems. The honey badger optimization algorithm can conduct a global search in a wide structural parameter space, automatically find the optimal combination of structural parameters, so as to improve the overall performance of the device without sacrificing other performances. This method can ensure the best conductivity and high-voltage resistance ability in practical applications through an adaptive search strategy and fine local optimization, and improve the efficiency, stability and reliability of the power device.

[0097] S2: Prepare the N-type substrate 1 according to the optimal structural parameters.

[0098] S3: Epitaxially grow the N-type drift layer 2, the first current spreading layer 3 and the second current spreading layer 4 on the N-type substrate 1 through chemical vapor deposition technology.

[0099] Among them, the chemical vapor deposition CVD technology is a commonly used technology for thin film deposition. It converts gaseous precursors into solid substances through chemical reactions and deposits them on the surface of the substrate.

[0100] S4: Form the first P-type well 5, the first P-type source region 6 and the first N-type source region 7 on the upper part of the first current spreading layer 3 through ion implantation technology.

[0101] Among them, ion implantation technology is a process method that accelerates charged ions, precisely controls their energy and quantity, and implants the ions into the material surface to change its physical and chemical properties. In semiconductor manufacturing, ion implantation is widely used in the doping process to regulate the conductivity of materials by adjusting the type and concentration of dopants.

[0102] S5: Through dry etching technology, a trench for placing the gate G is formed.

[0103] Among them, dry etching technology is a process that selectively removes the material surface using reactive substances in gas or plasma.

[0104] S6: Through ion implantation technology, a second P-type well 8, a second P-type source region 9, and a second N-type source region 10 are formed in the first current spreading layer 3 at the bottom of the trench.

[0105] S7: The gate G, the drain D, and the source S are set.

[0106] The present invention covers any alternatives, modifications, equivalent methods, and solutions made to the essence and scope of the present invention. For the public to have a thorough understanding of the present invention, specific details are described in detail in the preferred embodiments of the present invention, and those skilled in the art can fully understand the present invention without the description of these details. In addition, well-known methods, processes, procedures, components, and circuits are not described in detail to avoid unnecessary confusion to the essence of the present invention.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or replacements that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A silicon carbide power device, characterized in that: include: A gate, a drain, a source, an N-type substrate, an N-type drift layer, a first current spreading layer, a second current spreading layer, a first P-type well, a first P-type source region, a first N-type source region, a second P-type well, a second P-type source region, and a second N-type source region; The drain electrode serves as the bottom layer of the device; The N-type substrate is disposed on the drain; The N-type drift layer is arranged on the N-type substrate; The first current spreading layer is on the N-type drift layer; The second current spreading layer is on the first current spreading layer; The first P-type well is disposed on the second current spreading layer; The first P-type source region and the first N-type source region are arranged between the first P-type well and the source electrode; The first current spreading layer is provided with the second P-type well, the second P-type source region and the second N-type source region; The second P-type well surrounds the second P-type source region and the second N-type source region; The source electrode forms a groove extending toward the first current spreading layer, and the gate electrode is arranged in the groove; The gate is located above the second N-type source region.

2. The silicon carbide power device according to claim 1, characterized in that: The gate adopts a split gate structure.

3. The silicon carbide power device according to claim 1, characterized in that: The gate is in a fin shape.

4. The silicon carbide power device according to claim 1, characterized in that: The main impurity doping concentration of the first P-type well is consistent with that of the second P-type well.

5. The silicon carbide power device according to claim 4, characterized in that: The main impurities of the first P-type well and the second P-type well are boron.

6. The silicon carbide power device according to claim 1, characterized in that: Also includes: a third P-type source region and an N-type base layer; The first N-type source region is arranged between the first P-type source region and the third P-type source region, the third P-type source region is located on a side of the first P-type source region away from the source electrode, and the first P-type source region is located on a side of the first P-type source region away from the gate; The N-type base layer is arranged between the first P-type well, the third P-type source region and the first N-type source region as a carrier transmission path, and the first P-type well, the third P-type source region, the first N-type source region and the gate form a PN junction gate, and the device conduction ability is controlled by the PN junction gate.

7. The silicon carbide power device according to claim 1, characterized in that: A channel layer is formed along the wall surface of the groove; The channel layer is electrically connected to the first current spreading layer and the second current spreading layer; The doping concentration of impurities in the channel layer varies non-uniformly in the vertical direction.

8. The silicon carbide power device according to claim 7, characterized in that: The channel layer is divided into a first sub-channel layer farther from the source electrode and a second sub-channel layer closer to the source electrode in a vertical direction; The doping concentration of the impurities in the second sub-channel layer is greater than the doping concentration of the impurities in the first sub-channel layer.

9. A method for manufacturing a silicon carbide power device, characterized in that: For manufacturing the silicon carbide power device according to any one of claims 1 to 8, the manufacturing method comprises: S1: Determine the optimal structural parameters of the silicon carbide power device by simulation technology with the goal of improving the performance of the silicon carbide power device; S2: preparing an N-type substrate according to the optimal structural parameters; S3: epitaxially growing an N-type drift layer, a first current spreading layer, and a second current spreading layer on an N-type substrate by chemical vapor deposition technology; S4: forming a first P-type well, a first P-type source region and a first N-type source region on the upper portion of the first current spreading layer by ion implantation technology; S5: forming a trench for placing the gate by dry etching technology; S6: forming a second P-type well, a second P-type source region, and a second N-type source region in the first current spreading layer at the bottom of the trench by ion implantation technology; S7: Set the gate, drain and source.

10. The manufacturing method according to claim 9, characterized in that: The S1 is specifically: With the goal of reducing the on-resistance of the silicon carbide power device and increasing the breakdown voltage of the silicon carbide power device, the optimal structural parameters of the silicon carbide power device are searched and determined through the Honey Badger optimization algorithm.

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