A silicon carbide power device and a method of manufacturing the same

Abstract

The application provides a silicon carbide power device and a manufacturing method thereof, and relates to the technical field of semiconductor devices. A drain electrode is used as a bottom layer of the device; an N-type substrate is arranged on the drain electrode; an N-type drift layer is arranged on the N-type substrate; a first current spreading layer is arranged on the N-type drift layer; a second current spreading layer is arranged on the first current spreading layer; a first P-type well is arranged on the second current spreading layer; a first P-type source region and a first N-type source region are arranged between the first P-type well and the source electrode; a second P-type well, a second P-type source region and a second N-type source region are arranged in the first current spreading layer; the second P-type well surrounds the second P-type source region and the second N-type source region; the source electrode forms a groove extending to the first current spreading layer, and a gate electrode is arranged in the groove; and the gate electrode is arranged above the second N-type source region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a silicon carbide power device and its manufacturing method. Background Technology

[0002] Silicon carbide MOSFETs are metal-oxide-semiconductor field-effect power devices based on silicon carbide material, exhibiting excellent high-temperature, high-voltage, and high-frequency performance. Compared to traditional silicon MOSFETs, SiC MOSFETs can withstand higher voltages and temperatures, have lower on-resistance, faster switching speeds, and higher efficiency, thus being widely used in high-power, high-frequency, and harsh-environment electronic devices.

[0003] Current silicon carbide MOSFETs often employ a P-type well formed by creating a P-type region below the gate to enhance the threshold control of the device.

[0004] However, while the P-well design helps control the threshold voltage, in some cases, especially the electric field between the gate and the P-well, it can become uneven or excessively high. Current silicon carbide MOSFETs are prone to localized electric field concentration, particularly under high voltage or high current. This uneven electric field distribution can lead to gate oxide breakdown or increased leakage current, affecting device reliability. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a silicon carbide power device and its manufacturing method, which can solve the problem that, although the P-well design can help control the threshold voltage, in some cases, especially the electric field between the gate and the P-well, may be non-uniform or excessively high. Current silicon carbide MOSFETs are prone to local electric field concentration, especially under high voltage or high current. This non-uniform electric field distribution may lead to gate oxide breakdown or increased leakage current, affecting the reliability of the device.

[0006] In a first aspect, a silicon carbide power device is provided, comprising: a gate, a drain, a source, an N-type substrate, an N-type drift layer, a first current spreading layer, a second current spreading layer, a first P-type well, a first P-type source region, a first N-type source region, a second P-type well, a second P-type source region, and a second N-type source region;

[0007] The drain electrode serves as the bottom layer of the device;

[0008] The N-type substrate is disposed on the drain electrode;

[0009] The N-type drift layer is disposed on the N-type substrate;

[0010] The first current spreading layer is on the N-type drift layer;

[0011] The second current spreading layer is on top of the first current spreading layer;

[0012] The first P-type well is disposed on the second current spread layer;

[0013] The first P-type source region and the first N-type source region are disposed between the first P-type well and the source electrode;

[0014] The first current spread layer is provided with the second P-type well, the second P-type source region and the second N-type source region;

[0015] The second P-type well surrounds the second P-type source region and the second N-type source region;

[0016] The source electrode forms a trench extending toward the first current spreading layer, and the gate electrode is disposed in the trench;

[0017] The gate is located above the second N-type source region.

[0018] A second aspect of this invention provides a method for manufacturing a silicon carbide power device, used to prepare the silicon carbide power device described in the first aspect, the method comprising:

[0019] S1: Using simulation technology, with the goal of improving the performance of the silicon carbide power device, determine the optimal structural parameters of the silicon carbide power device;

[0020] S2: Prepare an N-type substrate according to the optimal structural parameters described above;

[0021] S3: An N-type drift layer, a first current spreading layer, and a second current spreading layer are epitaxially grown on an N-type substrate using chemical vapor deposition technology.

[0022] S4: A first P-type well, a first P-type source region, and a first N-type source region are formed on the upper part of the first current extension layer by ion implantation technology;

[0023] S5: A trench for placing the gate is formed using dry etching technology;

[0024] S6: Using ion implantation technology, a second P-type well, a second P-type source region, and a second N-type source region are formed in the first current extension layer at the bottom of the trench;

[0025] S7: Set the gate, drain, and source.

[0026] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0027] (1) In this embodiment of the invention, by setting a second P-type well, the second P-type well not only serves as a P-type shielding layer, but also works together with the first P-type well to carry out carrier transmission, thereby achieving more uniform and efficient carrier transmission and improving the conduction performance of the device.

[0028] (2) In this embodiment of the invention, in order to maintain good performance under short-circuit conditions, a second current extension layer is added, which helps to maintain a balance between the conduction performance and short-circuit performance of the device, improve the short-circuit withstand capability of the device, and thus improve the safety performance of the device. Attached Figure Description

[0029] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0030] Figure 1 This is a schematic diagram of the structure of a silicon carbide power device provided in an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of a finned gate structure provided in an embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of the structure of a PN junction gate controller provided in an embodiment of the present invention;

[0033] Figure 4 This is a schematic diagram of a channel layer structure provided in an embodiment of the present invention.

[0034] Explanation of reference numerals in the attached figures: 1-N-type substrate; 2-N-type drift layer; 3-First current spread layer; 4-Second current spread layer; 5-First P-type well; 6-First P-type source region; 7-First N-type source region; 8-Second P-type well; 9-Second P-type source region; 10-Second N-type source region; 11-Third P-type source region; 12-N-type base layer; 13-Channel layer; 131-First sub-channel layer; 132-Second sub-channel layer; G-Gate; S-Source; D-Drain. Detailed Implementation

[0035] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0036] Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts disclosed in this invention.

[0037] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention.

[0038] Reference manual attached Figure 1 The diagram shows a schematic structural diagram of a silicon carbide power device provided in an embodiment of the present invention.

[0039] An embodiment of the present invention provides a silicon carbide power device, comprising: a gate G, a drain D, a source S, an N-type substrate 1, an N-type drift layer 2, a first current spreading layer 3, a second current spreading layer 4, a first P-type well 5, a first P-type source region 6, a first N-type source region 7, a second P-type well 8, a second P-type source region 9, and a second N-type source region 10.

[0040] The drain (D) is the bottom layer of the device. The drain (D) is typically the device's current output terminal; it connects to external circuitry and receives current from the source. Setting the drain (D) as the bottom layer helps transfer heat directly to the substrate, thus preventing device damage caused by heat buildup.

[0041] The N-type substrate 1 is disposed on the drain D. The N-type substrate 1 is the core base layer of the MOSFET structure, and it is typically formed by doping with a high concentration of electronic impurities such as phosphorus or arsenic. The N-type substrate 1 provides the necessary conductive path for the device, enabling the device to effectively control current flow.

[0042] The N-type drift layer 2 is disposed on the N-type substrate 1. The N-type drift layer 2 is a key layer of the device, located on the N-type substrate, and typically has a relatively low doping concentration. The main function of the drift layer is to extend the operating region of the device, allowing electrons to flow freely along longer paths, and to optimize the breakdown voltage and on-resistance of the device by adjusting the doping concentration and thickness of the drift layer.

[0043] The first current spreading layer 3 is located on the N-type drift layer 2. The doping concentration of the first current spreading layer 3 is typically high to further improve the conductivity of the device. The function of the first current spreading layer is to increase the current carrying capacity and improve the overall performance by reducing the on-resistance of the device.

[0044] The second current spreading layer 4 is placed on top of the first current spreading layer 3. To maintain good performance under short-circuit conditions, the addition of the second current spreading layer 4 is a compromise. This helps to balance the device's conduction and short-circuit performance, improving its short-circuit withstand capability and thus enhancing its safety performance. The introduction of the second current spreading layer 4 provides the device with additional conductive areas, reduces on-resistance, improves conduction performance, and helps the device operate better in high-power and high-frequency applications.

[0045] The first P-type well 5 is disposed on the second current extension layer 4. The first P-type well 5 is a key part in forming the P-type region in the silicon carbide MOSFET. The P-type well is formed by doping with a trivalent element such as boron, and this layer provides the device with the ability to control charge carriers. The placement of the P-type well can effectively control the threshold voltage, thereby regulating the switching characteristics of the device.

[0046] The first P-type source region 6 and the first N-type source region 7 are located between the first P-type well 5 and the source S. The two source regions form different types of areas by adjusting the doping concentration to optimize current conduction characteristics. The combination of the first P-type source region 6 and the first N-type source region 7 forms a PN junction to regulate the device's turn-on and turn-off characteristics. During switching, the change in the electric field between the P-type and N-type source regions controls the flow of electrons, thereby achieving switching operation. By rationally designing the doping concentration and location of these two source regions, the switching speed of the device can be effectively improved and the on-resistance reduced.

[0047] The first current extension layer 3 contains a second P-type well 8, a second P-type source region 9, and a second N-type source region 10. The second P-type well functions similarly to the first P-type well, helping to regulate the threshold voltage and form a PN junction, while the second P-type source region 9 and the second N-type source region 10 help optimize the carrier transport path and reduce current loss. By adjusting the doping concentration of these regions, the device's conduction and switching performance can be further optimized, while avoiding overheating issues.

[0048] The second P-type well 8 surrounds the second P-type source region 9 and the second N-type source region 10, thereby forming a targeted PN junction region to optimize the electric field distribution.

[0049] The source S forms a trench extending into the first current extension layer 3, and the gate G is disposed in the trench.

[0050] The gate G is located above the second N-type source region 10. Placing the gate G above the second N-type source region further enhances the accuracy of the gate G's on / off control and optimizes the switching characteristics. With this configuration, the device can achieve lower switching losses and higher efficiency in high-speed switching applications.

[0051] The working principle of the silicon carbide MOSFET described above is explained below:

[0052] When a gate voltage (G) is applied, the gate electric field causes an inversion layer to form between the source (S) and drain (D), allowing charge carrier electrons or holes to flow from the source to the drain. At this time, the device enters the on-state, and current can flow through multiple regions, including the PN junction region between the P-type well and the source region, the current spread layer, and the N-type drift layer. The configuration of the first P-type well, the second P-type well, and the source region ensures high conductivity while limiting leakage current. When the gate voltage (G) is removed or reduced to a negative value, the inversion layer disappears, current flow is stopped, and the device enters the off-state. At this time, the current path between the source (S) and drain (D) is cut off, and the device cannot conduct.

[0053] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0054] (1) In this embodiment of the invention, by setting a second P-type well, the second P-type well not only serves as a P-type shielding layer, but also works together with the first P-type well to carry out carrier transmission, thereby achieving more uniform and efficient carrier transmission and improving the conduction performance of the device.

[0055] (2) In this embodiment of the invention, in order to maintain good performance under short-circuit conditions, a second current extension layer is added, which helps to maintain a balance between the conduction performance and short-circuit performance of the device, improve the short-circuit withstand capability of the device, and thus improve the safety performance of the device.

[0056] In one possible implementation, the gate G employs a split gate structure.

[0057] In this embodiment of the invention, the split-gate structure effectively optimizes the electric field distribution of the gate, thereby improving the switching performance of the device and reducing gate-drain charge. By dividing the gate into multiple parts, the electric field strength between the gate and drain can be reduced, decreasing losses during switching, especially in high-frequency or fast-switching applications. This design helps to improve the switching speed of the device, reduce switching losses, and improve the control accuracy of the gate, thereby enhancing overall performance and efficiency. Furthermore, the split-gate structure can effectively reduce the electric field stress on the gate oxide layer, improving the long-term stability and reliability of the gate oxide layer and extending the device's lifespan.

[0058] Refer to the instruction manual appendix Figure 2The diagram shows a schematic representation of a finned gate according to an embodiment of the present invention.

[0059] In one possible implementation, the gate G is fin-shaped.

[0060] In this embodiment of the invention, the finned gate design enhances the gate's control over the channel, thereby improving the device's switching performance and conduction capability. By increasing the surface area of ​​the gate in contact with the semiconductor material, the finned gate allows for more uniform control of current flow in the channel, reducing gate-drain charge and switching losses. Furthermore, the finned structure helps improve the electric field distribution and reduce electric field stress on the gate oxide layer, thus improving the device's reliability and stability. Particularly in high-frequency and high-power applications, the finned gate can significantly improve device efficiency and switching speed.

[0061] In one possible implementation, the primary impurity doping concentrations of the first P-type well 5 and the second P-type well 8 are the same.

[0062] Optionally, boron is used as the main impurity in the first P-type well 5 and the second P-type well 8.

[0063] In this embodiment of the invention, keeping the main impurity doping concentration of the first P-type well 5 and the second P-type well 8 consistent can ensure that the two P-type regions have the same conductivity characteristics, thereby ensuring that the threshold voltage of each channel in the device is consistent, which helps to optimize the current flow path, reduce uneven current distribution, and avoid performance instability caused by different conductivity characteristics.

[0064] Refer to the instruction manual appendix Figure 3 The diagram shows a schematic of the structure of a PN junction gate controller provided in an embodiment of the present invention.

[0065] In one possible implementation, the silicon carbide power device further includes a third P-type source region 11 and an N-type base layer 12. A first N-type source region 7 is disposed between a first P-type source region 6 and a third P-type source region 11. The third P-type source region 11 is located on the side of the first P-type source region 6 away from the source electrode S, and the first P-type source region 6 is located on the side of the first P-type source region 6 away from the gate G. An N-type base layer 12 is disposed between the first P-type well 5, the third P-type source region 11, and the first N-type source region 7 as a carrier transport path. The first P-type well 5, the third P-type source region 11, the first N-type source region 7, and the gate G form a PN junction gate, which controls the device's conduction capability.

[0066] It should be noted that in a PN junction gate, the gate voltage regulates the conduction capability by controlling the potential difference between the P-type well, P-type source region, and N-type source region. Specifically, when the gate voltage is applied, it affects the width of the depletion region within the PN junction: when the gate voltage is positive, the gate electric field causes holes in the P-type region and electrons in the N-type region to attract each other, reducing the width of the depletion region and thus enhancing conductivity, allowing current to flow between the source and drain. When the gate voltage is negative, the gate electric field increases the width of the depletion region, further suppressing carrier flow until the device is completely turned off, preventing current flow.

[0067] This design improves the device's conduction capability and ensures effective current control under short-circuit or high-voltage conditions, optimizing switching characteristics and enhancing stability. Under short-circuit and high-voltage conditions, the PN junction gate effectively limits the short-circuit current by adjusting the expansion of the depletion region, preventing excessive current from damaging the device. When the voltage increases, the PN junction gate expands the depletion region, narrowing the current path and increasing resistance, thereby reducing the short-circuit current and helping to protect the device from problems such as thermal runaway.

[0068] In this embodiment of the invention, the PN junction gate can precisely control the opening degree of the channel. Especially under high voltage and short circuit conditions, it can promote the expansion of the depletion region by adjusting the potential of the PN junction, thereby effectively reducing the short circuit current and saturation current and improving the stability and safety of the device.

[0069] Refer to the instruction manual appendix Figure 4 The diagram shows a schematic representation of a channel layer provided in an embodiment of the present invention.

[0070] In one possible implementation, a channel layer 13 is formed along the wall of the trench. The channel layer 13 is electrically connected to the first current spreading layer 3 and the second current spreading layer 4. The doping concentration of impurities in the channel layer 13 varies non-uniformly in the vertical direction.

[0071] In this embodiment of the invention, by using non-uniform doping concentration, more precise current control can be achieved in the channel region, thereby improving the conduction performance and switching characteristics of the device.

[0072] In one possible implementation, the channel layer 13 is vertically divided into a first sub-channel layer 131 further away from the source S and a second sub-channel layer 132 closer to the source S. The doping concentration of impurities in the second sub-channel layer 132 is greater than that in the first sub-channel layer 131.

[0073] In this embodiment of the invention, the second sub-channel layer 132, with its higher doping concentration, can be used to adjust the threshold voltage, for example, by raising the threshold voltage to a specific level to avoid or mitigate MOSFET malfunctions, thereby improving performance in high-speed applications. Combining highly doped and low-doped channel regions allows for the achievement of an ideal threshold voltage without sacrificing other electrical properties, thus optimizing the overall device performance.

[0074] This invention provides a manufacturing method for manufacturing the aforementioned silicon carbide power device, the manufacturing method comprising steps S1 to S7:

[0075] S1: Using simulation technology, with the goal of improving the performance of silicon carbide power devices, determine the optimal structural parameters of silicon carbide power devices.

[0076] Specifically, simulation models can be built using Silvaco TCAD.

[0077] Furthermore, the structural parameters mainly include the size of each layer and the doping concentration.

[0078] In one possible implementation, S1 specifically involves: aiming to reduce the on-resistance of the silicon carbide power device and increase its breakdown voltage, using the honey badger optimization algorithm to search for and determine the optimal structural parameters of the silicon carbide power device.

[0079] Optionally, the fitness function of the honey badger optimization algorithm can be constructed with the goal of reducing the on-resistance of the silicon carbide power device and increasing its breakdown voltage.

[0080] Honey badger individuals are initialized using a Sine chaotic map. Each honey badger individual represents a feasible set of structural parameters, and each honey badger individual consists of multiple dimensional components, each component representing a structural parameter.

[0081] ,

[0082] ,

[0083] Where, x i Let lb represent the initial position of the i-th individual honey badger. i Let ub represent the lower bound of the i-th feasible solution. i Let y denote the upper bound of the i-th feasible solution. i Let y represent the chaos number corresponding to the i-th individual honey badger. i-1 This represents the chaos number corresponding to the (i-1)th individual honey badger, and μ represents the chaos parameter, which is typically taken as 0.99.

[0084] In this embodiment of the invention, the advantage of using Sine chaotic mapping to initialize honey badger individuals is that it can improve the diversity and distribution uniformity of the initial population, thereby enhancing the global search capability and the ability to escape local optima of the honey badger optimization algorithm. Compared with traditional random initialization methods, Sine chaotic mapping has the characteristics of strong ergodicity, good pseudo-randomness, and weak periodicity. It can more fully cover all possible structural parameter regions in the search space, which helps to accelerate the convergence speed and improve the optimization accuracy, laying a good foundation for subsequent structural parameter optimization.

[0085] An elite selection strategy was adopted, retaining the top half of the honey badger individuals with the highest fitness values ​​and discarding the other half to filter the initial population.

[0086] In this embodiment of the invention, an elite selection strategy is adopted to retain the top half of the honey badger individuals with the highest fitness values. This helps to preserve the current optimal solution and excellent gene information during the iteration process, prevents excellent individuals from being randomly eliminated, and improves the convergence efficiency and stability of the algorithm.

[0087] During the mining phase, a random number r1 is introduced to select between searching around the globally optimal individual or the current individual in parallel, updating the individual's position:

[0088] when hour, .

[0089] when hour, .

[0090] in, ω represents the position of the i-th honey badger individual in the (t+1)-th iteration. t This represents the nonlinear weighting factor at the t-th iteration. x represents the position of the i-th honey badger individual at the t-th iteration. best The value represents the location of the globally optimal individual, F represents the search direction control parameter, β represents the honey badger's ability to obtain food, which is generally taken as a fixed value of 6, and I... i Let represent the intensity factor of the i-th honey badger individual, α represent the density factor, and r1, r2, r3 and r4 all represent random numbers between 0 and 1.

[0091] In this embodiment of the invention, the strategy of selecting search paths in parallel between the globally optimal individual and the current individual can achieve a dynamic balance between global exploration and local development. Individuals searching based on their own experience helps enhance population diversity and avoids prematurely falling into local optima. Individual nodes search around the current global optimum, which helps to accelerate convergence. By combining nonlinear weights, intensity factors, density factors, and periodic function terms, the update of individual node positions has a certain degree of perturbation and directionality, further improving the algorithm's ability to find local optima and its global optimization effect, and enhancing the algorithm's adaptability and robustness in complex optimization problems.

[0092] ,

[0093] Where t represents the current iteration number and T represents the maximum iteration number.

[0094] It should be noted that as the number of iterations increases, the weighting factor gradually decreases, prompting individuals to rely more on the current optimal solution in the later stages of the search, reducing overexploration and increasing the weight of local fine-tuning search. This adjustment allows the algorithm to maintain strong exploration capabilities in the early stages, avoiding getting trapped in local optima, while gradually converging to the global optimum in the later stages. This improves search efficiency, effectively avoids premature convergence, and enhances the stability and accuracy of the optimization process.

[0095] ,

[0096] Where r5 represents a random number between 0 and 1, and S represents the concentration intensity.

[0097] It's important to note that the intensity factor changes with the distance between the individual's position and the global optimum. When the individual is closer to the global optimum, the search intensity is weaker, avoiding over-concentration on known solutions. Conversely, as the individual moves further away from the global optimum, the intensity factor increases, enhancing the exploration capability. This adaptive adjustment mechanism balances the relationship between global and local search, facilitating extensive exploration of the search space early on and focusing on local optimization later, thereby improving the algorithm's convergence speed and avoiding getting trapped in local optima.

[0098] ,

[0099] Where C represents the density constant, and exp represents an exponential function with the natural constant as the base.

[0100] It should be noted that as the number of iterations increases, the density factor gradually decreases, thereby reducing the degree of "intensive exploration" in the search process and prompting individuals to gradually focus on the vicinity of the global optimum. This adjustment allows the optimization algorithm to extensively explore the search space in the early stages, while gradually reducing exploration in the later stages and concentrating resources on a refined search around the optimum. This method effectively balances the relationship between exploration and development, improves optimization efficiency, and enhances the convergence and stability of the algorithm.

[0101] ,

[0102] Where r6 represents a random number between 0 and 1.

[0103] During the honey-collecting phase, update individual location:

[0104] ,

[0105] Here, r7 represents a random number between 0 and 1.

[0106] In this embodiment of the invention, the global optimal solution is used to guide the search direction, ensuring that the individual converges towards a better solution. Through this balanced exploration and development approach, the algorithm can perform a detailed search near the global optimal solution, optimize the convergence process, improve search efficiency, and prevent premature convergence.

[0107] Update the fitness values ​​of each individual honey badger and the global best individual.

[0108] Determine if the current iteration count has reached the maximum iteration count. If yes, output the set of structural parameters represented by the honey badger individual with the highest fitness. Otherwise, return to continue iterating.

[0109] In this embodiment of the invention, the honey badger optimization algorithm aims to reduce the on-resistance and increase the breakdown voltage of silicon carbide power devices, effectively balancing conduction performance and breakdown voltage in complex multi-objective optimization problems. The honey badger optimization algorithm can perform a global search across a wide range of structural parameters, automatically finding the optimal combination of structural parameters, thereby improving the overall performance of the device without sacrificing other performance aspects. Through an adaptive search strategy and refined local optimization, this method ensures optimal conductivity and high-voltage withstand capability in practical applications, improving the efficiency, stability, and reliability of power devices.

[0110] S2: Prepare the N-type substrate 1 according to the optimal structural parameters.

[0111] S3: An N-type drift layer 2, a first current spreading layer 3, and a second current spreading layer 4 are epitaxially grown on an N-type substrate 1 using chemical vapor deposition.

[0112] Chemical vapor deposition (CVD) is a technique commonly used for thin film deposition. It uses chemical reactions to convert gaseous precursors into solid substances and deposit them on the surface of a substrate.

[0113] S4: A first P-type well 5, a first P-type source region 6, and a first N-type source region 7 are formed on the upper part of the first current extension layer 3 by ion implantation technology.

[0114] Ion implantation is a process that accelerates charged ions and precisely controls their energy and quantity to implant them onto the surface of a material, thereby altering its physical and chemical properties. In semiconductor manufacturing, ion implantation is widely used in the doping process to modulate the conductivity of materials by adjusting the type and concentration of dopant.

[0115] S5: A trench for placing the gate G is formed using dry etching technology.

[0116] Dry etching is a process that uses reactive substances in gas or plasma to selectively remove material from its surface.

[0117] S6: Using ion implantation technology, a second P-type well 8, a second P-type source region 9, and a second N-type source region 10 are formed at the bottom of the trench in the first current extension layer 3.

[0118] S7: Sets the gate (G), drain (D), and source (S).

[0119] This invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of this invention. To provide the public with a thorough understanding of this invention, specific details are described in detail in the preferred embodiments, while those skilled in the art will fully understand the invention even without these details. Furthermore, to avoid unnecessary misunderstanding of the essence of this invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the protection scope of the present invention.

Claims

1. A silicon carbide power device, characterized in that, include: Gate, drain, source, N-type substrate, N-type drift layer, first current spread layer, second current spread layer, first P-type well, first P-type source region, first N-type source region, second P-type well, second P-type source region, and second N-type source region; The drain electrode serves as the bottom layer of the device; The N-type substrate is disposed on the drain electrode; The N-type drift layer is disposed on the N-type substrate; The first current spreading layer is on the N-type drift layer; The second current spreading layer is on top of the first current spreading layer; The first P-type well is disposed on the second current spread layer; The first P-type source region and the first N-type source region are disposed between the first P-type well and the source electrode; The first current spread layer is provided with the second P-type well, the second P-type source region and the second N-type source region; The second P-type well surrounds the second P-type source region and the second N-type source region; The source electrode forms a trench extending toward the first current spreading layer, and the gate electrode is disposed in the trench; The gate is located above the second N-type source region; Silicon carbide power devices also include: a third P-type source region and an N-type base layer; The first N-type source region is disposed between the first P-type source region and the third P-type source region, the third P-type source region is located on the side of the first P-type source region away from the source electrode, and the first P-type source region is located on the side of the first P-type source region away from the gate electrode. An N-type base layer is provided between the first P-type well, the third P-type source region, and the first N-type source region as a carrier transport path. The first P-type well, the third P-type source region, the first N-type source region, and the gate form a PN junction gate, and the conduction capability of the device is controlled by the PN junction gate.

2. The silicon carbide power device according to claim 1, characterized in that, The gate adopts a split gate structure.

3. The silicon carbide power device according to claim 1, characterized in that, The gate is fin-shaped.

4. The silicon carbide power device according to claim 1, characterized in that, The main impurity doping concentrations of the first P-type well and the second P-type well are the same.

5. The silicon carbide power device according to claim 4, characterized in that, The primary impurity in both the first P-type well and the second P-type well is boron.

6. The silicon carbide power device according to claim 1, characterized in that, A channel layer is formed along the wall of the trench; The channel layer is electrically connected to the first current spreading layer and the second current spreading layer; The doping concentration of impurities in the channel layer varies non-uniformly in the vertical direction.

7. The silicon carbide power device according to claim 6, characterized in that, The channel layer is vertically divided into a first sub-channel layer that is further away from the source electrode and a second sub-channel layer that is closer to the source electrode; The doping concentration of impurities in the second sub-channel layer is greater than that in the first sub-channel layer.

8. A method for manufacturing a silicon carbide power device, characterized in that, The method for manufacturing the silicon carbide power device according to any one of claims 1 to 7 comprises: S1: Using simulation technology, with the goal of improving the performance of the silicon carbide power device, determine the optimal structural parameters of the silicon carbide power device; S2: Prepare an N-type substrate according to the optimal structural parameters described above; S3: An N-type drift layer, a first current spreading layer, and a second current spreading layer are epitaxially grown on an N-type substrate using chemical vapor deposition technology. S4: Using ion implantation technology, a first P-type well, a first P-type source region, and a first N-type source region are formed on the upper part of the first current extension layer; S5: A trench for placing the gate is formed using dry etching technology; S6: Using ion implantation technology, a second P-type well, a second P-type source region, and a second N-type source region are formed in the first current extension layer at the bottom of the trench; S7: Set the gate, drain, and source.

9. The manufacturing method according to claim 8, characterized in that, Specifically, S1 is: With the goal of reducing the on-resistance and increasing the breakdown voltage of the silicon carbide power device, the optimal structural parameters of the silicon carbide power device are determined by searching using the honey badger optimization algorithm.

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