Trench substrate lead-out structure, manufacturing method thereof and semiconductor device
By designing a trench substrate extraction structure with a metal semiconductor structure in semiconductor manufacturing, the problem of difficulty in preventing latch up in the prior art is solved, and more efficient substrate carrier collection and chip stability improvement are achieved.
Patent Information
- Application Number
- CN202311597271.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-27
- Publication Date
- 2025-05-30
AI Technical Summary
In the existing semiconductor manufacturing technology, it is difficult to effectively prevent the latch up (latch up) from occurring, resulting in chip failure.
A trench substrate lead-out structure is designed, including forming a heavily doped region in the substrate and providing a metal semiconductor structure on its side, the metal semiconductor structure extending from the top of the heavily doped region to the bottom of the trench isolation structure, and the bottom of the trench isolation structure is at least partially covered by the metal semiconductor structure.
By increasing the collection area of substrate carriers, the current formed by substrate carriers is effectively collected, preventing latch up and improving the reliability and stability of the chip.
Smart Images
Figure CN120076386A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a trench substrate lead-out structure, a manufacturing method of a trench substrate lead-out structure, and a manufacturing method of an isolation structure. Background Art
[0002] The lead-out of the substrate in a semiconductor is a very important structure, which can effectively collect the hole current from the substrate and prevent the occurrence of latch up, resulting in chip failure. Summary of the Invention
[0003] Based on this, it is necessary to provide a trench substrate lead-out structure with a better effect of preventing latch up.
[0004] A trench substrate lead-out structure includes: a heavily doped region, which is located in the substrate and has the same conductivity type as the substrate, and the doping concentration of the heavily doped region is greater than that of the substrate; a trench isolation structure, which is located on the side of the heavily doped region; a metal-semiconductor structure, which extends from the top of the heavily doped region to the side of the trench isolation structure close to the heavily doped region and continues to extend to the bottom of the trench isolation structure, and at least part of the bottom of the trench isolation structure is covered by the metal-semiconductor structure, or there is no metal-semiconductor structure at the bottom of the trench isolation structure.
[0005] In the above trench substrate lead-out structure, a metal-semiconductor structure is arranged on the side of the heavily doped region, which has a large collection area of substrate carriers, can more effectively collect the current formed by substrate carriers, and prevent the occurrence of latch up.
[0006] In one embodiment, the trench isolation structure includes a voltage-resistant part and a metal-semiconductor coating part located between the voltage-resistant part and the heavily doped region, and the metal-semiconductor structure is located on the side, bottom of the metal-semiconductor coating part and the top of the heavily doped region.
[0007] In one embodiment, the depth of the voltage-resistant part is greater than the depth of the metal-semiconductor coating part.
[0008] In one embodiment, the depth of the voltage-resistant part is equal to the depth of the metal-semiconductor coating part.
[0009] In one embodiment, the depth of the voltage-resistant part is less than the depth of the metal-semiconductor coating part, and the metal-semiconductor structure is arranged on the outer surface of the part where the depth of the metal-semiconductor coating part is greater than that of the voltage-resistant part.
[0010] In one embodiment, the material of the metal-semiconductor structure is metal silicide.
[0011] In one embodiment, the material of the trench isolation structure is silicon oxide.
[0012] In one embodiment, the conductive types of the substrate and the heavily doped region are P-type.
[0013] It is also necessary to provide a semiconductor device.
[0014] A semiconductor device includes the trench substrate lead-out structure described in any of the foregoing embodiments, and further includes a conductive structure in a contact hole located on the heavily doped region, and a metal interconnect on the conductive structure; the bottom of the conductive structure is electrically connected to the metal-semiconductor structure, and the top of the conductive structure is electrically connected to the metal interconnect.
[0015] The above semiconductor device has a trench substrate lead-out structure with a metal-semiconductor structure disposed on the side of the heavily doped region, having a large substrate carrier collection area, and can more effectively collect the current formed by substrate carriers to prevent latch up from occurring.
[0016] It is also necessary to provide a manufacturing method of a trench substrate lead-out structure.
[0017] A manufacturing method of a trench substrate lead-out structure includes:
[0018] Forming a total trench in the substrate; forming a heavily doped region in the substrate on the side of the total trench, the conductive type of the heavily doped region being the same as that of the substrate; forming a metal-semiconductor structure; the metal-semiconductor structure extends from the top of the heavily doped region to the side of the total trench close to the heavily doped region and continues to extend to the bottom of the total trench, and a part of the bottom of the total trench forms the metal-semiconductor structure, or there is no metal-semiconductor structure at the bottom of the total trench; filling a first insulating material in the total trench.
[0019] The above manufacturing method of the trench substrate lead-out structure has a metal-semiconductor structure disposed on the side of the heavily doped region, having a large substrate carrier collection area, and can more effectively collect the current formed by substrate carriers to prevent latchup from occurring.
[0020] In one embodiment, the total trench includes a first trench and a second trench. The step of forming the total trench in the substrate includes: forming a first trench in the substrate; filling a second insulating material in the first trench; forming a second trench communicating with the first trench on the side surface of the first trench; the step of forming a heavily doped region in the substrate on the side surface of the total trench includes forming a heavily doped region in the substrate on the side surface of the second trench; the metal-semiconductor structure is formed on the top of the heavily doped region, the bottom of the second trench, and the side surface of the second trench close to the heavily doped region; the step of filling a first insulating material in the total trench includes filling a first insulating material in the second trench.
[0021] In one embodiment, the step of forming a heavily doped region in the substrate on the side surface of the second trench forms the heavily doped region by ion implantation at an inclined angle.
[0022] In one embodiment, before the step of forming a first trench in the substrate, the step of forming a hard mask on the substrate is further included; the step of forming a first trench in the substrate etches the substrate with the hard mask as an etching stop layer to form the first trench; the step of forming a second trench communicating with the first trench on the side surface of the first trench includes: photolithographing and etching the hard mask to remove the hard mask directly above the position where the second trench is to be formed; etching the substrate with the remaining hard mask as an etching stop layer to form the second trench; after the step of filling a first insulating material in the second trench, the following steps are further included: removing the hard mask; performing ion implantation on the top of the heavily doped region, and implanting ions of the same conductivity type as the heavily doped region; wherein, the metal-semiconductor structure on the top of the heavily doped region is formed after the step of performing ion implantation on the top of the heavily doped region.
[0023] In one embodiment, the step of forming a hard mask on the substrate includes: forming a pad oxide layer on the upper surface of the substrate; forming a hard mask on the pad oxide layer.
[0024] In one embodiment, the hard mask is a nitride layer.
[0025] In one embodiment, the material of the nitride layer is silicon nitride. Description of the Drawings
[0026] To better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, and the currently understood best mode of these inventions.
[0027] Figure 1a is a schematic cross-sectional structure diagram of an exemplary trench substrate lead-out structure filled with polysilicon, Figure 1b is a schematic cross-sectional structure diagram of an exemplary trench substrate lead-out structure filled with tungsten;
[0028] Figure 2a is a schematic cross-sectional structure diagram of a trench substrate lead-out structure in an embodiment of the present application, Figure 2b is a schematic cross-sectional structure diagram of a trench substrate lead-out structure in another embodiment of the present application, Figure 2c is a schematic cross-sectional structure diagram of a trench substrate lead-out structure in yet another embodiment of the present application;
[0029] Figure 3 is a flowchart of a manufacturing method of a trench substrate lead-out structure in an embodiment of the present application;
[0030] Figure 4 is a schematic diagram of forming a pad oxide layer and a hard mask layer on a substrate in a manufacturing method of a trench substrate lead-out structure in an embodiment of the present application;
[0031] Figure 5 is a schematic cross-sectional structure diagram of a semiconductor structure after step S310 is completed in an embodiment of the present application;
[0032] Figure 6 is a schematic cross-sectional structure diagram of a semiconductor structure after step S320 is completed in an embodiment of the present application;
[0033] Figure 7 is a schematic diagram of patterning a hard mask before etching a second trench in an embodiment of the present application;
[0034] Figure 8a is a schematic cross-sectional structure diagram of a semiconductor structure after step S330 is completed in an embodiment of the present application, Figure 8b is a schematic cross-sectional structure diagram of a semiconductor structure after step S330 is completed in another embodiment of the present application, Figure 8c is a schematic cross-sectional structure diagram of a semiconductor structure after step S330 is completed in yet another embodiment of the present application;
[0035] Figure 9a is a schematic cross-sectional structure diagram of a semiconductor structure after forming a metal-semiconductor structure at the junction of a second trench and a silicon substrate in an embodiment of the present application, Figure 9b is a schematic cross-sectional structure diagram of a semiconductor structure after forming a metal-semiconductor structure at the junction of a second trench and a silicon substrate in another embodiment of the present application, Figure 9c is a schematic cross-sectional structure diagram of a semiconductor structure after forming a metal-semiconductor structure at the junction of a second trench and a silicon substrate in yet another embodiment of the present application;
[0036] Figure 10aIt is a schematic cross-sectional structure diagram of the trench substrate lead-out structure after step S360 in an embodiment of the present application. Figure 10b It is a schematic cross-sectional structure diagram of the trench substrate lead-out structure after step S360 in another embodiment of the present application. Figure 10c It is a schematic cross-sectional structure diagram of the trench substrate lead-out structure after step S360 in yet another embodiment of the present application. Detailed implementation manners
[0037] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present invention is thorough and complete.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used in the description of the present invention herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.
[0039] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or part discussed below may be denoted as a second element, component, region, layer or part without departing from the teachings of the present invention.
[0040] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.
[0041] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.
[0042] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. As such, variations from the shown shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present invention should not be limited to the particular shapes of regions shown herein but include shape deviations due to, for example, manufacturing. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation can result in some implantation in the region between that buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present invention.
[0043] The semiconductor field vocabulary used herein is common technical vocabulary for those skilled in the art. For example, for P-type and N-type impurities, to distinguish the doping concentration, simply P+ type represents P-type with a heavy doping concentration, P-type represents P-type with a medium doping concentration, P- type represents P-type with a light doping concentration, N+ type represents N-type with a heavy doping concentration, N-type represents N-type with a medium doping concentration, and N- type represents N-type with a light doping concentration.
[0044] An exemplary trench substrate lead-out structure is to fill polysilicon in the trench. See Figure 1a , a trench is formed in the P-type substrate (P-sub), the side wall of the trench is the oxide layer 12, the trench is filled with polysilicon 14, and the bottom of the polysilicon 14 is the substrate lead-out region P+. However, for the devices of the P-type substrate, P-type polysilicon needs to be filled in the trench, which is not compatible with the conventional gate polysilicon.
[0045] Another exemplary trench substrate lead-out structure is to fill tungsten metal in the trench. See Figure 1b , a trench is formed in the P-type substrate (P-sub), the side wall of the trench is the oxide layer 12, the trench is filled with tungsten metal 16, and the bottom of the tungsten metal 16 is the substrate lead-out region P+. This process can only be carried out in the back-end process (Back End of Line, BEOL) of chip manufacturing, and the process portability is not good. On the other hand, whether polysilicon or tungsten metal is filled in the trench, there will be relatively large stress, which is not conducive to process integration.
[0046] This application proposes a new type of trench substrate lead-out structure, which can effectively collect the hole current from the substrate and prevent the occurrence of latch up.
[0047] Figure 2a is a schematic cross-sectional structure diagram of the trench substrate lead-out structure in an embodiment of this application, including a substrate 210, a trench isolation structure 220, a heavily doped region 230, and a metal-semiconductor structure 240. The heavily doped region 230 is located in the substrate 210 and has the same conductivity type as the substrate 210, and the doping concentration of the heavily doped region 230 is greater than that of the substrate 210. In Figure 2a the shown embodiment, the substrate 210 is a P-type substrate (P-sub), and the heavily doped region 230 is a P+ region. The trench isolation structure 220 is located on the side of the heavily doped region 230. The trench isolation structure 220 is a structure formed by filling an insulating material in the trench. A metal-semiconductor structure 240 is provided on the top of the heavily doped region 230, and the metal-semiconductor structure 240 extends from the top of the heavily doped region 230 to the side of the trench isolation structure 220 close to the heavily doped region 230. In one embodiment, the metal-semiconductor structure 240 extends to the bottom of the trench isolation structure 220 so that it is partially or completely covered by the metal-semiconductor structure 240; in another embodiment, the metal-semiconductor structure 220 is not provided at the bottom of the trench isolation structure 240. A contact hole is provided on the top of the metal-semiconductor structure 240 to lead out the substrate potential. Therefore, the metal-semiconductor structure 240 needs to select a material with good electrical contact performance so that the metal in the contact hole forms good electrical contact with the underlying heavily doped region 230 (i.e., has a low contact resistance).
[0048] For the above-mentioned trench substrate lead-out structure, a metal-semiconductor structure 240 is disposed on the side of the heavily doped region 230, which has a large collection area of substrate carriers, can more effectively collect the current formed by the substrate carriers, and prevent latch-up from occurring.
[0049] In an embodiment of the present application, the substrate 210 is a silicon substrate. The insulating material filled in the trenches of the trench isolation structure 220 is silicon oxide, such as silicon dioxide. Replacing the filling of tungsten metal or polysilicon with silicon oxide in the trenches has lower stress and is beneficial to process integration.
[0050] In an embodiment of the present application, the material of the metal-semiconductor structure 240 is metal silicide. Specifically, the material of the metal silicide can be CoSi x , NiSi x , PtSi x or a combination of these compounds.
[0051] In Figure 2a the illustrated embodiment, the trench isolation structure 220 includes a voltage-resistant portion 222 and a metal-semiconductor coating portion 224 located between the voltage-resistant portion 222 and the heavily doped region 230. The depth of the voltage-resistant portion 222 is denoted as D1, and the depth of the metal-semiconductor coating portion 224 is denoted as D2. The outer surface of the metal-semiconductor coating portion 224 except the top is coated with the metal-semiconductor structure 240. The metal-semiconductor structure 240 is not provided on the outer surface of the voltage-resistant portion 222. The voltage-resistant portion 222 is used to isolate the metal-semiconductor structure 240 (and the heavily doped region 230) from other device structures to increase the breakdown voltage between the substrate lead-out end and other device structures. The insulating materials filled in the voltage-resistant portion 222 and the metal-semiconductor coating portion 224 can be the same or different.
[0052] In Figure 2a the illustrated embodiment, the depth D1 of the voltage-resistant portion 222 is greater than the depth D2 of the metal-semiconductor coating portion 224. For the trench isolation structure 220, the metal-semiconductor structure 240 is disposed on the bottom surface of the metal-semiconductor coating portion 224 and the side surface of the metal-semiconductor coating portion 224 close to the heavily doped region 230.
[0053] Figure 2b In another embodiment of the present application, the cross-sectional structure schematic diagram of the trench substrate lead-out structure, the main difference from the Figure 2a illustrated embodiment is that the depth D1 of the voltage-resistant portion 222 ( Figure 2b not marked therein) is equal to the depth of the metal-semiconductor coating portion ( Figure 2bThe depth D2 of the voltage withstand portion 222 (not labeled in the figure). For the trench isolation structure 220, the metal semiconductor structure 240 is also disposed on the bottom surface of the metal semiconductor coating portion 224 and on the side surface of the metal semiconductor coating portion 224 near the heavily doped region 230.
[0054] Figure 2c A schematic cross-sectional structure diagram of a trench substrate lead-out structure in another embodiment of the present application, and its main difference from the Figure 2a embodiment shown is that the depth D1 of the voltage withstand portion 222 ( Figure 2c not labeled in the figure) is less than the depth D2 of the metal semiconductor coating portion ( Figure 2c not labeled in the figure). For the trench isolation structure 220, the metal semiconductor structure 240 is disposed on the outer surface of the portion of the metal semiconductor coating portion 224 where the depth is greater than that of the voltage withstand portion 222, and on the side surface of the metal semiconductor coating portion 224 near the heavily doped region 230.
[0055] The present application correspondingly provides a semiconductor device, which includes the trench substrate lead-out structure described in any of the foregoing embodiments, and further includes a conductive structure in a contact hole on the heavily doped region 230 and a metal interconnect on the conductive structure. The bottom of the conductive structure is electrically connected to the metal semiconductor structure 240, and the top of the conductive structure is electrically connected to the metal interconnect. The material of the conductive structure can be metal and / or alloy, such as a tungsten plug.
[0056] The above semiconductor device has a trench substrate lead-out structure with a metal semiconductor structure 240 disposed on the side surface of the heavily doped region 230, has a large collection area for substrate carriers, can more effectively collect the current formed by the substrate carriers, and prevent latch up from occurring.
[0057] The present application correspondingly provides a manufacturing method for a trench substrate lead-out structure, including the following steps:
[0058] Form a total trench in the substrate;
[0059] Form a heavily doped region in the substrate on the side surface of the total trench, and the conductivity type of the heavily doped region is the same as that of the substrate;
[0060] Form a metal semiconductor structure; the metal semiconductor structure extends from the top of the heavily doped region to the side surface of the total trench near the heavily doped region and continues to extend to the bottom of the total trench, and a metal semiconductor structure is formed at a partial position at the bottom of the total trench, or there is no metal semiconductor structure at the bottom of the total trench;
[0061] Fill the total trench with a first insulating material.
[0062] In one embodiment of the present application, the total trench includes a first trench and a second trench. The step of forming the total trench in the substrate includes: forming a first trench in the substrate; filling a second insulating material in the first trench; forming a second trench communicating with the first trench on the side surface of the first trench; the step of forming a heavily doped region in the substrate on the side surface of the total trench includes forming a heavily doped region in the substrate on the side surface of the second trench; the metal-semiconductor structure is formed on the top of the heavily doped region, the bottom of the second trench, and the side surface of the second trench close to the heavily doped region; the step of filling the first insulating material in the total trench includes filling the first insulating material in the second trench.
[0063] In one embodiment of the present application, the step of forming a heavily doped region in the substrate on the side surface of the second trench forms the heavily doped region by ion implantation at an inclined angle.
[0064] In one embodiment of the present application, before the step of forming the first trench in the substrate, the step of forming a hard mask on the substrate is further included; the step of forming the first trench in the substrate etches the substrate using the hard mask as an etching barrier layer to form the first trench; the step of forming a second trench communicating with the first trench on the side surface of the first trench includes: performing photolithography and etching on the hard mask to remove the hard mask directly above the position where the second trench is to be formed; etching the substrate using the remaining hard mask as an etching barrier layer to form the second trench; after the step of filling the first insulating material in the second trench, the following steps are further included: removing the hard mask; performing ion implantation on the top of the heavily doped region, injecting ions of the same conductivity type as the heavily doped region; wherein, the metal-semiconductor structure on the top of the heavily doped region is formed after the step of performing ion implantation on the top of the heavily doped region.
[0065] In one embodiment of the present application, the step of forming a hard mask on the substrate includes: forming a pad oxide layer on the upper surface of the substrate; forming a hard mask on the pad oxide layer.
[0066] Figure 3 It is a flowchart of a manufacturing method for a trench substrate lead-out structure in one embodiment of the present application, including the following steps:
[0067] S310, forming a first trench in the substrate.
[0068] Obtain a wafer including a semiconductor substrate (substrate 410), and etch to form a first trench 421 extending from the upper surface of the substrate 410 into the substrate 410. In one embodiment of the present application, the hard mask 460 is used as an etching barrier layer to etch the substrate 410 to form the first trench 421.
[0069] Referring to Figure 4 , a hard mask 460 can be first formed on the substrate 410, and then the hard mask 460 is patterned to remove the hard mask 460 directly above the position where the first trench 421 is to be formed. Then, the substrate 410 is etched to form the first trench 421 with a depth of D1. Referring to Figure 5 . The hard mask 460 can be patterned by photolithography and etching processes. Specifically, a photoresist is coated on the hard mask 460, and then the photoresist is exposed using a corresponding photomask. After development, an etching window having the same cross-section as the first trench 421 is obtained, and then the hard mask 460 is etched, so as to remove the hard mask 460 directly above the position of the first trench 421. In an embodiment of the present application, the photoresist is removed before etching the substrate 410 to form the first trench 421.
[0070] In an embodiment of the present application, before forming the hard mask 460, it further includes the step of forming a pad oxide layer (PAD Oxide) 450 on the upper surface of the substrate 410. After forming the pad oxide layer 450, the hard mask 460 is formed on the pad oxide layer 450. In an embodiment of the present application, the pad oxide layer 450 is formed by thermal oxidation.
[0071] In an embodiment of the present application, the hard mask 460 is a nitride layer, for example, it can be a silicon nitride layer. In an embodiment of the present application, the hard mask 460 is formed by depositing silicon nitride. In Figure 4 and Figure 5 the illustrated embodiment, the substrate 410 is a P-type substrate (P-sub).
[0072] S320, filling an insulating material in the first trench.
[0073] In an embodiment of the present application, filling the insulating material 422a includes depositing silicon oxide, such as silicon dioxide. In an embodiment of the present application, it further includes the step of polishing the upper surface of the wafer by chemical mechanical planarization (CMP) to remove the excess insulating material 422a. Refer to Figure 6 .
[0074] S330, forming a second trench communicating with the first trench on the side surface of the first trench.
[0075] In an embodiment of the present application, the hard mask 460 is lithographed and etched to remove the hard mask 460 directly above the position where the second trench 423 is to be formed. Then, using the remaining hard mask 460 as an etching stop layer, the substrate 410 is etched to form the second trench 423.
[0076] In one embodiment of the present application, a photoresist 492 is coated on the hard mask 460, and then the photoresist is exposed using a corresponding photomask. After development, an etching window having the same cross-section as the second trench 423 is obtained. Then, the hard mask 460 is etched to remove the hard mask 460 directly above the position of the second trench 423. Refer to Figure 7 . After that, the photoresist 492 is removed. Using the remaining hard mask 460 as an etching stop layer, the substrate 410 is etched to form a second trench 423 with a depth of D2. Refer to Figure 8a .
[0077] Figure 8b And Figure 8c are schematic diagrams of the semiconductor structure after step S330 is completed in two other embodiments. The main difference from the embodiment shown in Figure 8a is whether the first trench 421 or the second trench 423 is deeper. In the embodiment shown in Figure 8a , the depth D1 of the first trench 421 is greater than the depth D2 of the second trench 423. In the embodiment shown in Figure 8b , the depth D1 is equal to the depth D2; in the embodiment shown in Figure 8c , the depth D1 is less than the depth D2.
[0078] S340, a heavily doped region is formed in the substrate on the side of the second trench.
[0079] The conduction type of the heavily doped region 430 is the same as that of the substrate 410. In one embodiment of the present application, the heavily doped region 430 is formed by ion implantation at an inclined angle, that is, the P+ region in Figure 9a . In the embodiment shown in Figure 9a , the heavily doped region 430 is also formed in the substrate 410 below the second trench 423.
[0080] S350, a metal-semiconductor structure is formed.
[0081] A metal-semiconductor structure 440 is formed at the junction of the second trench 423 and the heavily doped region 430 and at the junction of the second trench 423 and the substrate 410. In one embodiment of the present application, the material of the metal-semiconductor structure 440 is a metal silicide. In one embodiment of the present application, the material of the metal silicide can be CoSi x , NiSi x , PtSi x or a combination of these compounds.
[0082] Figure 8b The structure shown is obtained after performing steps S340 and S350 Figure 9b The structure shown. Figure 8c The structure shown is obtained after performing steps S340 and S350 Figure 9cThe structure shown.
[0083] S360, filling the insulating material in the second trench.
[0084] In one embodiment of the present application, filling the insulating material includes depositing silicon oxide, such as silicon dioxide.
[0085] For the manufacturing method of the above trench substrate lead-out structure, a metal-semiconductor structure 440 is arranged on the side of the heavily doped region 430, which has a larger collection area of substrate carriers, can more effectively collect the current formed by the substrate carriers, and prevent latch up from occurring.
[0086] In one embodiment of the present application, after step S360, it further includes a step of polishing the upper surface of the wafer by chemical mechanical planarization (CMP) to remove the excess insulating material.
[0087] In one embodiment of the present application, after step S360, it further includes the steps of removing the hard mask 460 and the excess insulating material. In one embodiment of the present application, the insulating material (the insulating material deposited in steps S320 and S360) above the upper surface of the substrate 410 is removed by wet etching, and then the hard mask 460 is removed.
[0088] Refer to Figure 10a , after removing the excess insulating material, the insulating material in the first trench 421 (not labeled in Figure 10a ) serves as the voltage-resistant part 422, and the insulating material in the second trench 423 (not labeled in Figure 10a ) serves as the metal-semiconductor coating part 424. The depth of the voltage-resistant part 422 is the depth D1 of the trench 421, and the depth of the metal-semiconductor coating part 424 is the depth D2 of the trench 423. The outer surface of the metal-semiconductor coating part 424 except the top is coated by the metal-semiconductor structure 440. The outer surface of the voltage-resistant part 422 is not provided with the metal-semiconductor structure 440. The voltage-resistant part 422 is used to isolate the metal-semiconductor structure 440 (and the heavily doped region 430) from other device structures to increase the breakdown voltage between the substrate lead-out end and other device structures.
[0089] In one embodiment of the present application, after removing the hard mask 460, it further includes a step of ion implanting the top of the heavily doped region 430. Since step S340 is an inclined implantation, the impurity ion concentration at the top of the heavily doped region 430 is insufficient and needs to be supplemented by implantation. In one embodiment of the present application, after this supplementary implantation step, it further includes removing the pad oxide layer 450 on the heavily doped region 430, and then forming the metal-semiconductor structure 440 on the top of the heavily doped region 430, refer to Figure 10a .
[0090] Figure 9b The structure shown is obtained after forming a metal-semiconductor structure on top of the heavily doped region Figure 10b The structure shown, Figure 9c The structure shown is obtained after forming a metal-semiconductor structure on top of the heavily doped region Figure 10c The structure shown.
[0091] It should be understood that although the steps in the flowcharts of the present application are shown sequentially in the direction of the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless otherwise clearly stated in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the present application may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential either, but can be executed alternately or in rotation with at least some of the steps or stages in other steps or other steps.
[0092] In the description of this specification, the descriptions with reference to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0093] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.
[0094] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.
Claims
1. A trench substrate lead-out structure, characterized in that, it includes: A heavily doped region, located in the substrate and having the same conductivity type as the substrate, and the doping concentration of the heavily doped region is greater than that of the substrate; A trench isolation structure, located on the side of the heavily doped region; A metal-semiconductor structure, extending from the top of the heavily doped region to the side of the trench isolation structure close to the heavily doped region, and continuing to extend to the bottom of the trench isolation structure, at least part of the bottom of the trench isolation structure is covered by the metal-semiconductor structure, or the metal-semiconductor structure is not provided at the bottom of the trench isolation structure.
2. The trench substrate lead-out structure according to claim 1, characterized in that, The trench isolation structure includes a voltage-resistant part and a metal-semiconductor coating part located between the voltage-resistant part and the heavily doped region, and the metal-semiconductor structure is located on the side, bottom of the metal-semiconductor coating part and the top of the heavily doped region.
3. The trench substrate lead-out structure according to claim 2, characterized in that, The depth of the voltage-resistant part is greater than the depth of the metal-semiconductor coating part; or The depth of the voltage-resistant part is equal to the depth of the metal-semiconductor coating part; or The depth of the voltage-resistant part is less than the depth of the metal-semiconductor coating part, and the metal-semiconductor structure is provided on the outer surface of the part where the depth of the metal-semiconductor coating part is greater than the depth of the voltage-resistant part.
4. The trench substrate lead-out structure according to claim 1, characterized in that, The material of the metal-semiconductor structure is metal silicide.
5. The trench substrate lead-out structure according to claim 1, characterized in that, The material of the trench isolation structure is silicon oxide.
6. A semiconductor device, characterized in that, it includes the trench substrate lead-out structure according to any one of claims 1-5, and further includes a conductive structure in a contact hole located on the heavily doped region, and a metal interconnect on the conductive structure; the bottom of the conductive structure is electrically connected to the metal-semiconductor structure, and the top of the conductive structure is electrically connected to the metal interconnect.
7. A manufacturing method of a trench substrate lead-out structure, including: Forming a total trench in the substrate; Forming a heavily doped region in the substrate on the side of the total trench, and the conductivity type of the heavily doped region is the same as that of the substrate; Forming a metal-semiconductor structure; The metal-semiconductor structure extends from the top of the heavily doped region to the side of the total trench close to the heavily doped region, and continues to extend to the bottom of the total trench, and a part of the bottom of the total trench forms the metal-semiconductor structure, or there is no metal-semiconductor structure at the bottom of the total trench; Filling a first insulating material in the total trench.
8. The manufacturing method of the trench substrate lead-out structure according to claim 7, characterized in that, The total trench includes a first trench and a second trench, and the step of forming a total trench in the substrate includes: Forming a first trench in the substrate; Filling a second insulating material in the first trench; Forming a second trench communicating with the first trench on the side of the first trench; The step of forming a heavily doped region in the substrate on the side of the total trench includes forming a heavily doped region in the substrate on the side of the second trench; the metal-semiconductor structure is formed on the top of the heavily doped region, the bottom of the second trench, and the side surface of the second trench close to the heavily doped region; the step of filling the first insulating material in the total trench includes filling the first insulating material in the second trench.
9. The manufacturing method of the trench substrate lead-out structure according to claim 8, wherein, the step of forming a heavily doped region in the substrate on the side of the second trench forms the heavily doped region by ion implantation at an inclined angle.
10. The manufacturing method of the trench substrate lead-out structure according to claim 8 or 9, wherein, before the step of forming the first trench in the substrate, a step of forming a hard mask on the substrate is further included; the step of forming the first trench in the substrate etches the substrate using the hard mask as an etching stop layer to form the first trench; the step of forming a second trench communicating with the first trench on the side of the first trench includes: photolithographing and etching the hard mask to remove the hard mask directly above the position where the second trench is to be formed; etching the substrate using the remaining hard mask as an etching stop layer to form the second trench; after the step of filling the first insulating material in the second trench, it further includes: removing the hard mask; performing ion implantation on the top of the heavily doped region, implanting ions of the same conductivity type as the heavily doped region; wherein, the metal-semiconductor structure on the top of the heavily doped region is formed after the step of performing ion implantation on the top of the heavily doped region.