Method for manufacturing a semiconductor structure, semiconductor structure, semiconductor device

Abstract

The application provides a semiconductor structure preparation method, a semiconductor structure and a semiconductor device. The preparation method comprises the following steps: providing a substrate; the substrate comprises a substrate and a first oxide layer formed on the surface of the substrate; wherein the substrate comprises a first region and a second region; forming a first gate material layer on the first oxide layer; wherein the first gate material layer comprises a first sacrificial gate material part located on the first region and a first gate material part located on the second region; using the first gate material part as a mask, removing the first sacrificial gate material part and a first sacrificial oxide part based on a dry etching process, and forming a second gate oxide part on the surface of the first region; wherein the thickness of the second gate oxide part is different from the thickness of the first gate oxide part. In this way, the problem of photoresist falling off in the process of preparing a double-gate oxide layer can be improved, the quality of the double-gate oxide layer is improved, and thus the performance and yield of the semiconductor structure are ensured.

Description

Technical Field

[0001] The embodiments in this application relate to the field of semiconductor fabrication technology, and in particular to a method for fabricating a semiconductor structure, a semiconductor structure, and a semiconductor device. Background Technology

[0002] In semiconductor manufacturing, dual gate oxide (DVO) technology is used to integrate transistors with different operating voltage requirements on the same chip. With the continuous development of integrated circuits, especially for mixed-signal and radio frequency applications, there is a need to integrate low-voltage core logic circuits and high-voltage input / output (I / O) circuits simultaneously on the same chip. Traditional single-gate oxide processes cannot meet these diverse needs because low-voltage circuits require thinner gate oxide layers to improve speed and reduce power consumption, while high-voltage circuits require thicker gate oxide layers to prevent breakdown and leakage current.

[0003] To address this, the Dual GOX process can fabricate gate oxide layers of varying thicknesses in different regions of the substrate to meet the voltage requirements of those regions. The Dual GOX process involves first growing a thicker gate oxide layer across the entire substrate surface, then removing the thick oxide layer in certain areas using photolithography and wet etching techniques, and finally growing a thinner gate oxide layer in those areas.

[0004] However, during the wet etching process of Dual GOX to remove the thick oxide layer covering a certain area, photoresist detachment is prone to occur, resulting in defects in the subsequently grown thin oxide layer, which affects the semiconductor structure performance and yield. Summary of the Invention

[0005] In view of this, several embodiments of this application aim to provide a method for fabricating a semiconductor structure, a semiconductor structure, and a semiconductor device, which can improve the photoresist shedding problem that occurs during the fabrication of a double gate oxide layer, improve the quality of the double gate oxide layer, and thus ensure the performance and yield of the semiconductor structure.

[0006] One embodiment of this application provides a method for fabricating a semiconductor structure, comprising: providing a substrate; the substrate including a substrate and a first oxide layer formed on the surface of the substrate; wherein the substrate includes a first region and a second region; the first oxide layer including a first sacrificial oxide portion located on the first region and a first gate oxide portion located on the second region; forming a first gate material layer on the first oxide layer; wherein the first gate material layer includes a first sacrificial gate material portion located on the first region and a first gate material portion located on the second region; using the first gate material portion as a mask, removing the first sacrificial gate material portion and the first sacrificial oxide portion based on a dry etching process, and forming a second gate oxide portion on the surface of the first region; wherein the thickness of the second gate oxide portion is different from the thickness of the first gate oxide portion.

[0007] Optionally, after the step of forming a first gate material layer on the first oxide layer, the method for fabricating the semiconductor structure further includes:

[0008] Optionally, the second oxide layer includes a second sacrificial oxide portion located on the first region and a protective oxide portion located on the second region; during the process of removing the first sacrificial gate material portion and the first sacrificial oxide portion based on the dry etching process, the first gate material portion and the protective oxide portion are used together as a mask, and the second sacrificial oxide portion is removed.

[0009] Optionally, after forming a second gate oxide portion on the surface of the first region, the method for fabricating the semiconductor structure further includes: depositing a second gate material layer on the surface of the second gate oxide portion and the protective oxide portion; wherein the second gate material layer includes a second gate material portion located on the first region and a second sacrificial gate material portion located on the second region; using the protective oxide portion as a planarization stop layer, performing a planarization process on the second gate material layer to make the second gate material portion flush with the first gate material portion.

[0010] Optionally, the step of planarizing the second gate material layer by using the protective oxide portion as a planarization stop layer includes: grinding the second gate material layer to be flush with the planarization stop layer based on a first chemical mechanical polishing process; wherein the second sacrificial gate material portion is removed; grinding the second gate material portion to be flush with the first gate material portion based on a second chemical mechanical polishing process; wherein the planarization stop layer is removed.

[0011] Optionally, after the second gate material layer is polished to be flush with the planarization stop layer based on the first chemical mechanical polishing process, a buffer portion is formed on the side of the planarization stop layer; wherein, during the second chemical mechanical polishing process, the buffer portion protects the remaining portion of the second gate material layer between the surface of the first region and the buffer portion.

[0012] Optionally, the thickness of the first gate oxide portion is greater than the thickness of the second gate oxide portion.

[0013] Optionally, the first region is a low-pressure region and the second region is a high-pressure region.

[0014] Optionally, the gate material of the first gate material layer is the same as that of the second gate material layer.

[0015] One embodiment of this application provides a semiconductor structure, which is prepared using the semiconductor structure preparation method described in any of the foregoing embodiments.

[0016] One embodiment of this application provides a semiconductor device, the semiconductor device comprising the semiconductor structure as described in any of the foregoing embodiments.

[0017] The various embodiments provided in this application have an unexpected effect: by directly forming a first gate material layer on a first oxide layer grown on the substrate surface, and then removing the first sacrificial oxide portion located in the first region using a dry etching process, a second gate oxide portion with a different thickness is formed on the surface of the first region. Since the first sacrificial oxide portion is removed using a dry etching process, the photoresist detachment problem caused by wet etching in related technologies can be reduced. Furthermore, during the dry etching process, the first gate material portion located in the second region of the pre-formed first gate material layer is cleverly used as a mask layer, eliminating the need to introduce a hard mask material. This not only simplifies the process steps but also avoids the impact of removing the hard mask material on the fabricated double-gate oxide layer, thereby improving the quality of the double-gate oxide layer and ensuring the performance and yield of the semiconductor structure. Attached Figure Description

[0018] Figure 1 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of a substrate provided in the method for fabricating a semiconductor structure according to an embodiment of this application.

[0020] Figure 3 This is a schematic diagram of the formation of a first gate material layer and a second oxide layer in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0021] Figure 4 and Figure 5 This is a schematic diagram of the removal of the first sacrificial oxide portion and the first sacrificial gate material portion in the method for fabricating the semiconductor structure provided in the embodiments of this application.

[0022] Figure 6 This is a schematic diagram of the formation of the second gate oxide portion in the method for fabricating the semiconductor structure provided in the embodiments of this application.

[0023] Figure 7 This is a schematic diagram of the formation of a second gate material layer in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0024] Figure 8 This is a schematic diagram of the first CMP process in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0025] Figure 9 This is a schematic diagram of the second CMP process in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0026] Figure 10 This is a schematic diagram of the formation of a gate in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0027] Explanation of reference numerals in the attached figures:

[0028] 10. Substrate; 11. Substrate; 111. First region; 112. Second region; 12. First oxide layer; 13. First gate material layer; 14. Second oxide layer; 121. First sacrificial oxide portion; 122. First gate oxide portion; 131. First sacrificial gate material portion; 132. First gate material portion; 141. Second sacrificial oxide portion; 142. Protective oxide portion; 15. Second gate oxide portion; 16. Second gate material layer; 161. Second gate material portion; 162. Second sacrificial gate material portion; 1611. Buffer portion; 17. First gate structure; 18. Second gate structure. Detailed Implementation

[0029] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0030] In this application, the accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features.

[0031] Unless otherwise stated, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0032] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0033] In the description of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. In other words, they should not be construed as limitations on this application.

[0034] In the description of this application, unless otherwise expressly defined, the terms "installation," "connection," "linking," "fixing," "setting," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can also refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0035] In related technologies, the Dual GOX process typically uses a wet etching method for removing thick oxide layers in areas requiring thin oxide layers. This involves immersing a substrate with photoresist in an acid bath for a certain period to remove the thick oxide layer. However, due to the acid resistance issues of photoresist materials (such as KRF photoresist), their stability decreases in acidic environments. This leads to photoresist detachment from the substrate surface during wet etching, resulting in defects in the thin oxide layer subsequently grown in the Dual GOX process, thus affecting the performance and reliability of the semiconductor structure.

[0036] In response, the engineers improved the process by using dry etching in the thick oxide layer removal step to reduce photoresist detachment. However, using dry etching may present other problems.

[0037] Specifically, compared to wet etching, dry etching processes typically require the introduction of hard mask materials, such as BARC (bottom anti-reflective coating), as a hard mask layer to ensure etching accuracy and provide protection. Therefore, after etching, additional removal of the hard mask material is required, which may lead to problems such as incomplete removal, chemical contamination, and substrate surface damage, thereby affecting the quality of the fabricated dual-gate oxide layer.

[0038] Therefore, it is necessary to provide a method for fabricating semiconductor structures that can improve the quality of the fabricated double-gate oxide layer, thereby ensuring the performance and yield of the semiconductor structure.

[0039] Please see Figures 1-10 One embodiment of this application provides a method for fabricating a semiconductor structure. The method for fabricating the semiconductor structure may include the following steps.

[0040] S110: Provides a substrate.

[0041] In this embodiment, as Figure 2 As shown, the substrate 10 includes a substrate 11 and a first oxide layer 12 formed on the surface of the substrate 11.

[0042] In this embodiment, the substrate 11 can serve as the basic structure of the semiconductor structure, not only providing mechanical support but also influencing the electrical properties of the semiconductor structure, such as operating voltage and carrier mobility, through doping with ions. Specifically, the substrate 11 can be made of silicon (Si), or, depending on the requirements, of other semiconductor materials, such as silicon carbide (SiC) or gallium nitride (GaN).

[0043] In this embodiment, the substrate 11 can be divided into multiple regions with different operating voltage requirements according to different circuit design needs. Each region can be fabricated with a gate oxide layer of different thickness to meet different operating voltage requirements. For example, for regions with high voltage withstand capability and high reliability requirements, the gate oxide layer can be thicker, while for regions with high operability and high flexibility requirements, such as logic circuits, the gate oxide layer can be thinner.

[0044] In this embodiment, the substrate 11 may include a first region 111 and a second region 112. The first region 111 and the second region 112 have different operating voltage requirements. Specifically, the first region 111 may be a low-voltage region with a lower operating voltage requirement, which can be used to form a thinner gate oxide layer. The second region 112 may be a high-voltage region with a higher operating voltage requirement, which can be used to form a thicker gate oxide layer. It should be noted that the voltage requirement mentioned in this application is relative, that is, the second region 112 is higher than the first region 111, and does not necessarily correspond to the voltage values ​​corresponding to high and low voltages in actual applications such as circuit design.

[0045] In this embodiment, the first oxide layer 12 may include a first sacrificial oxide portion 121 located on the first region 111 and a first gate oxide portion 122 located on the second region 112.

[0046] S120: A first gate material layer is formed on the first oxide layer.

[0047] In this embodiment, as Figure 3 As shown, a first gate material layer 13 can be formed directly on the first oxide layer 12, so that it can be used together with the first oxide layer 12 to form the gate structure located in the second region 112 in a subsequent process. Specifically, for example, the material of the first gate material layer 13 can be polysilicon or other gate materials, such as aluminum.

[0048] In this embodiment, the first gate material layer 13 may include a first sacrificial gate material portion 131 located on the first region 111 and a first gate material portion 132 located on the second region 112.

[0049] In this embodiment, after the first gate material layer 13 is formed on the first oxide layer 12, a second oxide layer 14 can be formed on the first gate material layer 13 to serve as a stop layer in the subsequent planarization process. The second oxide layer 14 may also include a second sacrificial oxide portion 141 located on the first region 111 and a protective oxide portion 142 located on the second region 112. In some embodiments, the second oxide layer 14 may not be formed, or a stop layer made of other materials may be formed. In this embodiment, the second oxide layer 14 may be made of the same material as the first oxide layer 12, such as silicon dioxide, to reduce the introduction of new materials in the process, thereby reducing the impact of subsequent removal processes on the semiconductor structure performance or reliability, and simplifying the process. Specifically, the thickness of the second oxide layer 14 may fall within the range of 180 Å to 220 Å. For example, the thickness of the second oxide layer 14 may be 200 Å, or it may be 180 Å, 220 Å, etc.

[0050] S130: Using the first gate material portion as a mask, the first sacrificial gate material portion and the first sacrificial oxide portion are removed by a dry etching process, and a second gate oxide portion is formed on the surface of the first region. The thickness of the second gate oxide portion is different from the thickness of the first gate oxide portion.

[0051] In this embodiment, as Figure 4 and Figure 5 As shown, a photoresist defining the first region 111 can be formed on the second oxide layer 14, and a dry etching process can be used to remove the first sacrificial oxide portion 121, the first sacrificial gate material portion 131, and the second sacrificial oxide portion 141 on the first region 111, thereby exposing the surface of the first region 111. Of course, in some embodiments, if the second oxide layer 14 is not formed, it can be understood that only the first sacrificial oxide portion 121 and the first sacrificial gate material portion 131 on the first region 111 are removed by dry etching. In this embodiment, by adjusting the selectivity ratio of the first gate material layer 13 to the first oxide layer 12, the remaining first gate material portion 132, excluding the first sacrificial gate material portion 131, can serve as a mask, which can, to some extent, replace the hard mask material in related technologies, thereby improving the etching accuracy.

[0052] Of course, in some embodiments, while retaining the protective oxide portion 142 located on the second region 112, the first gate material portion 132 and the protective oxide portion 142 can be used together as a mask for the dry etching process. In this way, the protective oxide portion 142 can be used to protect the first gate material portion 132 during the dry etching process, and the protective oxide portion 142 can also be used as a mask in the subsequent step of growing the second gate oxide portion on the surface of the first region 111.

[0053] Next, as Figure 6 As shown, using the first gate material portion 132 and the protective oxide portion 142 as masks, a second gate oxide portion 15 with a different thickness than the first oxide layer 12 is grown on the surface of the first region 111, thereby fabricating a double-gate oxide layer located on the surface of the substrate 11. Specifically, both the second gate oxide portion 15 and the first oxide layer 12 can be silicon dioxide, and the thickness of the first oxide layer 12 can be greater than the thickness of the second gate oxide portion 15. Of course, in some possible embodiments, the thickness of the first oxide layer 12 can also be less than the thickness of the second gate oxide portion 15, and the specific thicknesses of the first oxide layer 12 and the second gate oxide portion 15 can depend on the different voltage requirements corresponding to the first region 111 and the second region 112.

[0054] In this embodiment, an unexpected effect is that by directly forming a first gate material layer 13 on the first oxide layer 12 grown on the surface of the substrate 11, and then removing the first sacrificial oxide portion 121 located on the first region 111 using a dry etching process, a second gate oxide portion 15 with different thicknesses is formed on the surface of the first region 111. Since the first sacrificial oxide portion 121 is removed using a dry etching process, the photoresist detachment problem caused by wet etching in related technologies can be reduced. Furthermore, during the dry etching process, the first gate material portion 132 located on the second region 112 in the pre-formed first gate material layer 13 is cleverly used as a mask layer, eliminating the need to introduce a hard mask material. This not only simplifies the process steps but also avoids the impact of removing the hard mask material on the fabricated double-gate oxide layer, thereby improving the quality of the double-gate oxide layer and ensuring the performance and yield of the semiconductor structure.

[0055] In some embodiments, after forming a second gate oxide portion on the surface of the first region, the method for fabricating a semiconductor structure further includes: depositing a second gate material layer on the surface of the second gate oxide portion and the protective oxide portion; wherein the second gate material layer includes a second gate material portion located on the first region and a second sacrificial gate material portion located on the second region; using the protective oxide portion as a planarization stop layer, performing a planarization process on the second gate material layer to make the first gate material portion and the second gate material portion flush with the second oxide layer.

[0056] In some embodiments, such as Figure 7 As shown, by means of Figure 6 A gate material is deposited on the surface of the structure shown to form a second gate material layer 16. It can be understood that the second gate material layer 16 may include a second gate material portion 161 located on the first region 111 and a second sacrificial gate material portion 162 located on the second region 112, wherein the second gate material portion 161 is located on the surface of the second gate oxide portion 15.

[0057] In some embodiments, the first gate material layer 13 may use the same gate material as the second gate material layer 16, such as both being polysilicon, which is beneficial for simplifying subsequent processes.

[0058] Next, a planarization process, such as CMP (chemical mechanical polishing), can be performed on the second gate material layer 16 to remove the portion protruding from the first gate material portion 132, resulting in a planarized gate layer. Specifically, the gate layer may include the first gate material portion 132 and the second gate material portion 161.

[0059] In some embodiments, the protective oxide portion 142 can serve as a planarization stop layer to protect the first gate material portion 132 covered thereon during the planarization process.

[0060] In some embodiments, the step of planarizing the second gate material layer using the protective oxide portion as a planarization stop layer includes: grinding the second gate material layer to be flush with the planarization stop layer based on a first chemical mechanical polishing process; wherein the second sacrificial gate material portion is removed; and grinding the second gate material portion to be flush with the first gate material portion based on a second chemical mechanical polishing process; wherein the planarization stop layer is removed.

[0061] In some embodiments, reference Figure 7 , Figure 8 and Figure 9 The planarization process for the second gate material layer 16 may include two CMP processes.

[0062] Specifically, such as Figure 7 and Figure 8 As shown, the portion above the surface of the second oxide layer protective oxide portion 142 can be ground using a first CMP process and stopped on the planarization stop layer, making the second gate material layer 16 flush with the height of the planarization stop layer. After the first CMP process, the second sacrificial gate material portion 162 is removed, and the second gate material portion 161 can have a portion above the first gate material portion 132. This portion is located on the first region 111 and on the side of the planarization stop layer, and can serve as a buffer portion 1611 in the subsequent second CMP process. It can be understood that after the first CMP process, in addition to the buffer portion 1611, the second gate material portion 161 also has a remaining portion between the surface of the first region 111 and the buffer portion 1611.

[0063] Next, a second CMP process is performed on the planarization stop layer and buffer portion to make the second gate material portion 161 flush with the first gate material portion 132, resulting in the following... Figure 9The structure is shown. During the second CMP process, by controlling the CMP selectivity, the buffer portion 1611 located on the first region 111 and on the side of the planarization stop layer can protect the remaining portion of the second gate material between the surface of the first region 111 and the buffer portion 1611, thus improving the planarization effect. This remaining portion of the second gate material can serve as the gate precursor 1612 on the first region 111 for subsequent gate fabrication.

[0064] In some embodiments, the width of the buffer portion 1611 falls within the range of 400 Å to 600 Å. Controlling the width of the buffer portion 1611 within this range results in better planarization after two CMP processes.

[0065] In some embodiments, such as Figure 10 As shown, subsequent etching processes can be performed to complete the gate fabrication at each location, such as forming a first gate structure 17 on the first region 111 and a second gate structure 18 on the second region 112. It can be understood that the gate oxide layer thicknesses of the first gate structure 17 and the second gate structure 18 are different, and therefore they have different threshold voltages.

[0066] In some embodiments, since the first gate material portion 132 located on the second region is formed in advance during the preparation of the dual gate oxide layer, only the first region 111 needs to be fabricated during the subsequent gate material fabrication, thus simplifying the process.

[0067] In some embodiments, the second region 112 can be a high-voltage region, such as an input / output (I / O) region, distinguished according to the operating voltage requirement. The first region 111 can be a low-voltage region. Based on the relatively high operating voltage requirement of the second region 112, the thickness of the first gate oxide portion 122 is greater than the thickness of the second gate oxide portion 15.

[0068] One embodiment of this application provides a semiconductor structure, which is prepared using the semiconductor structure preparation method described in any of the foregoing embodiments.

[0069] One embodiment of this application provides a semiconductor device, the semiconductor device comprising the semiconductor structure as described in any of the foregoing embodiments.

[0070] It is understood that the specific examples in this document are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of the invention.

[0071] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0072] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0073] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0074] The above description is merely a specific embodiment of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; The substrate includes a substrate and a first oxide layer formed on the surface of the substrate; wherein the substrate includes a first region and a second region; the first oxide layer includes a first sacrificial oxide portion located on the first region and a first gate oxide portion located on the second region; A first gate material layer is formed on the first oxide layer; wherein the first gate material layer includes a first sacrificial gate material portion located on a first region and a first gate material portion located on a second region; A second oxide layer is formed on the first gate material layer; wherein the second oxide layer includes a second sacrificial oxide portion located on a first region and a protective oxide portion located on a second region; Based on the dry etching process, the second sacrificial oxide portion, the first sacrificial gate material portion, and the first sacrificial oxide portion are removed; A second gate oxide portion is formed on the surface of the first region; wherein the thickness of the second gate oxide portion is different from the thickness of the first gate oxide portion; A second gate material layer is deposited on the surfaces of the second gate oxide portion and the protective oxide portion; wherein, the second gate material layer includes a second gate material portion located on a first region and a second sacrificial gate material portion located on a second region; The second gate material layer is subjected to two chemical mechanical polishing processes to make the second gate material portion flush with the first gate material portion; wherein, the protective oxide portion is used to protect the first gate material portion.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of using the protective oxide layer as a planarization stop layer to planarize the second gate material layer includes: Using the protective oxide portion as a planarization stop layer, the second gate material layer is ground to be flush with the planarization stop layer based on a first chemical mechanical polishing process; wherein, the second sacrificial gate material portion is removed; Based on a second chemical mechanical polishing process, the second gate material portion is ground until it is flush with the first gate material portion; wherein, the planarization stop layer is removed.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, After the second gate material layer is polished to be flush with the planarization stop layer using the first chemical mechanical polishing process, a buffer portion is formed on the side of the planarization stop layer; wherein, during the second chemical mechanical polishing process, the buffer portion protects the remaining portion of the second gate material between the surface of the first region and the buffer portion.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The thickness of the first gate oxide portion is greater than the thickness of the second gate oxide portion.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The first region is a low-pressure region, and the second region is a high-pressure region.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first gate material layer and the second gate material layer have the same gate material.

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