Semiconductor device and method of manufacturing the same

Abstract

The semiconductor device includes: a substrate including a first region and a second region surrounding the first region; the epitaxial layer is arranged in the first region and the second region, and the epitaxial layer has a first conduction type; a buried layer disposed under the epitaxial layer, in which the buried layer has a second conductivity type different from the first conductivity type; a first high-concentration impurity region disposed on the epitaxial layer in the first region, in which the first high-concentration impurity region overlaps a top surface of the epitaxial layer and has a first conductivity type; a second high-concentration impurity region disposed on the epitaxial layer in the first region, in which the second high-concentration impurity region overlaps a top surface of the epitaxial layer and has a second conductivity type; and a device isolation film disposed on the epitaxial layer between the first high-concentration impurity region and the second high-concentration impurity region.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0165841, filed with the Korean Intellectual Property Office on November 24, 2023, the content of which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device including a high - voltage power diode and a method of manufacturing the semiconductor device. Background art

[0004] Power diodes are power components widely used in high - voltage applications of direct current (DC) / alternating current (AC) converters. These high - voltage power diodes may require a high breakdown voltage and a low on - resistance.

[0005] High - voltage power diodes can be manufactured together with various other components through a bipolar complementary metal - oxide - semiconductor (CMOS) double - diffused metal - oxide - semiconductor (DMOS) (BCD) process. The BCD process involves implementing bipolar transistors, CMOS transistors, and DMOS transistors on a single semiconductor substrate and can be used for the production of various power components. Summary of the invention

[0006] Embodiments of the present disclosure provide a semiconductor device having an improved breakdown voltage.

[0007] Embodiments of the present disclosure also provide a method of manufacturing a semiconductor device having an improved breakdown voltage.

[0008] According to an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a substrate including a first region and a second region surrounding the first region; an epitaxial layer disposed in the first region and the second region, wherein the epitaxial layer has a first conductivity type; a buried layer disposed below the epitaxial layer, wherein the buried layer has a second conductivity type different from the first conductivity type; a first high-concentration impurity region disposed on the epitaxial layer in the first region, wherein the first high-concentration impurity region overlaps with the top surface of the epitaxial layer and has the first conductivity type; a second high-concentration impurity region disposed on the epitaxial layer in the first region, wherein the second high-concentration impurity region overlaps with the top surface of the epitaxial layer and has the second conductivity type; a device isolation film disposed on the epitaxial layer between the first high-concentration impurity region and the second high-concentration impurity region, wherein the device isolation film is disposed adjacent to the second high-concentration impurity region; a drift region disposed on the epitaxial layer below the device isolation film and the second high-concentration impurity region, wherein the drift region has the second conductivity type; a high-voltage well disposed on the epitaxial layer below the drift region, wherein the high-voltage well has the second conductivity type; a third high-concentration impurity region disposed on the epitaxial layer in the second region, wherein the third high-concentration impurity region overlaps with the top surface of the epitaxial layer and has the second conductivity type; and an isolation well located within the epitaxial layer in the second region, wherein the isolation well connects the buried layer and the third high-concentration impurity region and has the second conductivity type. The impurity concentration of the high-voltage well is lower than that of the isolation well.

[0009] According to an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a substrate; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type; a buried layer disposed below the epitaxial layer, wherein the buried layer has a second conductivity type different from the first conductivity type; a first high-concentration impurity region disposed on the epitaxial layer, wherein the first high-concentration impurity region overlaps with the top surface of the epitaxial layer and has the first conductivity type; a second high-concentration impurity region disposed on the epitaxial layer, wherein the second high-concentration impurity region overlaps with the top surface of the epitaxial layer and has the second conductivity type; a device isolation film disposed on the epitaxial layer between the first high-concentration impurity region and the second high-concentration impurity region, wherein the device isolation film is adjacent to the second high-concentration impurity region; a drift region disposed on the epitaxial layer below the device isolation film and the second high-concentration impurity region, wherein the drift region has the second conductivity type; and a high-voltage well disposed on the epitaxial layer below the drift region, wherein the high-voltage well has the second conductivity type. The buried layer includes a base portion located below the first high-concentration impurity region and an extending portion extending from the base portion and located below the high-voltage well, and the impurity concentration of the extending portion is lower than that of the base portion.

[0010] According to an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a substrate including a first region and a second region surrounding the first region; a P-type epitaxial layer disposed in the first region and the second region; an N-type buried layer disposed under the P-type epitaxial layer; a P-type high-concentration impurity region disposed on the P-type epitaxial layer in the first region, wherein the P-type high-concentration impurity region overlaps with the top surface of the P-type epitaxial layer; a first N-type high-concentration impurity region disposed on the P-type epitaxial layer in the first region, wherein the first N-type high-concentration impurity region overlaps with the top surface of the P-type epitaxial layer; a device isolation film disposed on the P-type epitaxial layer between the P-type high-concentration impurity region and the first N-type high-concentration impurity region, wherein the device isolation film is adjacent to the first N-type high-concentration impurity region; a gate electrode disposed on the P-type epitaxial layer between the P-type high-concentration impurity region and the first N-type high-concentration impurity region, wherein the gate electrode is adjacent to the P-type high-concentration impurity region; an N-type drift region disposed on the P-type epitaxial layer under the device isolation film and the first N-type high-concentration impurity region; an N-type high-voltage well disposed on the P

[0011] type epitaxial layer under the N-type drift region; a second N-type high-concentration impurity region disposed on the P-type epitaxial layer in the second region, wherein the second N-type high-concentration impurity region is located between the top surfaces of the P-type epitaxial layer; and an N-type isolation well disposed in the P-type epitaxial layer on the second region, wherein the N-type isolation well connects the N-type buried layer and the second N-type high-concentration impurity region. The impurity concentration of the N-type high-voltage well is lower than that of the N-type isolation well. The N-type buried layer includes a base portion located under the P-type high-concentration impurity region and an extension portion extending from the base portion and located under the high-voltage well, and the impurity concentration of the extension portion is lower than that of the base portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 Shows the layout of a semiconductor device according to some embodiments of the present disclosure.

[0013] Figure 2 Shows Figure 1 the first region and the second region.

[0014] Figure 3 Is a cross-sectional view taken along lines A-A and B-B of Figure 2 the.

[0015] Figure 4 Is a graph of the breakdown voltage of a semiconductor device according to some embodiments of the present disclosure.

[0016] Figure 5 Is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0017] Figure 6A cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0018] Figure 7 Shows the layout of a semiconductor device according to some embodiments of the present disclosure.

[0019] Figure 8 Shows the layout of a semiconductor device according to some embodiments of the present disclosure.

[0020] Figure 9 Is a graph of the breakdown voltage of a semiconductor device according to some embodiments of the present disclosure.

[0021] Figures 10 to 18 Is a cross-sectional view showing an intermediate stage of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0022] Figure 19 And Figure 20 Are cross-sectional views showing a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed Description

[0023] Hereinafter, reference will be made to Figures 1 to 9 Describe a semiconductor device according to some embodiments of the present disclosure.

[0024] In some embodiments, a semiconductor device is manufactured together with various other components by a bipolar complementary metal oxide semiconductor double-diffused metal oxide semiconductor (BCD) process. For example, components manufactured together on a single semiconductor substrate by the BCD process include, but are not limited to, nLDMOS, pLDMOS, isolated CMOS, BiCMOS, CDMOS, nDMOS, pDMOS, vertical NPN, lateral PNP, Schottky diodes, etc.

[0025] Figure 1 Shows the layout of a semiconductor device according to some embodiments of the present disclosure. Figure 2 Shows Figure 1 The first region and the second region of. Figure 3 Is along Figure 2 Cross-sectional views taken along lines A-A and B-B of.

[0026] Refer to Figures 1 to 3, in some embodiments, the semiconductor device includes a substrate 100, a buried layer 110, an epitaxial layer 120, a first high-voltage well 130, a second high-voltage well 140, isolation wells 142 and 144, a drift region 150, a first well region 160, a second well region 170, a first high-concentration impurity region 180, a second high-concentration impurity region 190, a third high-concentration impurity region 195, a device isolation film 200, a gate dielectric film 310, a gate electrode 320, a first electrode 410, a second electrode 420, and a third electrode 430.

[0027] The substrate 100 is a semiconductor substrate such as a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a silicon (Si) substrate, or may include other materials such as silicon germanium (SiGe), silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compounds, indium phosphide, gallium antimonide, or gallium arsenide. In some embodiments, the substrate 100 includes an epitaxial layer formed on a base substrate. For convenience, the substrate 100 will be described hereinafter as being a Si substrate.

[0028] The substrate 100 includes a first region I and a second region II. The first region I is a region where power components such as high-voltage power diodes are formed, and includes a drift region 150, a first high-concentration impurity region 180, and a second high-concentration impurity region 190. The first region I is shown to have a rectangular shape in a plan view, but the embodiments of the present disclosure are not necessarily limited thereto. For example, the first region I may have various other shapes. The second region II surrounds the first region I. For example, the second region II surrounds the first region I in a plane such as the XY plane defined by a first direction X and a second direction Y. The second region II is an isolation region that electrically isolates the first region I from other regions of the substrate 100.

[0029] In some embodiments, the substrate 100 has a first conductivity type. For convenience, the first conductivity type will be described hereinafter as being P-type. For example, the substrate 100 is a P-type substrate ("P-SUB") containing P-type impurities such as boron (B), indium (In), gallium (Ga), or aluminum (Al).

[0030] The buried layer 110 is formed on the substrate 100. The buried layer 110 has a second conductivity type different from the first conductivity type. For example, the buried layer 110 is formed by doping an N-type impurity such as phosphorus (P), antimony (Sb), or arsenic (As) into the upper part of the substrate 100. For example, the buried layer 110 is an N-type buried layer ("NBL"). The buried layer 110 is a high-concentration impurity region doped with a relatively high concentration of impurities. For example, the concentration of the N-type impurity such as phosphorus (P) doped into the buried layer 110 may be about 10E19 cm -3 to about 10E20 cm -3 .

[0031] The buried layer 110 is formed to span across the first region I and the second region II. In some embodiments, the buried layer 110 is formed over the entire first region I and a part of the second region II.

[0032] The epitaxial layer 120 is formed on the substrate 100 and / or the buried layer 110. The epitaxial layer 120 is formed to span across the first region I and the second region II. The epitaxial layer 120 is grown from the substrate 100 and / or the buried layer 110 by an epitaxial growth method. The epitaxial layer 120 has a first conductivity type. For example, the epitaxial layer 120 is a P-type epitaxial layer (“P-EPI”) containing P-type impurities such as B, In, Ga, or Al.

[0033] The first high-voltage well 130 is formed within the epitaxial layer 120 over the first region I. The first high-voltage well 130 is adjacent to the top surface of the epitaxial layer 120. The first high-voltage well 130 has a first conductivity type. For example, the first high-voltage well 130 is formed by doping P-type impurities such as B, In, Ga, or Al into the upper portion of the epitaxial layer 120. For example, the first high-voltage well 130 is a high-voltage P-type well (“HVPW”).

[0034] In some embodiments, the first high-voltage well 130 is not formed within the epitaxial layer 120 in the second region II. In some embodiments, the first high-voltage well 130 is omitted.

[0035] The drift region 150 is formed within the epitaxial layer 120 over the first region I. The drift region 150 has a second conductivity type. For example, the drift region 150 is formed by doping N-type impurities such as P, Sb, or As into a part of the first high-voltage well 130. For example, the drift region 150 is an N-type drift region (“NDRIFT”). The drift region 150 is a low-concentration impurity region doped with a relatively low concentration of impurities. For example, the concentration of N-type impurities such as P doped into the drift region 150 is about 10E16 cm -3 to about 10E18 cm -3 .

[0036] The first well region 160 is formed within the epitaxial layer 120 over the first region I. The first well region 160 is adjacent to the top surface of the epitaxial layer 120. The first well region 160 is spaced apart from the drift region 150. For example, a part of the first high-voltage well 130 is interposed between the drift region 150 and the first well region 160. The first well region 160 has a first conductivity type. For example, the first well region 160 is formed by doping P-type impurities such as B, In, Ga, or Al into the upper portion of the epitaxial layer 120. The first well region 160 is a P-type well (“PWELL”). The concentration of P-type impurities such as B doped into the first well region 160 is about 10E17 cm -3to about 10E18 cm -3 。

[0037] The second well region 170 is formed within the epitaxial layer 120 in the second region II. The second well region 170 is adjacent to the top surface of the epitaxial layer 120. The second well region 170 has a second conductivity type. For example, the second well region 170 is formed by doping an N-type impurity such as P, Sb, or As into the upper portion of the epitaxial layer 120. The second well region 170 is an N-type well (“NWELL”). The concentration of the N-type impurity such as P doped into the second well region 170 is about 10E17 cm -3 to about 10E18 cm -3 。

[0038] In some embodiments, at least a portion of the second well region 170 overlaps with the buried layer 110. Here, the expression “overlaps” means that at least a portion of the second well region 170 overlaps with the buried layer 110 in a third direction Z that intersects the top surface of the substrate 100 or intersects the first direction X and the second direction Y.

[0039] The first high-concentration impurity region 180 is formed within the first well region 160. The first high-concentration impurity region 180 overlaps with the top surface of the epitaxial layer 120. The first high-concentration impurity region 180 has a first conductivity type. For example, the first high-concentration impurity region 180 is formed by doping a P-type impurity such as B, In, Ga, or Al into the upper portion of the first well region 160.

[0040] The first high-concentration impurity region 180 is a P-type high-concentration impurity region (“P+”). The impurity concentration of the first high-concentration impurity region 180 is higher than the impurity concentration of the first well region 160. For example, the concentration of the P-type impurity (e.g., B) doped into the first high-concentration impurity region 180 is about 10E19 cm -3 to about 10E20 cm -3 。

[0041] The first electrode 410 is formed on the first high-concentration impurity region 180. The first electrode 410 is electrically connected to the first high-concentration impurity region 180. In some embodiments, the first electrode 410 serves as the anode 520 (“Anode”) of a high-voltage power diode. For example, a ground voltage is applied to the first electrode 410.

[0042] The second highest-concentration impurity region 190 is formed within the drift region 150. The second highest-concentration impurity region 190 overlaps with the top surface of the epitaxial layer 120. The second highest-concentration impurity region 190 has a second conductivity type. For example, the second highest-concentration impurity region 190 is formed by doping an N-type impurity such as P, Sb, or As into the upper portion of the epitaxial layer 120. The second highest-concentration impurity region 190 is an N-type high-concentration impurity region ("N+"). The impurity concentration of the second highest-concentration impurity region 190 is higher than the impurity concentration of the drift region 150. For example, the concentration of the N-type impurity such as P doped into the second highest-concentration impurity region 190 is about 10E19 cm -3 to about 10E20 cm -3 .

[0043] The second electrode 420 is formed on the second highest-concentration impurity region 190. The second electrode 420 is electrically connected to the second highest-concentration impurity region 190. In some embodiments, the second electrode 420 serves as the cathode 510 ("Cathode") of the high-voltage power diode.

[0044] In some embodiments, the first highest-concentration impurity region 180 and the second highest-concentration impurity region 190 extend in parallel in the second direction Y. For example, as Figure 2 shown, the first highest-concentration impurity region 180 and the second highest-concentration impurity region 190 are arranged along the first direction X and extend longitudinally in the second direction Y.

[0045] The third highest-concentration impurity region 195 is formed within the second well region 170. The third highest-concentration impurity region 195 is adjacent to the top surface of the second well region 170 and is located between the top surfaces of the epitaxial layer 120. The third highest-concentration impurity region 195 has a second conductivity type. For example, the third highest-concentration impurity region 195 is formed by doping an N-type impurity such as P, Sb, or As into the upper portion of the second well region 170. The third highest-concentration impurity region 195 is an N-type high-concentration impurity region ("N+"). The impurity concentration of the third highest-concentration impurity region 195 is higher than the impurity concentration of the second well region 170. For example, the concentration of the N-type impurity such as P doped into the third highest-concentration impurity region 195 is about 10E19 cm -3 to about 10E20 cm -3 .

[0046] In some embodiments, the third highest-concentration impurity region 195 is formed at the same level as the second highest-concentration impurity region 190. In this specification, the expression "formed at the same level" means that the third highest-concentration impurity region 195 and the second highest-concentration impurity region 190 are created by the same manufacturing process. For example, the impurity concentration of the third highest-concentration impurity region 195 is the same as the impurity concentration of the second highest-concentration impurity region 190.

[0047] The third electrode 430 is formed on the third high-concentration impurity region 195. The third electrode 430 is electrically connected to the third high-concentration impurity region 195. In some embodiments, the third electrode 430 is connected to the first electrode 410. For example, the same voltage can be applied to the first electrode 410 and the third electrode 430. For example, a ground voltage can be applied to the third electrode 430.

[0048] The device isolation film 200 is formed on the epitaxial layer 120 in the first region I and the second region II. The device isolation film 200 is adjacent to the top surface of the epitaxial layer 120 in the second region II. The device isolation film 200 can be formed by a process such as shallow trench isolation (STI) or local oxidation of silicon (LOCOS).

[0049] The device isolation film 200 in the first region I is interposed between the first high-concentration impurity region 180 and the second high-concentration impurity region 190. In addition, the device isolation film 200 in the first region I is formed above a part of the first high-voltage well 130 and the drift region 150. In some embodiments, the device isolation film 200 in the first region I is formed to span a part of both the first high-voltage well 130 and the drift region 150.

[0050] The first high-concentration impurity region 180 is spaced apart from the device isolation film 200. The first high-concentration impurity region 180 is spaced farther from the device isolation film 200 than the first well region 160. For example, a part of the first well region 160 is interposed between the device isolation film 200 and the first high-concentration impurity region 180. In some embodiments, a part of the first high-voltage well 130 is interposed between the device isolation film 200 and the first well region 160.

[0051] The second high-concentration impurity region 190 is adjacent to the device isolation film 200. For example, the second high-concentration impurity region 190 is formed by doping an N-type impurity such as P, Sb, or As into the upper part of the drift region 150 exposed through the device isolation film 200. The drift region 150 is formed below the device isolation film 200 and the second high-concentration impurity region 190.

[0052] The device isolation film 200 in the second region II is formed on both sides of the third high-concentration impurity region 195. For example, the third high-concentration impurity region 195 is formed by doping an N-type impurity such as P, Sb, or As into the upper part of the second well region 170 exposed through the device isolation film 200. The second well region 170 is formed below the device isolation film 200 and the third high-concentration impurity region 195.

[0053] The second high-voltage well 140 is formed within the first high-voltage well 130 in the first region I. The second high-voltage well 140 is formed below the drift region 150. The second high-voltage well 140 is adjacent to the drift region 150. The second high-voltage well 140 is spaced apart from the buried layer 110. The second high-voltage well 140 has a second conductivity type. For example, the second high-voltage well 140 is formed by doping an N-type impurity such as P, Sb, or As into other portions of the first high-voltage well 130 placed below the drift region 150. For example, the second high-voltage well 140 is a high-voltage N-type well ("HVNW"). In some embodiments, a portion of the first high-voltage well 130 is interposed between the buried layer 110 and the second high-voltage well 140.

[0054] At least a portion of the second high-voltage well 140 overlaps with the second high-concentration impurity region 190 in the third direction Z. In some embodiments, the second high-voltage well 140 protrudes beyond the second high-concentration impurity region 190 toward the first high-concentration impurity region 180 or the first well region 160. For example, other portions of the second high-voltage well 140 overlap with the device isolation film 200 in the third direction Z. In some embodiments, the drift region 150 protrudes beyond the second high-voltage well 140 toward the first high-concentration impurity region 180 or the first well region 160.

[0055] Isolation wells 142 and 144 are formed in the second region II. The isolation wells 142 and 144 are formed on the buried layer 110 and below the second well region 170. The isolation wells 142 and 144 connect the buried layer 110 and the second well region 170. The isolation wells 142 and 144 have a second conductivity type. For example, the isolation wells 142 and 144 are formed by doping an N-type impurity such as P, Sb, or A into the portion of the epitaxial layer 120 on the buried layer 110 in the second region II. For example, the isolation wells 142 and 144 are high-voltage N-type wells ("HVNW", such as Figure 3 "HVNW1" and "HVNW2" in the example).

[0056] The isolation wells 142 and 144 surround the first region I in a plan view. For example, the isolation wells 142 and 144 surround the first region I in a plane such as the XY plane defined by the first direction X and the second direction Y. The buried layer 110 and the isolation wells 142 and 144 electrically isolate the first region I from other regions of the substrate 100.

[0057] In some embodiments, isolation wells 142 and 144 include a first sub-isolation well 142 and a second sub-isolation well 144 that are sequentially formed on the buried layer 110. The first sub-isolation well 142 connects the buried layer 110 and the second sub-isolation well 144, and the second sub-isolation well 144 connects the first sub-isolation well 142 and the second well region 170. The first sub-isolation well 142 and the second sub-isolation well 144 have a second conductivity type. For example, the first sub-isolation well 142 is a high-voltage N-type well ("HVNW"), and the second sub-isolation well 144 is a high-voltage N-type well ("HVNW") having a projection range (R p ) smaller than that of the first sub-isolation well 142. In some embodiments, the second high-voltage well 140 is formed at the same level as the second sub-isolation well 144.

[0058] The second high-voltage well 140 is a low-doped impurity region. The impurity concentration of the second high-voltage well 140 is lower than the impurity concentrations of the isolation wells 142 and 144. In some embodiments, the impurity concentration of the second high-voltage well 140 is lower than the impurity concentration of the second sub-isolation well 144.

[0059] The gate dielectric film 310 and the gate electrode 320 are formed on the epitaxial layer 120 in the first region I. The gate dielectric film 310 is interposed between the epitaxial layer 120 and the gate electrode 320. The gate electrode 320 is spaced apart from the epitaxial layer 120 by the gate dielectric film 310.

[0060] The gate electrode 320 is formed on the first high-voltage well 130 between the first high-concentration impurity region 180 and the second high-concentration impurity region 190. In some embodiments, the gate electrode 320 is formed to span a portion of the first high-voltage well 130 and the device isolation film 200. For example, the gate electrode 320 is formed to span a portion of the first well region 160, the first high-voltage well 130, and the device isolation film 200.

[0061] The first high-concentration impurity region 180 is adjacent to the gate electrode 320. For example, the first high-concentration impurity region 180 is formed by doping a P-type impurity such as B, In, Ga, or Al into the upper portion of the first well region 160 exposed by the gate electrode 320. The portion of the first well region 160 located between the device isolation film 200 and the first high-concentration impurity region 180 is formed below the gate electrode 320. In some embodiments, the portion of the first high-voltage well 130 interposed between the device isolation film 200 and the first well region 160 is formed below the gate electrode 320.

[0062] The second high-concentration impurity region 190 is spaced apart from the gate electrode 320. For example, a portion of the device isolation film 200 is formed below the gate electrode 320, and other portions of the device isolation film 200 are interposed between the second high-concentration impurity region 190 and the gate electrode 320.

[0063] In some embodiments, the gate electrode 320 is electrically connected to the first electrode 410. For example, the same voltage may be applied to the first electrode 410 and the gate electrode 320. For example, a ground voltage may be applied to the gate electrode 320.

[0064] The gate dielectric film 310 includes at least one of, for example, silicon oxide, silicon nitride, silicon carbide, a dielectric material having a dielectric constant greater than that of silicon oxide, and combinations thereof, but embodiments of the present disclosure are not necessarily limited thereto. For example, the gate dielectric film 310 includes a silicon oxide film.

[0065] The gate electrode 320 includes a conductive material such as polysilicon (polycrystalline Si), amorphous silicon (a-Si), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum (Ta), cobalt (Co), ruthenium (Ru), Al, tungsten (W), and combinations thereof, but embodiments of the present disclosure are not necessarily limited thereto. For example, the gate electrode 320 includes a polysilicon film.

[0066] As described above, a semiconductor device according to some embodiments of the present disclosure includes a second high-voltage well 140 formed under the drift region 150. The second high-voltage well 140 is, for example, a high-voltage N-type well ("HVNW") formed by a BCD process. The second high-voltage well 140 enhances the reduced surface field (RESURF) effect by expanding the depletion region in a vertical direction such as a third direction Z. Accordingly, a high-voltage power diode having an improved breakdown voltage can be provided.

[0067] In addition, since the second high-voltage well 140 is positioned close to the buried layer 110, a punch-through phenomenon between the depletion region caused by the second high-voltage well 140 and the buried layer 110 may become a problem. However, as disclosed above, since the second high-voltage well 140 is a relatively low doped impurity region compared to the isolation wells 142 and 144, an excessive expansion of the depletion region caused by the second high-voltage well 140 can be prevented. Accordingly, a high-voltage power diode having an improved breakdown voltage can be provided without a leakage current problem.

[0068] Figure 4 is a graph of the breakdown voltage of a semiconductor device according to some embodiments of the present disclosure. For example, Figure 4 is a graph comparing the turn-off state current measurements from Example 1 and the Comparative Example. Example 1 uses Figures 1 to 3 the semiconductor device of. The Comparative Example uses a similar semiconductor device that does not include the second high-voltage well 140.

[0069] Referring to Figure 4 , compared with the semiconductor device according to the comparative example having a breakdown voltage of about 123V, the semiconductor device according to Example 1 has a significantly improved breakdown voltage of about 143V. This confirms that the second high-voltage well 140 of Figure 3 can be used to improve the breakdown voltage of the high-voltage power diode.

[0070] Figure 5 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. For convenience, the description of the components already referred to above Figures 1 to 4 may be summarized or omitted.

[0071] Referring to Figure 1 , Figure 2 and Figure 5 , in the embodiment, the buried layer 110 includes a substrate portion 112 and an extension portion 114.

[0072] The substrate portion 112 is formed in the first region I and the second region II. The extension portion 114 extends from the substrate portion 112 in the first region. The extension portion 114 is formed under the second high-voltage well 140. At least a part of the extension portion 114 overlaps with the second high-voltage well 140 in the third direction Z. In some embodiments, at least a part of the extension portion 114 overlaps with the second high-concentration impurity region 190 in the third direction Z.

[0073] The impurity concentration of the extension portion 114 is lower than that of the substrate portion 112. The extension portion 114 can more effectively prevent the punch-through phenomenon between the buried layer 110 and the depletion region caused by the second high-voltage well 140. In some embodiments, the impurity concentration of the extension portion 114 decreases as the distance from the substrate portion 112 increases. For example, the extension portion 114 is an impurity region formed by the diffusion of impurity atoms from the substrate portion 112.

[0074] In some embodiments, the thickness of the extension portion 114 decreases as the distance from the substrate portion 112 increases. For example, the top surface of the extension portion 114 becomes lower as it moves away from the substrate portion 112, and the bottom surface of the extension portion 114 becomes higher as it moves away from the substrate portion 112.

[0075] Figure 6 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. For convenience, the description of the components already referred to above Figures 1 to 5 may be summarized or omitted.

[0076] Referring to Figure 1 , Figure 2 and Figure 6, in an embodiment, the second high-voltage well 140 includes a first portion 140a, a second portion 140b, and a third portion 141.

[0077] The first portion 140a and the second portion 140b are arranged in a direction of a first direction X, such as arranging a first high-concentration impurity region 180 and a second high-concentration impurity region 190. The third portion 141 is interposed between the first portion 140a and the second portion 140b. For example, the first portion 140a, the third portion 141, and the second portion 140b are sequentially arranged in the first direction X.

[0078] In some embodiments, the first portion 140a overlaps with the device isolation film 200 in a third direction Z. In some embodiments, the second portion 140b overlaps with the second high-concentration impurity region 190 in the third direction Z.

[0079] The depth at which the third portion 141 is formed is less than the depths at which the first portion 140a and the second portion 140b are formed. For example, the bottom surface of the third portion 141 is higher than the bottom surfaces of the first portion 140a and the second portion 140b. In some embodiments, the bottom surface of the third portion 141 becomes higher as it is farther from the first portion 140a and the second portion 140b. For example, the third portion 141 is an impurity region formed by diffusion of impurity atoms from the first portion 140a and the second portion 140b.

[0080] In some embodiments, the impurity concentration of the third portion 141 is lower than the impurity concentrations of the first portion 140a and the second portion 140b. In some embodiments, the impurity concentration of the third portion 141 decreases as the distance from the first portion 140a and the second portion 140b increases, but the embodiments of the present disclosure are not necessarily limited thereto. In some embodiments, the impurity concentrations of the first portion 140a, the second portion 140b, and the third portion 141 are substantially the same.

[0081] Figure 7 Shows the layout of a semiconductor device according to some embodiments of the present disclosure. Figure 8 Shows the layout of a semiconductor device according to some embodiments of the present disclosure. For convenience, the descriptions of the components described above may be summarized or omitted with reference to Figures 1 to 6 the descriptions.

[0082] With reference to Figure 7 and Figure 8 , in some embodiments, the second high-concentration impurity region 190 surrounds the first high-concentration impurity region 180.

[0083] For example, in a plan view, a plurality of first high-concentration impurity regions 180 are arranged as a plurality of isolated regions, and a second high-concentration impurity region 190 surrounds the first high-concentration impurity regions 180.

[0084] In an embodiment, as Figure 7 shown, in a plan view, the first high-concentration impurity regions 180 are arranged in a honeycomb pattern, and the second high-concentration impurity region 190 has a hexagon surrounding the first high-concentration impurity regions 180.

[0085] In an embodiment, as Figure 8 shown, in a plan view, the first high-concentration impurity regions 180 are arranged in a lattice pattern, and the second high-concentration impurity region 190 has a rectangle surrounding the first high-concentration impurity regions 180.

[0086] As shown above, the second high-voltage well 140 overlaps with the second high-concentration impurity region 190 in the third direction Z. Thus, in a plan view, the second high-voltage well 140 also surrounds the first high-concentration impurity regions 180. The second high-voltage well 140 can enhance the RESURF effect by expanding the depletion region in two horizontal directions (such as in the XY plane) and in the vertical direction (such as the third direction Z). Thus, a high-voltage power diode having a further improved breakdown voltage can be provided.

[0087] Figure 9 is a graph of the breakdown voltage of a semiconductor device according to some embodiments of the present disclosure. For example, Figure 9 is a graph comparing the turn-off state current measurements from Example 1, the comparative example, and Example 2. Example 2 uses Figure 7 the semiconductor device of.

[0088] Referring to Figure 9 , the semiconductor device according to Example 2 has an improved breakdown voltage of approximately 149V. This confirms that Figure 7 the use of the second high-voltage well 140 of can further enhance the breakdown voltage of the high-voltage power diode.

[0089] Hereinafter, a method of manufacturing a semiconductor device according to some embodiments of the present disclosure will be described with reference to Figures 10 to 20 .

[0090] Figures 10 to 18 is a cross-sectional view showing an intermediate stage of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. For convenience, the description of the components described above with reference to Figures 1 to 9 may be summarized or omitted.

[0091] Referring to Figure 10 , in an embodiment, a buried layer 110 is formed on a substrate 100.

[0092] For example, the substrate 100 is a P-type substrate (“P-SUB”). Thereafter, an ion implantation process of doping N-type impurities such as P is performed on the top surface of the substrate 100. As a result, an N-type buried layer (“NBL”) is formed as the buried layer 110.

[0093] Referring to Figure 11 , in an embodiment, an epitaxial layer 120 is formed on the substrate 100 and the buried layer 110.

[0094] The epitaxial layer 120 can be formed by a selective epitaxial growth method or a solid-phase epitaxial growth method, but the embodiments of the present disclosure are not necessarily limited thereto. A P-type epitaxial layer (“P-EPI”) is formed as the epitaxial layer 120.

[0095] Referring to Figure 12 , in an embodiment, a first high-voltage well 130, an initial high-voltage well 140p, a first initial isolation well 142p, and a second initial isolation well 144p are formed in the epitaxial layer 120.

[0096] For example, an ion implantation process of doping P-type impurities into the upper portion of the epitaxial layer 120 in the first region I is performed. As a result, a high-voltage P-type well (“HVPW”) is formed as the first high-voltage well 130.

[0097] In addition, for example, an ion implantation process of doping N-type impurities into the epitaxial layer 120 in the second region II is performed. As a result, a first initial isolation well 142p is formed on the buried layer 110 in the second region II. Thereafter, an ion implantation process of doping N-type impurities having a projection range (R p ) smaller than the projection range (R p ) of the first initial isolation well 142p into the epitaxial layer 120 in the first region I and the second region II is performed. As a result, an initial high-voltage well 140p and a second initial isolation well 144p having a depth shallower than that of the first initial isolation well 142p are formed.

[0098] In some embodiments, the initial high-voltage well 140p includes a first low-concentration impurity region 140p1 and a second low-concentration impurity region 140p2 spaced apart from the first low-concentration impurity region 140p1. For example, the first low-concentration impurity region 140p1 and the second low-concentration impurity region 140p2 are spaced apart from each other in the first direction X. The initial high-voltage well 140p can be formed by a slit-type ion implantation process of doping N-type impurities into a predetermined pattern using a photoresist, but the embodiments of the present disclosure are not necessarily limited thereto.

[0099] Referring to Figure 13 , in an embodiment, a second high-voltage well 140 and isolation wells 142 and 144 are formed in the epitaxial layer 120.

[0100] For example, Figure 12 The initial high voltage well 140p and the first initial isolation well 142p and the second initial isolation well 144p are subjected to a heat treatment process such as an annealing process. As a result, the impurity atoms doped in the initial high voltage well 140p may diffuse, thereby resulting in the formation of the second high voltage well 140. In addition, the impurity atoms doped in the first initial isolation well 142p and the second initial isolation well 144p may diffuse, thereby resulting in the formation of isolation wells 142, 144 including the first sub-isolation well 142 and the second sub-isolation well 144. The heat treatment process may be performed immediately after the initial high voltage well 140p and the first initial isolation well 142p and the second initial isolation well 144p are formed, but the embodiments of the present disclosure are not necessarily limited thereto. Those skilled in the art to which the present disclosure pertains will appreciate that the heat treatment process may also be performed during or after a subsequent stage.

[0101] Since the second high voltage well 140 is formed by the initial high voltage well 140p including the first low concentration impurity region 140p1 and the second low concentration impurity region 140p2, the impurity concentration of the second high voltage well 140 can be reduced. For example, the impurity concentration of the second high voltage well 140 is lower than that of the second sub-isolation well 144.

[0102] Reference Figure 14 In an embodiment, a drift region 150 is formed in the epitaxial layer 120 on the first region I.

[0103] For example, an ion implantation process is performed to dope low-concentration N-type impurities into the upper portion of the first high voltage well 130 on the second high voltage well 140. As a result, an N-type drift region ("NDRIFT") is formed as the drift region 150.

[0104] Reference Figure 15 In an embodiment, a device isolation film 200 is formed in the epitaxial layer 120 .

[0105] The device isolation film 200 overlaps with the top surface of the epitaxial layer 120. The device isolation film 200 in the first region I is formed on the drift region 150, and the device isolation film 200 in the first region I exposes a portion of the drift region 150. In some embodiments, the device isolation film 200 in the second region II is formed on the epitaxial layer 120 and the isolation wells 142 and 144, and the device isolation film 200 in the second region II exposes a portion of the isolation wells 142 and 144.

[0106] The device isolation film 200 is an oxide layer formed by, for example, an STI process or a LOCOS process, but the embodiments of the present disclosure are not necessarily limited thereto.

[0107] Reference Figure 16, in an embodiment, a first well region 160 is formed within a first high-voltage well 130 in a first region I, and a second well region 170 is formed within a second sub-isolation well 144 in a second region II.

[0108] For example, an ion implantation process of doping P-type impurities is performed on the upper portion of the first high-voltage well 130 isolated from the drift region 150 and the device isolation film 200. As a result, a P-type well ("PWELL") is formed as the first well region 160.

[0109] In addition, for example, an ion implantation process of doping N-type impurities into the upper portions of the isolation wells 142 and 144 is performed. As a result, an N-type well ("NWELL") is formed as the second well region 170.

[0110] Referring to Figure 17 , in an embodiment, a gate dielectric film 310 and a gate electrode 320 are sequentially formed on the epitaxial layer 120 on the first region I.

[0111] The gate dielectric film 310 and the gate electrode 320 are formed above a part of the epitaxial layer 120 and the device isolation film 200. For example, the gate dielectric film 310 and the gate electrode 320 are formed above a part of the first well region 160, the first high-voltage well 130, and the device isolation film 200.

[0112] Referring to Figure 18 , in an embodiment, a first high-concentration impurity region 180, a second high-concentration impurity region 190, and a third high-concentration impurity region 195 are formed on the epitaxial layer 120.

[0113] For example, an ion implantation process of doping high-concentration P-type impurities is performed on the first well region 160 exposed through the gate dielectric film 310 and the gate electrode 320. As a result, the first high-concentration impurity region 180 is formed.

[0114] In addition, for example, an ion implantation process of doping high-concentration N-type impurities into the upper portion of the drift region 150 exposed through the device isolation film 200 and into the upper portion of the second well region 170 is performed. As a result, the second high-concentration impurity region 190 and the third high-concentration impurity region 195 are formed.

[0115] After that, referring to Figure 3 , in an embodiment, a first electrode 410, a second electrode 420, and a third electrode 430 are formed on the epitaxial layer 120. As a result, a Figures 1 to 3 semiconductor device can be obtained.

[0116] Figure 19 and Figure 20It is a cross-sectional view showing a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. For convenience, descriptions of components already referred to above may be summarized or omitted. Figures 1 to 19 Descriptions of the components described above.

[0117] Referring to Figure 19 , in an embodiment, an initial buried layer 110p is formed on a substrate 100.

[0118] For example, an ion implantation process of doping an N-type impurity such as P into the upper part of the substrate 100 is performed. As a result, an N-type buried layer (“NBL”) is formed as the initial buried layer 110p.

[0119] The initial buried layer 110p is formed on the upper part of the first region I, but not on another upper part of the first region I. For example, the initial buried layer 110p may expose a part of the top surface of the substrate 100 on the first region I.

[0120] Referring to Figure 20 , in an embodiment, a buried layer 110 including a base portion 112 and an extension portion 114 is formed on the substrate 100.

[0121] For example, a heat treatment process such as an annealing process is performed on Figure 19 the initial buried layer 110p. As a result, impurity atoms doped into the initial buried layer 110p may diffuse, resulting in the formation of the base portion 112. In addition, impurity atoms doped in the initial buried layer 110p diffuse into the upper part of the first region I where the initial buried layer 110p is not formed, resulting in the formation of the extension portion 114. The heat treatment process may be performed immediately after the initial buried layer 110p is formed, but embodiments of the present disclosure are not necessarily limited thereto. Those skilled in the art to which the present disclosure pertains will understand that the heat treatment process may also be performed during a subsequent stage or after a subsequent stage.

Claims

1. A semiconductor device comprising: a substrate comprising a first region and a second region surrounding the first region; an epitaxial layer disposed in the first region and the second region, wherein the epitaxial layer has a first conductivity type; a buried layer disposed below the epitaxial layer, wherein the buried layer has a second conductivity type different from the first conductivity type; a first high-concentration impurity region disposed on the epitaxial layer in the first region, wherein the first high-concentration impurity region overlaps a top surface of the epitaxial layer and has the first conductivity type; a second high-concentration impurity region disposed on the epitaxial layer in the first region, wherein the second high-concentration impurity region overlaps a top surface of the epitaxial layer and has the second conductivity type; a device isolation film disposed on the epitaxial layer between the first high-concentration impurity region and the second high-concentration impurity region, wherein the device isolation film is disposed adjacent to the second high-concentration impurity region; a drift region disposed on the epitaxial layer below the device isolation film and the second high-concentration impurity region, wherein the drift region has the second conductivity type; a high voltage well disposed on the epitaxial layer below the drift region, wherein the high voltage well has the second conductivity type; a third high-concentration impurity region disposed on the epitaxial layer in the second region, wherein the third high-concentration impurity region overlaps a top surface of the epitaxial layer and has the second conductivity type; and an isolation well located in the epitaxial layer in the second region, wherein the isolation well connects the buried layer and the third high-concentration impurity region and has the second conductivity type, Wherein, the impurity concentration of the high voltage well is lower than the impurity concentration of the isolation well.

2. The semiconductor device according to claim 1, wherein At least a portion of the high voltage well overlaps with the second high concentration impurity region in a direction intersecting with a top surface of the substrate.

3. The semiconductor device according to claim 1, wherein The impurity concentration of the drift region is lower than the impurity concentration of the second high-concentration impurity region.

4. The semiconductor device according to claim 1, wherein The impurity concentration of the high voltage well is lower than the impurity concentration of the second high-concentration impurity region.

5. The semiconductor device according to claim 1, wherein The same voltage is applied to the first high-concentration impurity region and the third high-concentration impurity region.

6. The semiconductor device according to claim 1, wherein The third high-concentration impurity region surrounds the epitaxial layer in the first region.

7. The semiconductor device according to claim 1, further comprising: A gate electrode is provided on the epitaxial layer between the first high-concentration impurity region and the second high-concentration impurity region, wherein the gate electrode is adjacent to the first high-concentration impurity region.

8. The semiconductor device according to claim 7, wherein: The same voltage is applied to the first high-concentration impurity region and the gate electrode.

9. The semiconductor device according to claim 1, wherein: The buried layer includes a base portion and an extension portion, the base portion being located below the first high-concentration impurity region, the extension portion extending from the base portion and being located below the high voltage well, and The extension portion has an impurity concentration lower than an impurity concentration of the base portion.

10. The semiconductor device according to claim 1, wherein The second high-concentration impurity region surrounds the first high-concentration impurity region.

11. The semiconductor device according to claim 1, wherein The isolation well comprises a first sub-isolation well and a second sub-isolation well, the first sub-isolation well is connected to the buried layer, the second sub-isolation well connects the first sub-isolation well and the third high-concentration impurity region, and An impurity concentration of the high voltage well is lower than an impurity concentration of the second sub-isolation well.

12. A semiconductor device comprising: substrate; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a first conductivity type; a buried layer disposed below the epitaxial layer, wherein the buried layer has a second conductivity type different from the first conductivity type; a first high-concentration impurity region disposed on the epitaxial layer, wherein the first high-concentration impurity region overlaps with a top surface of the epitaxial layer and has the first conductivity type; a second high-concentration impurity region disposed on the epitaxial layer, wherein the second high-concentration impurity region overlaps with a top surface of the epitaxial layer and has the second conductivity type; a device isolation film disposed on the epitaxial layer between the first high-concentration impurity region and the second high-concentration impurity region, wherein the device isolation film is adjacent to the second high-concentration impurity region; a drift region disposed on the epitaxial layer below the device isolation film and the second high-concentration impurity region, wherein the drift region has the second conductivity type; and a high voltage well disposed on the epitaxial layer below the drift region, wherein the high voltage well has the second conductivity type, The buried layer includes a base portion and an extension portion, the base portion is located below the first high-concentration impurity region, the extension portion extends from the base portion and is located below the high voltage well, and The extension portion has an impurity concentration lower than an impurity concentration of the base portion.

13. The semiconductor device according to claim 12, wherein: The thickness of the extension portion decreases as the distance from the base portion increases.

14. The semiconductor device according to claim 12, wherein: The impurity concentration of the extension portion decreases as the distance from the base portion increases.

15. The semiconductor device according to claim 12, further comprising: A gate electrode is provided on the epitaxial layer between the first high-concentration impurity region and the second high-concentration impurity region, wherein the gate electrode is adjacent to the first high-concentration impurity region.

16. The semiconductor device according to claim 15, wherein: The same voltage is applied to the first high-concentration impurity region and the gate electrode.

17. The semiconductor device according to claim 12, wherein: The second high-concentration impurity region surrounds the first high-concentration impurity region.

18. A semiconductor device comprising: a substrate comprising a first region and a second region surrounding the first region; A P-type epitaxial layer is disposed in the first region and the second region; An N-type buried layer, which is arranged below the P-type epitaxial layer; A P-type high-concentration impurity region disposed on the P-type epitaxial layer in the first region, wherein the P-type high-concentration impurity region overlaps with a top surface of the P-type epitaxial layer; a first N-type high-concentration impurity region disposed on the P-type epitaxial layer in the first region, wherein the first N-type high-concentration impurity region overlaps with a top surface of the P-type epitaxial layer; a device isolation film, which is disposed on the P-type epitaxial layer between the P-type high-concentration impurity region and the first N-type high-concentration impurity region, wherein the device isolation film is adjacent to the first N-type high-concentration impurity region; a gate electrode disposed on the P-type epitaxial layer between the P-type high-concentration impurity region and the first N-type high-concentration impurity region, wherein the gate electrode is adjacent to the P-type high-concentration impurity region; An N-type drift region is disposed on the P-type epitaxial layer below the device isolation film and the first N-type high-concentration impurity region; An N-type high voltage well, which is arranged on the P-type epitaxial layer below the N-type drift region; a second N-type high-concentration impurity region disposed on the P-type epitaxial layer in the second region, wherein the second N-type high-concentration impurity region is located between top surfaces of the P-type epitaxial layer; and an N-type isolation well disposed in the P-type epitaxial layer in the second region, wherein the N-type isolation well connects the N-type buried layer and the second N-type high-concentration impurity region, Wherein, the impurity concentration of the N-type high voltage well is lower than the impurity concentration of the N-type isolation well, The N-type buried layer includes a base portion and an extension portion, the base portion is located below the P-type high-concentration impurity region, the extension portion extends from the base portion and is located below the high voltage well, and The extension portion has an impurity concentration lower than an impurity concentration of the base portion.

19. The semiconductor device according to claim 18, wherein: A ground voltage is applied to the P-type high-concentration impurity region, the gate electrode, and the second N-type high-concentration impurity region.

20. The semiconductor device according to claim 18, wherein The first N-type high-concentration impurity region surrounds the P-type high-concentration impurity region.

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